WM2637 Dual 10-Bit Serial Input Voltage Output DAC with Internal Reference Production Data, Rev 1.0, July 1999 DESCRIPTION FEATURES • • • • • Dual 10-bit voltage output DAC Single 2.7V to 5.5V supply DNL ± 0.1 LSBs, INL ± 0.4 LSBs Internal programmable voltage reference Low power consumption: • 5.5 mW, slow mode - 5V supply • 3.3 mW, slow mode - 3V supply TM TM TMS320, (Q) SPI , and Microwire compatible serial interface Programmable settling time of 1µ µ s or 3.5µ µ s typical Power down mode 10nA • • • APPLICATIONS • • • • • • • The WM2637 is a dual 10-bit voltage output, resistor string, digitalto-analogue converter. A software controlled power down mode is provided that reduces current consumption to 10nA. The WM2637 features an internal programmable voltage reference simplifying overall system design. A reference voltage may also be supplied externally. The device has been designed to interface efficiently to industry standard microprocessors and DSPs, including the TMS320 family. The WM2637 is programmed with a 16-bit serial word comprising of a latch address, mode DAC control bits and DAC or control data. Excellent performance is delivered with a typical DNL of 0.1 LSBs. The programmable settling time allows the designer to optimize speed versus power consumption. The output stage is buffered by a x2 gain near rail-to-rail amplifier. Battery powered test instruments Digital offset and gain adjustment Battery operated/remote industrial controls Machine and motion control devices Wireless telephone and communication systems Speech synthesis Arbitrary waveform generation The device is available in an 8-pin SOIC package ideal for spacecritical applications. Commercial temperature (0° to 70°C) and industrial temperature (-40° to 85 °C) variants are supported. ORDERING INFORMATION DEVICE TEMP. RANGE PACKAGE WM2637CD 0° to 70°C 8-pin SOIC WM2637ID -40° to 85°C 8-pin SOIC BLOCK DIAGRAM TYPICAL PERFORMANCE VDD (8) 0.2 c 5V = VDD, VREF = External, Speed = Slow mode, Load = 10k/100pF REFERENCE OUTPUT BUFFER WITH OUPUT ENABLE REF(6) X1 0.15 1.024V/2.048V SELECTABLE REFERENCE 0.1 DIN (1) SCLK (2) 16-BIT SHIFT REGISTER AND CONTROL LOGIC NCS (3) 10-BIT DAC A LATCH REFERENCE INPUT BUFFER X1 DAC OUTPUT BUFFER X2 (4) OUTA 0 -0.05 REFERENCE INPUT BUFFER X1 10-BIT DAC B HOLDING LATCH DNL - LSB 0.05 2-BIT REFERENCE SELECT LATCH 10-BIT DAC B LATCH -0.1 DAC OUTPUT BUFFER X2 (7) OUTB -0.15 -0.2 0 POWER-ON RESET 2-BIT CONTROL LATCH 256 512 767 1023 DIGITAL CODE POWERDOWN/ SPEED CONTROL WM2637 (5) AGND WOLFSON MICROELECTRONICS LTD Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: [email protected] http://www.wolfson.co.uk Production Data contains final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics' Terms and Conditions. Last printed 15/07/99 15:56 1999 Wolfson Microelectronics Ltd. WM2637 Production Data PIN CONFIGURATION DIN 1 8 VDD SCLK 2 7 OUT B NCS 3 6 REF OUT A 4 5 AGND PIN DESCRIPTION PIN NO NAME TYPE 1 DIN Digital input Serial data input. DESCRIPTION 2 SCLK Digital input Serial clock input. 3 NCS Digital input Chip select. This pin is active low. 4 OUTA Analogue output 5 AGND Supply 6 REF Analogue I/O 7 OUTB Analogue output 8 VDD Supply DAC A analogue output. Analogue ground. Reference voltage input/output. DAC B analogue output Positive power supply. ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. CONDITION MIN MAX Supply voltage, VDD to AGND 7V Digital input voltage -0.3V VDD + 0.3V Reference input voltage -0.3V VDD + 0.3V WM2637CD 0°C WM2637ID -40°C 70°C 85°C -65°C 150°C Operating temperature range, TA Storage temperature Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds 260°C RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL Supply voltage VDD TEST CONDITIONS 2.7 High-level digital input voltage VIH VDD = 5V Low-level digital input voltage VIL VDD = 5V Reference voltage to REF MIN CL Serial Clock Rate FSCLK Operating free-air temperature WOLFSON MICROELECTRONICS LTD TA UNIT 5.5 V 0.8 V V VDD - 1.5 RL Load capacitance MAX 2 VREF Load resistance TYP 2 V kΩ 100 20 WM2637CD 0 70 °C WM2637ID -40 85 °C PD Rev 1.0 July 99 2 WM2637 Production Data Note: Reference voltages greater than VDD/2 will cause saturation for large DAC codes. ELECTRICAL CHARACTERISTICS Test Conditions: RL = 10kΩ, CL = 100pF. VDD = 5V ± 10%, VREF = 2.048V and VDD = 3V ± 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Static DAC Specifications Resolution 10 bits Integral non-linearity INL See Note 1 ±0.4 ±1.0 LSB Differential non-linearity DNL See Note 2 ±0.1 ±0.5 LSB Zero code error ZCE See Note 3 ±24 mV GE See Note 4 ±0.6 % FSR DC PSRR See Note 5 0.5 mV/V Zero code error temperature coefficient See Note 6 10 ppm/°C Gain error temperature coefficient See Note 6 10 ppm/°C Gain error D.c. power supply rejection ratio DAC Output Specifications Output voltage range 0 Output load regulation 2kΩ to 10kΩ load See Note 7 VDD - 0.1 V ±0.1 ±0.25 % 2.0 4.2 2.5 5.0 mA mA 1.7 3.8 2.1 4.6 mA mA 1.7 3.7 2.2 4.6 mA mA 1.4 3.4 1.8 4.2 mA mA 0.01 10 µA Power Supplies Active supply current IDD Power down supply current No load, VIH = VDD, VIL = 0V VDD = 5V, VREF = 2.048V, Internal Slow Fast VDD = 5V, VREF = 2.048V, External Slow Fast VDD = 3V, VREF = 1.024V, Internal Slow Fast VDD = 3V, VREF = 1.024V, External Slow Fast See Note 8 No load, all digital inputs 0V or VDD See Note 9 Dynamic DAC Specifications Slew rate DAC code 32 to 1023, 10%-90% Slow Fast See Note 10 DAC code 32 to 1023 Slow Fast See Note 11 Code 511 to 512 Settling time Glitch energy Signal to noise ratio Signal to noise and distortion ratio WOLFSON MICROELECTRONICS LTD 1.5 8.0 V/µs V/µs 3.5 1.0 µs µs 10 nV-s SNR fs = 400ksps, fOUT = 1kHz, BW = 20kHz See Note 12 53 56 dB SNRD fs = 400ksps, fOUT = 1kHz, BW = 20kHz 50 54 dB PD Rev 1.0 July 99 3 WM2637 Production Data Test Conditions: RL = 10kΩ, CL = 100pF. VDD = 5V ± 10%, VREF = 2.048V and VDD = 3V ± 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT -61 -50 dB See Note 12 Total harmonic distortion Spurious free dynamic range THD SPFDR fs = 400ksps, fOUT = 1kHz, BW = 20kHz See Note 12 fs = 400ksps, fOUT = 1kHz, BW = 20kHz See Note 12 51 62 dB 10 MΩ Reference Configured As Input Reference input resistance RREFIN Reference input capacitance CREFIN Reference feedthrough VREF = 1VPP at 1kHz + 1.024V dc, DAC code 0 VREF = 0.2VPP + 1.024V dc DAC code 1024 Slow Fast Reference input bandwidth 55 pF -60 dB 1.0 1.0 MHz MHz Reference Configured As Output Low reference voltage VREFOUTL High reference voltage VREFOUTH Output source current IREFSRC Output sink current IREFSNK VDD > 4.75V 1.003 1.024 1.045 V 2.027 2.048 2.069 V 1 mA -1 mA Load Capacitance 100 PSRR -48 pF dB Digital Inputs High level input current IIH Input voltage = VDD 1 µA Low level input current IIL Input voltage = 0V -1 µA Input capacitance CI 8 pF Notes: 1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale effects of zero code and full scale errors). (excluding the 2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code. 3. Zero code error is the voltage output when the DAC input code is zero. 4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error. 5. Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error. 6. Zero code error and Gain error temperature coefficients are normalised to full scale voltage. 7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ load. It is expressed as a percentage of the full scale output voltage with a 10kΩ load. 8. IDD is measured while continuously writing code 1512 to the DAC. For VIH < VDD - 0.7V and VIL > 0.7V supply current will increase. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test. Slew rate results are for the lower value of the rising and falling edge slew rates 9. 10. 11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested. 12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency fOUT generated with a sampling frequency fs. WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 99 4 WM2637 Production Data SERIAL INTERFACE tSUCSS tDCS1 NCS tWCL tSUCS1 tWCH tSUCS2 SCLK tSUDCLK tHDCLK D15 DIN D14 D13 D12 D11 D0 Figure 1 Timing Diagram Test Conditions: RL = 10kΩ, CL = 100pF. VDD = 5V ± 10%, VREF = 2.048V and VDD = 3V ± 10%, VREF = 1.024V over recommended operating freeair temperature range (unless noted otherwise) SYMBOL TEST CONDITIONS MIN tSUCSS Setup time NCS low before SCLK low 10 ns tSUCS1 Setup time, rising edge of SCLK to rising edge of NCS, external end of write 10 ns tSUCS2 Setup time, rising edge of SCLK to falling edge of NCS, start of next write cycle 5 ns tWCL Pulse duration, SCLK high 25 ns tWCH Pulse duration, SCLK low 25 ns tSUDCLK Setup time, data ready before SCLK falling edge 10 ns tHDCLK Hold time, data held valid after SCLK falling edge 5 ns WOLFSON MICROELECTRONICS LTD TYP MAX UNIT PD Rev 1.0 July 99 5 WM2637 Production Data TYPICAL PERFORMANCE GRAPHS 1 5V = VDD, VREF = External, 2.048V, Speed = Fast mode, Load = 10k/100pF 0.8 0.6 0.4 INL - LSB 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 256 512 767 1023 Digital Code Figure 2 Integral Non-Linearity 0.4 0.4 VDD = 5V, VREF = 2V, Input Code = 0 0.35 0.35 0.3 0.3 OUTPUT VOLTAGE - V OUTPUT VOLTAGE - V VDD = 3V, VREF = 1V, Input Code = 0 0.25 0.2 0.15 0.25 0.2 0.15 0.1 0.1 0.05 0.05 0 0 0 1 2 3 4 5 6 7 8 9 0 10 1 Slow 3 4 5 6 7 8 9 Slow Fast Figure 3 Sink Current VDD = 3V 10 Fast Figure 4 Sink Current VDD = 5V 2.06 4.1 VDD = 3V, VREF = 1V, Input Code = 4095 VDD = 5V, V REF = 2V, Input Code = 4095 2.055 4.095 2.05 4.09 OUTPUT VOLTAGE - V OUTPUT VOLTAGE - V 2 ISINK - mA ISINK- mA 2.045 2.04 2.035 4.085 4.08 4.075 2.03 4.07 2.025 4.065 2.02 4.06 0 1 2 3 4 5 6 7 8 ISOURCE- mA Figure 5 Source Current VDD = 3V WOLFSON MICROELECTRONICS LTD 9 10 Slow 11 Fast 0 1 2 3 4 5 6 ISOURCE - mA 7 8 9 10 Slow 11 Fast Figure 6 Source Current VDD = 5V PD Rev 1.0 July 99 6 WM2637 Production Data DEVICE DESCRIPTION GENERAL FUNCTION The device uses a resistor string network buffered with an op amp to convert 10-bit digital data to analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and the input code according to the following relationship: ( Output voltage = 2 VREF code ) 1024 INPUT 11 1111 OUTPUT ( 1111 ) 1023 1024 2 VREF 10 : 0000 0001 10 0000 0000 2(VREF ( 2 VREF 01 1111 : 512 ) 1024 = V REF ( 1111 2 VREF 00 : 0000 0000 511 ) 1024 : ( 0001 2 VREF 0000 513 )1024 0000 1 ) 1024 0V Table 1 Binary Code Table (0V to 2VREF Output), Gain = 2 POWER ON RESET An internal power-on-reset circuit resets the DAC registers to all 0s on power-up. BUFFER AMPLIFIER The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2kΩ load with a 100pF load capacitance. SERIAL INTERFACE When chip select (NCS) is low, the input data is read into a 16-bit shift register with the input data clocked in most significant bit first. The falling edge of the SCLK input shifts the data into the input register. After 16 bits have been transferred, the next rising edge on SCLK or NCS then transfers the data to the DAC latch. When NCS is high, input data cannot be clocked into the input register (see Table 2). SERIAL CLOCK AND UPDATE RATE Figure 1 shows the device timing. The maximum serial rate is: 1 = 20MHz tWCH min + tWCL min The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC settling time to 10 bits limits the update rate for large input step transitions. fSCLKmax = SOFTWARE CONFIGURATION OPTIONS The 16 bits of data can be transferred with the sequence shown in Table 2. D11-D2 contains the 10-bit data word. D15-D12 hold the programmable options which are summarized Table 3 D15 D14 D13 D12 R1 SPD PWD R0 D11 D10 D9 D8 D7 D6 D5 D4 D3 New DAC value or control register value D2 D1 x D0 x Table 2 Serial Word Format WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 99 7 WM2637 Production Data PROGRAMMABLE SETTLING TIME Settling time is a software selectable 1µs or 3.5µs typical, to within ±0.5LSB of final value. This is controlled by the value of D14. A ONE defines a settling time of 1µs, a ZERO defines a settling time of 3.5µs. PROGRAMMABLE POWER DOWN The power down function is controlled by D13. A ZERO configures the device as active, or fully powered up, a ONE configures the device into power down mode. When the power down function is released the device reverts back to the DAC code set prior to power down. REGISTER ADDRESSING A separate internal control register is available. This is accessed from the register access bits R1 (Bit D15) and R0 (Bit D12). R1 R0 (BIT D15) (BIT D12) REGISTER 0 0 Write data to DAC B and BUFFER 0 1 Write data to BUFFER 1 0 Write data to DAC A and update DAC B with BUFFER content 1 1 Write data to control register Table 3 Programmable Options The contents of the control register, shown below in Table 4, are used to program the internal reference function D11 x D10 x D9 x D8 x D7 x D6 x D5 x D4 x D3 x D2 X D1 D0 REF1 REF0 Table 4 Control Register Contents PROGRAMMABLE INTERNAL REFERENCE The reference can be sourced internally or externally under software control. If an external reference voltage is applied to the REF pin, the device must be configured to accept this. If an external reference is selected, the reference voltage input is buffered which makes the DAC input resistance independent of code. The REF pin has an input resistance of 10MΩ and an input capacitance of typically 55pF. The reference voltage determines the DAC full-scale output. If an internal reference is selected, a voltage of 1.024V or 2.048V is available. The internal reference can source up to 1mA and can therefore be used as an external system reference. REF1 REF0 (BIT D1) (BIT D0) 0 0 1 1 0 1 0 1 REGISTER External 1.024V 2.048V External Table 5 Internal Reference Options Examples: 1. D15 1 2. D15 0 Set internal reference voltage to 2.048V D14 x D13 0 D12 1 D11 x D10 x D9 x D8 x D7 x D6 x D5 x D4 x D3 x D2 x D1 1 D0 0 D4 D3 D2 D1 x D0 x Write new DAC A value and update DAC A output D14 x WOLFSON MICROELECTRONICS LTD D13 0 D12 0 D11 D10 D9 D8 D7 D6 D5 New DAC A output value PD Rev 1.0 July 99 8 WM2637 Production Data FUNCTION OF THE LATCH CONTROL BITS (D15 AND D12) PURPOSE AND USE OF THE DOUBLE BUFFER Normally only one DAC output can change after a write. The double buffer allows both DAC outputs to change after a single write. This is achieved by the two following steps. 1. A double buffer only write is executed to store the new DAC B data without changing the DAC A and B outputs. 2. Following the previous step, a write to latch A is executed. This writes the serial interface register (SIR) data to latch A and also writes the double buffer contents to latch B. Thus both DACs receive their new data at the same time and so both DAC outputs begin to change at the same time. Unless a double buffer only write is issued, the latch B and double buffer contents are identical. Thus, following a write to latch A or B with another write to latch A does not change the latch B contents. Three data transfer options are possible. All transfers occur immediately after NCS goes high (or on the sixteenth positive SCLK edge, whichever is earlier) and are described in the following sections). LATCH A WRITE, LATCH B UPDATE (D15 = HIGH, D12 = LOW) The serial interface register (SIR) data are written to latch A and the double buffer latch contents are written to latch B. The double buffer contents are unaffected. This program bit condition allows simultaneous output updates of both DACs. SERIAL INTERFACE REGISTER D12 = LOW D15 = HIGH DOUBLE BUFFER LATCH LATCH A TO DAC A LATCH B TO DAC B Figure 7 Latch A Write, Latch B Update LATCH B AND DOUBLE BUFFER 1 WRITE (D15 = LOW, D12 = LOW) The SIR data are written to both latch B and the double buffer. Latch A is unaffected. SERIAL INTERFACE REGISTER D12 = LOW D15 = LOW DOUBLE BUFFER LATCH LATCH A TO DAC A LATCH B TO DAC B Figure 8 Latch B and Double Buffer Write WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 99 9 WM2637 Production Data DOUBLE BUFFER ONLY WRITE (D15 = LOW, D12 = HIGH) The SIR data are written to the double buffer only. Latch A and B contents are unaffected. SERIAL INTERFACE REGISTER D12 = HIGH D15 = LOW DOUBLE BUFFER LATCH A TO DAC A LATCH B TO DAC B Figure 9 Double Buffer Only Write OPERATIONAL EXAMPLES 1. changing the latch A data from zero to full code Assuming that latch A starts at zero code (e.g. after power up), the latch can be filled with 1s by writing (bit D15 on the left, D0 on the right) 1X00 1111 1111 11xx to the serial interface. Bit D14 can be zero to select slow mode or one to select fast mode. The latch B contents and DAC B output are not changed by this write unless the double buffer contents are different from the latch B contents. This can only be true if the last write was a double buffer-only write. 2. changing the latch B data from zero to full code Assuming that latch B starts at zero code (e.g. after power up), the latch can be filled with 1s by writing (bit D15 on the left, D0 on the right) 0X00 1111 1111 11xx to the serial interface. Bit D14 can be zero to select slow mode or one to select fast mode. The data (bits D2 to D11) are written to both the double buffer and latch B. The latch A contents and the DAC A output are not changed by this write. 3. double buffered change of both DAC outputs Assuming that DACs A and B start at zero code (e.g. after power up), if DAC A is to be driven to mid-scale and DAC B to full-scale, and if the outputs are to begin rising at the same time, this can be achieved as follows: First, 0d01 1111 1111 11xx is written (bit D15 on the left, D0 on the right) to the serial interface. This loads the full-scale code into the double buffer but does not change the latch B contents and the DAC B output voltage. The latch A contents and the DAC A output are also unaffected by this write operation. Changing from fast to slow to fast mode changes the supply current which can glitch the outputs, and so D14 (designated by d in the above data word) should be set to maintain the speed mode set by the previous write. Next, 1d00 1000 0000 00xx is written (bit D15 on the left, D0 on the right) to the serial interface. This writes the mid-scale code (1000000000) to latch A and also copies the full-scale code from the double buffer to latch B. Both DAC outputs thus begin to rise after the second write. WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 99 10 WM2637 Production Data PACKAGE DIMENSIONS D: 8 PIN SOIC 3.9mm Wide Body DM009.B B e 8 5 E 1 H L 4 D h x 45o A A1 -C- 0.10 (0.004) Symbols A A1 B C D e E h H L α REF: Dimensions (mm) MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 1.27 BSC 3.80 4.00 0.25 0.50 5.80 6.20 0.40 1.27 0o 8o α C SEATING PLANE Dimensions (Inches) MIN MAX 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.1890 0.1968 0.050 BSC 0.1497 0.1574 0.0099 0.0196 0.2284 0.2440 0.0160 0.0500 0o 8o JEDEC.95, MS-012 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-012, VARIATION = AA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. WOLFSON MICROELECTRONICS LTD PD Rev 1.0 July 99 11