X9408
®
Low Noise/Low Power/2-Wire Bus
Data Sheet
September 19, 2005
Quad Digitally Controlled (XDCP™)
Potentiometers
DESCRIPTION
The X9408 integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.
FEATURES
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FN8191.2
Four potentiometers in one package
64 resistor taps per potentiometer
2-wire serial interface
Wiper resistance, 40Ω typical at 5V
Four nonvolatile data registers for each pot
Nonvolatile storage of wiper position
Standby current < 1µA max (total package)
VCC = 2.7V to 5.5V operation
V+ = 2.7V to 5.5V
V- = –2.7V to -5.5V
10kΩ, 2.5kΩ end to end resistances
High reliability
—Endurance–100,000 data changes per bit per
register
—Register data retention–100 years
24 Ld SOIC, 24 Ld TSSOP, 24 Ld PDIP packages
Pb-free plus anneal available (RoHS compliant)
The digital controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and four
non-volatile Data Registers that can be directly written
to and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
though the switches. Powerup recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC
V+
VSS
V-
Pot 0
R0 R1
R2 R3
WP
SCL
SDA
A0
A1
A2
A3
Interface
and
Control
Circuitry
VH0/RH0
Wiper
Counter
Register
(WCR)
VL0/RL0
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 2
VH2/RH2
VL2/RL2
VW0/RW0
VW2/RW2
VW1/RW1
VW3/RW3
8
Data
R0 R1
R2 R3
1
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
VH1/RH1
VL1/RL1
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 3
VH3/RH3
VL3/RL3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9408
Ordering Information
PART NUMBER
POTENTIOMETER
ORGANIZATION
(kΩ)
PART MARKING VCC LIMITS (V)
X9408YP24
5 ±10%
2.5
TEMP RANGE
(°C)
PACKAGE
0 to 70
24 Ld PDIP
X9408YS24*
0 to 70
24 Ld SOIC (300 mil)
X9408YS24I*
-40 to 85
24 Ld SOIC (300 mil)
X9408YV24*
X9408YV
0 to 70
24 Ld TSSOP (4.4mm)
X9408YV24Z* (Note)
X9408YV Z
0 to 70
24 Ld TSSOP (4.4mm) (Pb-free)
X9408YV24I*
X9408YV I
-40 to 85
24 Ld TSSOP (4.4mm)
X9408YV24IZ* (Note)
X9408YV Z I
-40 to 85
24 Ld TSSOP (4.4mm) (Pb-free)
X9408WP24
10
X9408WP24I
0 to 70
24 Ld PDIP
-40 to 85
24 Ld PDIP
X9408WS24*
X9408WS
0 to 70
24 Ld SOIC (300 mil)
X9408WS24I*
X9408WS I
-40 to 85
24 Ld SOIC (300 mil)
X9408WV24*
X9408WV
0 to 70
24 Ld TSSOP (4.4mm)
X9408WV24Z* (Note)
X9408WV Z
0 to 70
24 Ld TSSOP (4.4mm) (Pb-free)
X9408WV24I*
X9408WV I
-40 to 85
24 Ld TSSOP (4.4mm)
X9408WV24IZ* (Note)
X9408WV Z I
-40 to 85
24 Ld TSSOP (4.4mm) (Pb-free)
-40 to 85
24 Ld PDIP
X9408YP24I-2.7
2.7 to 5.5
2.5
X9408YS24-2.7*
0 to 70
24 Ld SOIC (300 mil)
X9408YS24I-2.7*
-40 to 85
24 Ld SOIC (300 mil)
X9408YV24-2.7*
X9408YV F
0 to 70
24 Ld TSSOP (4.4mm)
X9408YV24Z-2.7* (Note)
X9408YV Z F
0 to 70
24 Ld TSSOP (4.4mm) (Pb-free)
X9408YV24I-2.7*
X9408YV G
X9408YV24IZ-2.7T1 (Note) X9408YV Z G
X9408WP24-2.7
10
X9408WP24I-2.7
-40 to 85
24 Ld TSSOP (4.4mm)
-40 to 85
24 Ld TSSOP (4.4mm) Tape and Reel
(Pb-free)
0 to 70
24 Ld PDIP
-40 to 85
24 Ld PDIP
X9408WS24-2.7*
X9408WS F
0 to 70
24 Ld SOIC (300 mil)
X9408WS24I-2.7*
X9408WS G
-40 to 85
24 Ld SOIC (300 mil)
-40 to 85
24 Ld SOIC (300 mil)
X9408WSI-2.7
X9408WV24-2.7*
X9408WV F
0 to 70
24 Ld TSSOP (4.4mm)
X9408WV24Z-2.7* (Note)
X9408WV Z F
0 to 70
24 Ld TSSOP (4.4mm) (Pb-free)
X9408WV24I-2.7*
X9408WV G
-40 to 85
24 Ld TSSOP (4.4mm)
X9408WV24IZ-2.7* (Note)
X9408WV Z G
-40 to 85
24 Ld TSSOP (4.4mm) (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN8191.2
September 19, 2005
X9408
PIN DESCRIPTIONS
VW/RW (VW0/RW0 – VW3/RW3)
Host Interface Pins
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9408.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.
Hardware Write Protect Input (WP)
The WP pin when low prevents nonvolatile writes to
the Data Registers.
Analog Supplies V+, VThe Analog Supplies V+, V- are the supply voltages
for the XDCP analog section.
PIN NAMES
Symbol
Description
SCL
Serial Clock
SDA
Serial Data
The address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9408. A maximum of 16 devices may occupy the
2-wire serial bus.
A0-A3
Device Address
VH0/RH0 - VH3/RH3,
VL0/RL0 - VL3/RL3
Potentiometer Pins
(terminal equivalent)
VW0/RW0 - VW3/RW3
Potentiometer Pins
(wiper equivalent)
WP
Hardware Write Protection
Potentiometer Pins
V+,V-
Analog Supplies
VH/RH (VH0/RH0 - VH3/RH3), VL/RL (VL0/RL0 - VL3/RL3)
VCC
System Supply Voltage
The VH/RH and VL/RL inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
VSS
System Ground
NC
No Connection
Device Address (A0 - A3)
PIN CONFIGURATION
DIP/SOIC
TSSOP
VCC
1
24
V+
VL0/RL0
2
23
VL3/RL3
SDA
1
24
WP
A1
2
23
VL1/RL1
VH1/RH1
3
22
A2
VW0/RW0
4
VH0/RH0
3
22
VH3/RH3
VW0/RW0
4
21
VW3/RW3
21
VH0/RH0
A2
5
20
A0
VW1/RW1
5
20
VL0/RL0
WP
6
19
NC
VSS
6
19
VCC
SDA
7
18
A3
V-
7
18
V+
A1
8
17
SCL
VW2/RW2
8
17
VL3/RL3
VL1/RL1
9
16
VL2/RL2
VH2/RH2
9
16
VH3/RH3
VH1/RH1
10
15
VH2/RH2
VL2/RL2
10
15
VW3/RW3
VW1/RW1
11
14
VW2/RW2
SCL
11
14
A0
12
13
A3
12
13
NC
V
SS
X9408
3
V-
X9408
FN8191.2
September 19, 2005
X9408
PRINCIPLES OF OPERATION
The X9408 is a highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9408 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9408 will be considered a
slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (tLOW). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
The X9408 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9408 will respond with a final acknowledge.
Array Description
The X9408 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RLinputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(RW) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six bits of the WCR are decoded to select, and enable,
one of sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers
and the WCR can be read and written by the host
system.
All commands to the X9408 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (tHIGH). The X9408 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.
Device Addressing
Stop Condition
Figure 1. Slave Address
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9408
this is fixed as 0101[B].
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
Acknowledge
Device Type
Identifier
0
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
4
1
0
1
A3
A2
A1
A0
Device Address
The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A0 - A3 inputs. The X9408 compares
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9408 to respond with an acknowledge. The
A0 - A3 inputs can be actively driven by CMOS input
signals or tied to VCC or VSS.
FN8191.2
September 19, 2005
X9408
Figure 2. Instruction Byte Format
Acknowledge Polling
The disabling of the inputs, during the internal
Nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9408
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9408 is still busy with the write operation no ACK will
be returned. If the X9408 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.
Flow 1. ACK Polling Sequence
Nonvolatile Write
Command Completed
Enter ACK Polling
Issue
START
Issue Slave
Address
ACK
Returned?
Issue STOP
NO
YES
Further
Operation?
NO
YES
Issue
Instruction
Issue STOP
Proceed
Proceed
Register
Select
I3
I2
I1
Instructions
I0
R1
R0
P1
P0
Wiper Counter
Register Select
The four high order bits define the instruction. The
next two bits (R1 and R0) select one of the four
registers that is to be acted upon when a register
oriented instruction is issued. The last bits (P1, P0)
select which one of the four potentiometers is to be
affected by the instruction.
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is
illustrated in Figure 3. These two-byte instructions
exchange data between the Wiper Counter Register
and one of the Data Registers. A transfer from a Data
Register to a Wiper Counter Register is essentially a
write to a static RAM. The response of the wiper to this
action will be delayed tWRL. A transfer from the Wiper
Counter Register (current wiper position), to a data
register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein
the transfer occurs between all of the potentiometers
and one of their associated registers.
Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9408; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are: Read Wiper Counter Register (read the current
wiper position of the selected pot), Write Wiper
Counter Register (change current wiper position of the
selected pot), Read Data Register (read the contents
of the selected nonvolatile register) and Write Data
Register (write a new value to the selected Data
Register). The sequence of operations is shown in
Figure 4.
Instruction Structure
The next byte sent to the X9408 contains the instruction
and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the two pots and when applicable they
point to one of four associated registers. The format is
shown below in Figure 2.
5
FN8191.2
September 19, 2005
X9408
Figure 3. Two-Byte Instruction Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9408 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
(tHIGH) while SDA is HIGH, the selected wiper will
I2
I1
I0
R1 R0 P1 P0
A
C
K
S
T
O
P
move one resistor segment towards the RH terminal.
Similarly, for each SCL clock pulse while SDA is LOW,
the selected wiper will move one resistor segment
towards the RL terminal. A detailed illustration of the
sequence and timing for this operation are shown in
Figures 5 and 6 respectively.
Table 1. Instruction Set
I3
1
I2
0
Instruction Set
I1 I0 R1 R0
0
1
0
0
1
0
1
0
0
0
P1
P0
1
0
1
1
R1
R0
P1
P0
Write Data Register
1
1
0
0
R1
R0
P1
P0
XFR Data Register to
Wiper Counter Register
1
1
0
1
R1
R0
P1
P0
XFR Wiper Counter
Register to Data
Register
Global XFR Data Registers to Wiper Counter
Registers
Global XFR Wiper
Counter Registers to
Data Register
Increment/Decrement
Wiper Counter Register
1
1
1
0
R1
R0
P1
P0
0
0
0
1
R1
R0
0
0
1
0
0
0
R1
R0
0
0
0
0
1
0
0
0
P1
P0
Instruction
Read Wiper Counter
Register
Write Wiper Counter
Register
Read Data Register
Note:
P1
P1
P0
P0
Operation
Read the contents of the Wiper Counter Register
pointed to by P1 - P0
Write new value to the Wiper Counter Register pointed
to by P1 - P0
Read the contents of the Data Register pointed to by
P1 - P0 and R1 - R0
Write new value to the Data Register pointed to by
P1 - P0 and R1 - R0
Transfer the contents of the Data Register pointed to
by P1 - P0 and R1 - R0 to its associated Wiper Counter
Register
Transfer the contents of the Wiper Counter Register
pointed to by P1 - P0 to the Data Register pointed to
by R1 - R0
Transfer the contents of the Data Registers pointed to by
R1 - R0 of all four pots to their respective Wiper Counter
Registers
Transfer the contents of both Wiper Counter Registers
to their respective Data Registers pointed to by
R1 - R0 of all four pots
Enable Increment/decrement of the Wiper Counter
Register pointed to by P1 - P0
(7) 1/0 = data is one or zero
6
FN8191.2
September 19, 2005
X9408
Figure 4. Three-Byte Instruction Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0 A
C
K
I3
I2
I1 I0
R1 R0 P1 P0 A
C
K
0
0
D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
Figure 5. Increment/Decrement Instruction Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3
I2
I1
I0
R1 R0 P1 P0
A
C
K
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
S
T
O
P
Figure 6. Increment/Decrement Timing Limits
INC/DEC
CMD
Issued
tWRID
SCL
SDA
Voltage Out
VW/RW
7
FN8191.2
September 19, 2005
X9408
Figure 7. Acknowledge Response from Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
Acknowledge
START
Figure 8. Detailed Potentiometer Block Diagram
Serial Data Path
Serial
Bus
Input
From Interface
Circuitry
Register 0
Register 1
8
Register 2
If WCR = 00[H] then VW/RW = VL/RL
If WCR = 3F[H] then VW/RW = VH/RH
6
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
Register 3
VH/RH
C
o
u
n
t
e
r
D
e
c
o
d
e
INC/DEC
Logic
UP/DN
Modified SCL
UP/DN
CLK
VL/RL
VW/RW
8
FN8191.2
September 19, 2005
X9408
DETAILED OPERATION
All XDCP potentiometers share the serial interface
and share a common architecture. Each potentiometer
has a Wiper Counter Register and four Data
Registers. A detailed discussion of the register
organization and array operation follows.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.
Register Descriptions
Data Registers, (6-Bit), Nonvolatile
Wiper Counter Register
The X9408 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The Wiper Counter
Register can be envisioned as a 6-bit parallel and
serial load counter with its outputs decoded to select
one of sixty-four switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/ Decrement
instruction. Finally, it is loaded with the contents of its
data register zero (DR0) upon power-up.
The WCR is a volatile register; that is, its contents are
lost when the X9408 is powered-down. Although the
register is automatically loaded with the value in R0
upon power-up, it should be noted this may be
different from the value present at power-down.
Data Registers
Each potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred between any of the
four Data Registers and the WCR. It should be noted
all operations changing data in one of these registers
is a nonvolatile operation and will take a maximum of
10ms.
9
D5
D4
D3
D2
D1
D0
NV
NV
NV
NV
NV
NV
(MSB)
(LSB)
Four 6-bit Data Registers for each XDCP. (sixteen 6bit registers in total).
– {D5~D0}: These bits are for general purpose not volatile data storage or for storage of up to four different wiper values. The contents of Data Register 0
are automatically moved to the wiper counter register on power-up.
Wiper Counter Register, (6-Bit), Volatile
WP5
WP4
WP3
WP2
WP1
WP0
V
V
V
V
V
V
(MSB)
(LSB)
One 6-bit Wiper Counter Register for each XDCP.
(Four 6-bit registers in total.)
– {D5~D0}: These bits specify the wiper position of the
respective XDCP. The Wiper Counter Register is
loaded on power-up by the value in Data Register 0.
The contents of the WCR can be loaded from any of
the other Data Register or directly. The contents of
the WCR can be saved in a DR.
FN8191.2
September 19, 2005
X9408
Instruction Format
Notes: (1)
(2)
(3)
(4)
(5)
“MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
“A3 ~ A0”: stands for the device addresses sent by the master.
“X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
“I”: stands for the increment operation, SDA held high during active SCL phase (high).
“D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register (WCR)
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
WCR
S
opcode
addresses
A
C
P P
1 0 0 1 0 0
K
1 0
wiper position
S
(sent by slave on SDA)
A
W W W W W W
C
0 0 P P P P P P
K
5 4 3 2 1 0
M
A
C
K
S
T
O
P
wiper position
S
(sent by master on SDA)
A
W W W W W W
C
K 0 0 P P P P P P
5 4 3 2 1 0
S
A
C
K
S
T
O
P
Write Wiper Counter Register (WCR)
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
WCR
S
opcode
addresses
A
C
P P
K 1 0 1 0 0 0 1 0
Read Data Register (DR)
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction DR and WCR
S
opcode
addresses
A
C
R R P P
K 1 0 1 1 1 0 1 0
wiper position/data
S
(sent by slave on SDA)
A
W W W W W W
C
0
0
P P P P P P
K
5 4 3 2 1 0
M
A
C
K
S
T
O
P
Write Data Register (DR)
S device type
device
instruction DR and WCR
S
T identifier
addresses
opcode
addresses
A
A
C
R R P P
R 0 1 0 1 A A A A
1 1 0 0
3 2 1 0 K
1 0 1 0
T
wiper position/data
S
(sent by master on SDA)
A
W W W W W W
C
0 0 P P P P P P
K
5 4 3 2 1 0
S
A
C
K
S
T HIGH-VOLTAGE
O WRITE CYCLE
P
XFR Data Register (DR) to Wiper Counter Register (WCR)
S device type
device
instruction DR and WCR
S
T identifier
addresses
opcode
addresses
A
A
C
R R P P
R 0 1 0 1 A A A A
1 1 0 1
3 2 1 0 K
1 0 1 0
T
S
A
C
K
S
T
O
P
Write Wiper Counter Register (WCR) to Data Register (DR)
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
10
instruction DR and WCR
S
opcode
addresses
A
C
R R P P
1 1 1 0
K
1 0 1 0
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
FN8191.2
September 19, 2005
X9408
Increment/Decrement Wiper Counter Register (WCR)
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
WCR
S
opcode
addresses
A
C
P P
K 0 0 1 0 0 0 1 0
increment/decrement
S
(sent by master on SDA)
A
C I/ I/
I/ I/
K D D . . . . D D
S
T
O
P
Global XFR Data Register (DR) to Wiper Counter Register (WCR)
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
DR
S
opcode
addresses
A
C
R R
K 0 0 0 1 1 0 0 0
S
A
C
K
S
T
O
P
Global XFR Wiper Counter Register (WCR) to Data Register (DR)
S device type
device
T identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
DR
S
opcode
addresses
A
C
R R
1 0 0 0
0 0
K
1 0
SYMBOL TABLE
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
120
11
100
Resistance (Κ)
WAVEFORM
S
A
C
K
80
60
RMIN =
VCC MAX
=1.8kΩ
IOL MIN
RMAX =
tR
CBUS
Max.
Resistance
40
20 Min.
Resistance
0
0 20 40 60
80 100 120
Bus Capacitance (pF)
FN8191.2
September 19, 2005
X9408
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SDA, SCL or any address
input with respect to VSS ......................... -1V to +7V
Voltage on V+ (referenced to VSS)........................ 10V
Voltage on V- (referenced to VSS)........................-10V
(V+) - (V-) .............................................................. 12V
Any VH/RH, VL/RL, VW/RW ............................ V- to V+
Lead temperature (soldering, 10s) .................... 300°C
IW (10s) ..............................................................±6mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Min.
0°C
-40°C
Commercial
Industrial
Max.
Device
X9408
X9408-2.7
+70°C
+85°C
Supply Voltage (VCC) Limits
5V ± 10%
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
RTOTAL
Parameter
End to end resistance tolerance
Min.
-20
Typ.
Power rating
IW
Wiper current
RW
Wiper resistance
VV+
Voltage on V+ pin
-3
150
40
V VVTERM
Voltage on V- pin
X9408
+4.5
X9408-2.7
+2.7
X9408
-5.5
X9408-2.7
-5.5
Voltage on any VH/RH, VL/RL or
VW/RW pin
V-
Noise
-120
Resolution
Unit
%
mW
mA
Ω
Ω
V
25°C, each pot
IW = ± 1mA @ V+, V- = ±3V
IW = ± 1mA @ V+, V- = ±5V
V
V
dBV
1.6
Test Condition
%
Ref: 1kHz
See Note 4
Absolute linearity (1)
-1
+1
MI(3)
V(Vwn/Rwn)(actual) V(Vwn/Rwn)(expected)(4)
Relative linearity (2)
-0.2
+0.2
MI(3)
V(Vw(n+1)/Rw(n+1)) [V(Vw(n)/Rw(n)) + MI](4)
Temperature coefficient of RTOTAL
±300
Ratiometric Temperature Coefficient
CH/CL/CW Potentiometer Capacitances
IAL
Max.
+20
50
+3
250
100
+5.5
+5.5
-4.5
-2.7
V+
VH/RH, VL/RL, VW/RW Leakage
Current
12
ppm/°C
20
10/10/25
0.1
10
ppm/°C
See Note 4
See Note 4
pF
See Macro model
µA
VIN = V- to V+. Device is in
Stand-by mode.
FN8191.2
September 19, 2005
X9408
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
ICC1
Min.
Typ.
Max.
Unit
Test Conditions
VCC supply current (nonvolatile
write)
1
mA
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
ICC2
VCC supply current (move wiper,
write, read)
100
µA
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
ISB
VCC current (standby)
1
µA
SCL = SDA = VCC, Addr. = VSS
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH voltage
VCC x 0.7
VCC +0.5
V
VIL
Input LOW voltage
–0.5
VCC x 0.1
V
VOL
Output LOW voltage
0.4
V
IOL = 3mA
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 63 or [V(VH/RH) – V(VL/RL)] / 63, single pot
ENDURANCE AND DATA RETENTION
Parameter
Min.
Unit
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
years
CAPACITANCE
Symbol
CI/O
(4)
CIN(4)
Test
Max.
Unit
Test Condition
Input/output capacitance (SDA)
8
pF
VI/O = 0V
Input capacitance (A0, A1, A2, A3, and SCL)
6
pF
VIN = 0V
POWER-UP TIMING
Symbol
tPUR
(5)
tPUW(5)
tRVCC(6)
Parameter
Max.
Unit
Power-up to initiation of read operation
1
ms
Power-up to initiation of write operation
5
ms
50
V/msec
VCC Power-up Ramp
Min.
0.2
Power-up Requirements (Power-up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First V-, then VCC and V+, and then the potentiometer pins, VH/RH,
VL/RL, and VW/RW. Voltage should not be applied to the potentiometer pins before V+ or V- is applied. The VCC
ramp rate specification should be met, and any glitches or slope changes in the VCC line should be held to <100mV if
possible. If VCC powers down, it should be held below 0.1V for more than 1 second before powering up again in order
for proper wiper register recall. Also, VCC should not reverse polarity by more than 0.5V. Recall of wiper position will
not be complete until VCC, V+ and V- reach their final value.
Notes: (4) This parameter is periodically sampled and not 100% tested
(5) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific
instruction can be issued. These parameters are periodically sampled and not 100% tested.
(6) This is not a tested or guaranteed parameter and should only be used as a guidance.
13
FN8191.2
September 19, 2005
X9408
A.C. TEST CONDITIONS
Circuit #3 SPICE Macro Model
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
RTOTAL
VH/RH
CH
VL/RL
CL
CW
10pF
EQUIVALENT A.C. LOAD CIRCUIT
10pF
25pF
5V
VW/RW
1533Ω
SDA Output
100pF
AC TIMING (over recommended operating condition)
Symbol
Parameter
Min.
Max.
Unit
400
kHz
fSCL
Clock frequency
tCYC
Clock cycle time
tHIGH
Clock high time
600
ns
tLOW
Clock low time
1300
ns
tSU:STA
Start setup time
600
ns
tHD:STA
Start hold time
600
ns
tSU:STO
Stop setup time
600
ns
tSU:DAT
SDA data input setup time
100
ns
tHD:DAT
SDA data input hold time
30
ns
2500
ns
tR
SCL and SDA rise time
300
ns
tF
SCL and SDA fall time
300
ns
tAA
SCL low to SDA data output valid time
900
ns
tDH
SDA Data output hold time
50
ns
Noise suppression time constant at SCL and SDA inputs
50
ns
1300
ns
TI
tBUF
Bus free time (prior to any transmission)
tSU:WPA
WP, A0, A1, A2 and A3 setup time
0
ns
tHD:WPA
WP, A0, A1, A2 and A3 hold time
0
ns
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
tWR
Parameter
High-voltage write cycle time (store instructions)
14
Typ.
Max.
Unit
5
10
ms
FN8191.2
September 19, 2005
X9408
XDCP TIMING
Symbol
Max.
Unit
Wiper response time after the third (last) power supply is stable
10
µs
tWRL
Wiper response time after instruction issued (all load instructions)
10
µs
tWRID
Wiper response time from an active SCL/SCK edge (increment/decrement instruction)
10
µs
tWRPO
Parameter
Min.
Notes: (9) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling
edge of SCL.
TIMING DIAGRAMS
START and STOP Timing
g
(START)
(STOP)
tR
tF
SCL
tSU:STA
tHD:STA
tSU:STO
tR
tF
SDA
Input Timing
tCYC
tHIGH
SCL
tLOW
SDA
tSU:DAT
tHD:DAT
tBUF
Output Timing
SCL
SDA
tAA
15
tDH
FN8191.2
September 19, 2005
X9408
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+VR
VR
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
VS
Voltage Regulator
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Offset Voltage Adjustment
R1
Comparator with Hysteresis
R2
VS
VS
–
+
VO
100kΩ
–
VO
+
}
}
TL072
R1
R2
10kΩ
10kΩ
+12V
10kΩ
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
-12V
16
FN8191.2
September 19, 2005
X9408
Application Circuits (continued)
Attenuator
Filter
C
VS
+
R2
R1
VS
VO
–
–
R
VO
+
R3
R4
R2
All RS = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2πRC)
V O = G VS
-1/2 ≤ G ≤ +1/2
R1
R2
}
}
Inverting Amplifier
Equivalent L-R Circuit
VS
R2
C1
–
VS
VO
+
+
–
R1
ZIN
VO = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
Function Generator
C
R2
–
+
R1
–
} RA
+
} RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
17
FN8191.2
September 19, 2005
X9408
XDCP Timing (for All Load Instructions)
(STOP)
SCL
LSB
SDA
tWRL
VWx
XDCP Timing (for Increment/Decrement Instruction)
SCL
SDA
Wiper Register Address
Inc/Dec
Inc/Dec
tWRID
VWx
Write Protect and Device Address Pins Timing
(START)
SCL
(STOP)
...
(Any Instruction)
...
SDA
...
tSU:WPA
tHD:WPA
WP
A0, A1
A2, A3
18
FN8191.2
September 19, 2005
X9408
PACKAGING INFORMATION
24-Lead Plastic Dual In-Line Package Type P
1.265 (32.13)
1.230 (31.24)
0.557 (14.15)
0.530 (13.46)
Pin 1 Index
Pin 1
0.080 (2.03)
0.065 (1.65)
1.100 (27.94)
Ref.
0.162 (4.11)
0.140 (3.56)
Seating
Plane
0.030 (0.76)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
0.065 (1.65)
0.040 (1.02)
0.022 (0.56)
0.014 (0.36)
0.625 (15.87)
0.600 (15.24)
Typ. 0.010 (0.25)
0°
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
19
FN8191.2
September 19, 2005
X9408
PACKAGING INFORMATION
24-Lead Plastic Small Outline Gull Wing Package Type S
0.290 (7.37) 0.393 (10.00)
0.299 (7.60) 0.420 (10.65)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050" Typical
0.010 (0.25)
X 45°
0.020 (0.50)
0.050"
Typical
0° - 8°
0.009 (0.22)
0.013 (0.33)
0.420"
0.015 (0.40)
0.050 (1.27)
FOOTPRINT
0.030" Typical
24 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
20
FN8191.2
September 19, 2005
X9408
PACKAGING INFORMATION
24-Lead Plastic, TSSOP Package Type V
.026 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.06)
.005 (.15)
.010 (.25)
Gage Plane
0° - 8°
(4.16) (7.72)
Seating Plane
.020 (.50)
.030 (.75)
(1.78)
Detail A (20X)
(0.42)
(0.65)
.031 (.80)
.041 (1.05)
ALL MEASUREMENTS ARE TYPICAL
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
21
FN8191.2
September 19, 2005