X9429 ® Low Noise/Low Power/2-Wire Bus Data Sheet October 19, 2005 Single Digitally Controlled Potentiometer (XDCP™) FN8248.2 DESCRIPTION The X9429 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. FEATURES • Single Voltage Potentiometer • 64 Resistor Taps • 2-wire Serial Interface for Write, Read, and Transfer Operations of the Potentiometer • Wiper Resistance, 150Ω Typical at 5V • Non-Volatile Storage of Multiple Wiper Positions • Power-on Recall. Loads Saved Wiper Position on Power-up. • Standby Current < 5µA Max • VCC : 2.7V to 5.5V Operation • 2.5kΩ, 10kΩ Total Pot Resistance • Endurance: 100, 000 Data Changes per Bit per Register • 100 yr. Data Retention • 14 Ld TSSOP, 16 Ld SOIC • Low Power CMOS • Pb-Free Plus Anneal Available (RoHS Compliant) The digital controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. BLOCK DIAGRAM VCC address data status 2-wire bus interface VH/RH write read transfer inc / dec Bus Interface & Control Wiper Counter Register (WCR) control VSS 1 Power-on Recall wiper 10kΩ 64-taps POT Data Registers 4 Bytes VL/RL VW/RW CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9429 Ordering Information PART NUMBER PART MARKING X9429WS16* X9429WS X9429WS16Z* (Note) VCC LIMITS (V) 5 ±10% POTENTIOMETER ORGANIZATION (kΩ) TEMP RANGE (°C) 10 PACKAGE 0 to 70 16 Ld SOIC (300 mil) X9429WS Z 0 to 70 16 Ld SOIC (300 mil) (Pb-free) X9429WS16I* X9429WS I -40 to 85 16 Ld SOIC (300 mil) X9429WS16IZ* (Note) X9429WS Z I -40 to 85 16 Ld SOIC (300 mil) (Pb-free) X9429WV14* X9429WV 0 to 70 14 Ld TSSOP (4.4mm) X9429WV14Z* (Note) X9429WV Z 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free) X9429WV14IZ* (Note) X9429WV Z I -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free) X9429WV14I* X9429WV I -40 to 85 14 Ld TSSOP (4.4mm) X9429YS16* X9429YS X9429YS16Z* (Note) 2.5 0 to 70 16 Ld SOIC (300 mil) X9429YS Z 0 to 70 16 Ld SOIC (300 mil) (Pb-free) X9429YS16I* X9429YS I -40 to 85 16 Ld SOIC (300 mil) X9429YS16IZ* (Note) X9429YS Z I -40 to 85 16 Ld SOIC (300 mil) (Pb-free) X9429YV14* X9429YV 0 to 70 14 Ld TSSOP (4.4mm) X9429YV14Z* (Note) X9429YV Z 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free) X9429YV14I* X9429YV I -40 to 85 14 Ld TSSOP (4.4mm) X9429YV14IZ* (Note) X9429YV Z I -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free) X9429WS16-2.7* X9429WS F X9429WS16Z-2.7* (Note) X9429WS Z F X9429WS16I-2.7* X9429WS G 2.7 to 5.5 10 X9429WS16IZ-2.7* (Note) X9429WS Z G 0 to 70 16 Ld SOIC (300 mil) 0 to 70 16 Ld SOIC (300 mil) (Pb-free) -40 to 85 16 Ld SOIC (300 mil) -40 to 85 16 Ld SOIC (300 mil) (Pb-free) X9429WV14-2.7* X9429WV F 0 to 70 14 Ld TSSOP (4.4mm) X9429WV14Z-2.7* (Note) X9429WV Z F 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free) X9429WV14I-2.7* X9429WV G X9429WV14IZ-2.7* (Note) X9429WV Z G 2.5 -40 to 85 14 Ld TSSOP (4.4mm) -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free) X9429YS16-2.7* X9429YS F 0 to 70 16 Ld SOIC (300 mil) X9429YS16Z-2.7* (Note) X9429YS Z F 0 to 70 16 Ld SOIC (300 mil) (Pb-free) X9429YS16I-2.7* X9429YS G -40 to 85 16 Ld SOIC (300 mil) X9429YS16IZ-2.7* (Note) X9429YS Z G -40 to 85 16 Ld SOIC (300 mil) (Pb-free) X9429YV14-2.7* X9429YV F 0 to 70 14 Ld TSSOP (4.4mm) X9429YV14Z-2.7* (Note) X9429YV Z F 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free) X9429YV14I-2.7* X9429YV G -40 to 85 14 Ld TSSOP (4.4mm) X9429YV14IZ-2.7* (Note) X9429YV Z G -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free) *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN8248.2 October 19, 2005 X9429 DETAILED FUNCTIONAL DIAGRAM VCC Power-on Recall DR0 DR1 Control SCL SDA A3 A2 A0 DR2 DR3 INTERFACE AND CONTROL CIRCUITRY 10kΩ 64--taps WIPER COUNTER REGISTER (WCR) RH/VH RL/VL RW/VW DATA WP VSS CIRCUIT LEVEL APPLICATIONS SYSTEM LEVEL APPLICATIONS • Vary the gain of a voltage amplifier • Provide programmable dc reference voltages for comparators and detectors • Control the volume in audio circuits • Trim out the offset voltage error in a voltage amplifier circuit • Set the output voltage of a voltage regulator • Trim the resistance in Wheatstone bridge circuits • Control the gain, characteristic frequency and Q-factor in filter circuits • Set the scale factor and zero point in sensor signal conditioning circuits • Vary the frequency and duty cycle of timer ICs • Vary the dc biasing of a pin diode attenuator in RF circuits • Provide a control variable (I, V, or R) in feedback circuits • Adjust the contrast in LCD displays • Control the power level of LED transmitters in communication systems • Set and regulate the DC biasing point in an RF power amplifier in wireless systems • Control the gain in audio and home entertainment systems • Provide the variable DC bias for tuners in RF wireless systems • Set the operating points in temperature control systems • Control the operating point for sensors in industrial systems • Trim offset and gain errors in artificial intelligent systems 3 FN8248.2 October 19, 2005 X9429 PIN CONFIGURATION SOIC TSSOP NC 1 14 VCC NC 1 16 VCC NC 2 13 RL/VL NC 2 15 NC NC 3 12 RH/VH NC 3 14 RL/VL A2 4 SCL X9429 5 11 A2 4 13 RH/VH SCL 5 12 RW/VW SDA 6 11 A3 7 10 A0 8 9 WP RW/VW 10 A3 SDA 6 9 A0 VSS 7 8 WP NC VSS X9429 PIN ASSIGNMENTS TSSOP pin SOIC pin Symbol Brief Description 1 1 NC No Connect 2 2 NC No Connect 3 3 NC No Connect 4 4 A2 Device Address for 2-wire bus. 5 5 SCL Serial Clock for 2-wire bus. 6 6 SDA Serial Data Input/Output for 2-wire bus. 7 8 VSS System Ground 8 9 WP Hardware Write Protect 9 10 A0 Device Address for 2-wire bus. 10 11 A3 11 12 RW / V W Wiper Terminal of the Potentiometer. 12 13 R H / VH High Terminal of the Potentiometer. 13 14 R L / VL Low Terminal of the Potentiometer. 14 16 VCC System Supply Voltage 15 NC No Connect 7 NC No Connect Device Address for 2-wire bus. Device Address (A0, A2, A3) PIN DESCRIPTIONS The SCL input is used to clock data into and out of the X9429. The Address inputs are used to set the least significant 3 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9429. A maximum of 8 devices may occupy the 2-wire serial bus. Serial Data (SDA) Potentiometer Pins Host Interface Pins Serial Clock (SCL) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. 4 RH/VH, RL/VL The RH/VH and RL/VL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. FN8248.2 October 19, 2005 X9429 RW/VW The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. The WP pin when low prevents nonvolatile writes to the Data Registers. The X9429 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9429 will respond with a final acknowledge. PRINCIPLES OF OPERATION Array Description The X9429 is a highly integrated microcircuit incorporating a resistor array and its associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. The X9429 is comprised of a resistor array. The array contains 63 discrete resistive segments that are connected in series. The physical ends of the array are equivalent to the fixed terminals of a mechanical potentiometer (VH/RH and VL/RL inputs). Serial Interface At both ends of the array and between each resistor segment is a CMOS switch connected to the wiper (VW/RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches. Hardware Write Protect Input WP The X9429 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9429 will be considered a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods (tLOW). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Start Condition All commands to the X9429 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (tHIGH). The X9429 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. The WCR may be written directly, or it can be changed by transferring the contents of one of four associated Data Registers into the WCR. These Data Registers and the WCR can be read and written by the host system. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (refer to Figure 1). For the X9429 this is fixed as 0101[B]. Figure 1. Slave Address Device Type Identifier 0 Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and 5 1 0 1 A3 A2 0 A0 Device Address The next four bits of the slave address are the device address. The physical device address is defined by the state of the A0, A2, and A3 inputs. The X9429 compares the serial data stream with the address input state; a successful compare of all three address bits is required for the X9429 to respond with an acknowledge. The A0, A2, and A3 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. FN8248.2 October 19, 2005 X9429 Flow 1. ACK Polling Sequence Acknowledge Polling The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms EEPROM write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9429 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9429 is still busy with the write operation no ACK will be returned. If the X9429 has completed the write operation an ACK will be returned, and the master can then proceed with the next operation. Instruction Structure The next byte sent to the X9429 contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of four associated registers. The format is shown below in Figure 2. Figure 2. Instruction Byte Format I2 I1 I0 R1 R0 Issue START Issue Slave Address ACK Returned? Issue STOP NO YES Further Operation? NO YES Register Select I3 Nonvolatile Write Command Completed Enter ACK Polling 0 Issue Instruction Issue STOP Proceed Proceed 0 Instructions The four high order bits define the instruction. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. Bits 0 and 1 are defined to be 0. Four of the seven instructions end with the transmission of the instruction byte. The basic sequence is illustrated in Figure 3. These two-byte instructions exchange data between the Wiper Counter Register and one of the Data Registers. A transfer from a Data Register to a Wiper Counter Register is essentially a write to a static RAM. The response of the wiper to this action will be delayed tWRL. A transfer from the Wiper Counter Register (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. Four instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9429; either between the host and one of the Data Registers or directly between the host and the Wiper Counter Register. These instructions are: 6 FN8248.2 October 19, 2005 X9429 Figure 3. Two-Byte Instruction Sequence SCL SDA S T A R T 0 1 0 1 A3 A2 0 A0 A C K I3 I2 I1 I0 R1 R0 0 0 A C K S T O P the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the VH/RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figures 5 and 6 respectively. Read Wiper Counter Register (read the current wiper position of the selected pot), write Wiper Counter Register (change current wiper position of the selected pot), read Data Register (read the contents of the selected nonvolatile register) and write Data Register (write a new value to the selected Data Register). The sequence of operations is shown in Figure 4. The Increment/Decrement command is different from the other commands. Once the command is issued and the X9429 has responded with an acknowledge, Table 1. Instruction Set I3 I2 Instruction Set I1 I0 R1 R0 1 0 0 1 0 1 0 1 0 0 Read Data Register 1 0 1 1 Write Data Register 1 1 0 1 1 1 0 Instruction Read Wiper Counter Register Write Wiper Counter Register XFR Data Register to Wiper Counter Register XFR Wiper Counter Register to Data Register Increment/Decrement Wiper Counter Register Note: X1 X0 0 0 0 Read the contents of the Wiper Counter Register 0 0 0 Write new value to the Wiper Counter Register 1/0 1/0 0 0 0 1/0 1/0 0 0 0 1 1/0 1/0 0 0 1 1 0 1/0 1/0 0 0 Transfer the contents of the Wiper Counter Register to the Data Register pointed to by R1 - R0 0 1 0 0 0 Enable Increment/decrement of the Wiper Counter Register 0 0 Operation Read the contents of the Data Register pointed to by R1 - R0 Write new value to the Data Register pointed to by R1 - R0 Transfer the contents of the Data Register pointed to by R1 - R0 to its Wiper Counter Register (1) 1/0 = data is one or zero 7 FN8248.2 October 19, 2005 X9429 Figure 4. Three-Byte Instruction Sequence SCL SDA S T A R T 0 1 0 1 A3 A2 0 A0 A C K I3 I2 I1 I0 R1 R0 0 0 A C K 0 0 D5 D4 D3 D2 D1 D0 A C K S T O P Figure 5. Increment/Decrement Instruction Sequence SCL SDA S T A R T 0 1 0 1 A3 A2 0 A0 A C K I3 I2 I1 I0 R1 R0 0 0 A C K I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P Figure 6. Increment/Decrement Timing Limits INC/DEC CMD Issued tWRID SCL SDA Voltage Out VW/RW 8 FN8248.2 October 19, 2005 X9429 Figure 7. Acknowledge Response from Receiver SCL from Master 1 8 9 Data Output from Transmitter Data Output from Receiver START Acknowledge Figure 8. Detailed Potentiometer Block Diagram Serial Data Path Serial Bus Input From Interface Circuitry Register 0 Register 1 8 Register 2 If WCR = 00[H] then VW/RW = VL/RL If WCR = 3F[H] then VW/RW = VH/RH 6 Parallel Bus Input Wiper Counter Register (WCR) Register 3 VH/RH C o u n t e r D e c o d e INC/DEC Logic UP/DN Modified SCL UP/DN CLK VL/RL VW/RW 9 FN8248.2 October 19, 2005 X9429 Register Descriptions DETAILED OPERATION The potentiometer has a Wiper Counter Register and four Data Registers. A detailed discussion of the register organization and array operation follows. Wiper Counter Register Data Registers, (6-Bit), Nonvolatile D5 D4 D3 D2 D1 D0 NV NV NV NV NV NV (MSB) The X9429 contains a Wiper Counter Register. The Wiper Counter Register can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty-four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/Decrement instruction. Finally, it is loaded with the contents of its Data Register zero (DR0) upon power-up. The WCR is a volatile register; that is, its contents are lost when the X9429 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, it should be noted this may be different from the value present at power-down. Data Registers The potentiometer has four nonvolatile Data Registers. These can be read or written directly by the host and data can be transferred between any of the four Data Registers and the Wiper Counter Register. It should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms. (LSB) Four 6-bit Data Registers for each XDCP. – {D5~D0}: These bits are for general purpose not volatile data storage or for storage of up to four different wiper values. The contents of Data Register 0 are automatically moved to the Wiper Counter Register on power-up. Wiper Counter Register, (6-Bit), Volatile WP5 WP4 WP3 WP2 WP1 WP0 V V V V V V (MSB) (LSB) One 6-bit wiper counter register for each XDCP. – {D5~D0}: These bits specify the wiper position of the respective XDCP. The Wiper Counter Register is loaded on power-up by the value in Data Register 0. The contents of the WCR can be loaded from any of the other Data Register or directly. The contents of the WCR can be saved in a DR. If the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. 10 FN8248.2 October 19, 2005 X9429 Instruction Format Notes: (1) (2) (3) (4) (5) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave. “A3 ~ A0”: stands for the device addresses sent by the master. “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition. “I”: stands for the increment operation, SDA held high during active SCL phase (high). “D”: stands for the decrement operation, SDA held low during active SCL phase (high). Read Wiper Counter Register (WCR) S device type device T identifier addresses A R 0 1 0 1 A A 0 A 3 2 0 T instruction wiper position S S opcode (sent by slave on SDA) A A W W W W W W C C 1 0 0 1 0 0 0 0 0 0 P P P P P P K K 5 4 3 2 1 0 M A C K S T O P instruction wiper position S S opcode (sent by master on SDA) A A W W W W W W C C 1 0 1 0 0 0 0 0 0 0 P P P P P P K K 5 4 3 2 1 0 S A C K S T O P instruction register S opcode addresses A C R R K 1 0 1 1 1 0 0 0 M A C K S T O P Write Wiper Counter Register (WCR) S device type device T identifier addresses A R 0 1 0 1 A A 0 A 3 2 0 T Read Data Register (DR) S device type device T identifier addresses A R 0 1 0 1 A A 0 A 3 2 0 T wiper position/data S (sent by slave on SDA) A W W W W W W C 0 0 P P P P P P K 5 4 3 2 1 0 Write Data Register (DR) S device type device instruction register S T identifier addresses opcode addresses A A C A A A R R R 0 1 0 1 0 1 1 0 0 0 0 3 2 0 K 1 0 T wiper position/data S (sent by master on SDA) A W W W W W W C 0 0 P P P P P P K 5 4 3 2 1 0 S A C K S T HIGH-VOLTAGE O WRITE CYCLE P XFR Data Register (DR) to Wiper Counter Register (WCR) S device type device instruction register S T identifier addresses opcode addresses A A C A A A R R R 0 1 0 1 0 1 1 0 1 0 0 3 2 0 K 1 0 T 11 S A C K S T O P FN8248.2 October 19, 2005 X9429 XFR Wiper Counter Register (WCR) to Data Register (DR) S device type device T identifier addresses A R 0 1 0 1 A A 0 A 3 2 0 T instruction register S opcode addresses A C R R 1 1 1 0 0 0 K 1 0 S A C K S T O P HIGH-VOLTAGE WRITE CYCLE Increment/Decrement Wiper Counter Register (WCR) S device type device T identifier addresses A R 0 1 0 1 A A 0 A 3 2 0 T instruction increment/decrement S S opcode (sent by master on SDA) A A C C I/ I/ I/ I/ K 0 0 1 0 0 0 0 0 K D D . . . . D D WAVEFORM Guidelines for Calculating Typical Values of Bus Pull-Up Resistors INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance 12 120 100 Resistance (K) SYMBOL TABLE S T O P 80 60 RMIN = VCC MAX =1.8kΩ IOL MIN RMAX = tR CBUS Max. Resistance 40 20 Min. Resistance 0 0 20 40 60 80 100 120 Bus Capacitance (pF) FN8248.2 October 19, 2005 X9429 ABSOLUTE MAXIMUM RATINGS COMMENT Temperature under bias : ........................-65°C to +135°C Storage temperature: .............................-65°C to +150°C Voltage on SCL, SDA any address input with respect to VSS: ...................................-1V to +7V ∆V = | (VH - VL) | .............................................................5V Lead temperature (soldering, 10 seconds)..............300°C IW (10 seconds) ...................................................±6mA Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Commercial Min. 0°C Max. +70°C Device X9429 Supply Voltage (VCC) Limits 5V ±10% Industrial -40°C +85°C X9429-2.7 2.7V to 5.5V ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Symbol Parameter Min. Typ. Max. Unit Test Conditions End to End Resistance Tolerance ±20 % Power rating 50 mW IW Wiper current ±3 mA RW Wiper resistance 150 250 Ω Wiper current = ± 1mA, VCC = 5V 400 1000 Ω Wiper current = ± 1mA, VCC = 3V VCC V VSS = 0V -120 dBV Ref: 1kHz 1.6 % VTERM Voltage on any VH/RH or VL/RL pin Noise Resolution (4) Absolute Linearity (1) Relative Linearity (2) Temperature Coefficient of RTOTAL VSS Potentiometer Capacitances 13 ±1 MI(3) Vw(n)(actual) - Vw(n)(expected) ±0.2 MI(3) Vw(n + 1) - [Vw(n) + MI] ±300 Ratiometric Temperature Coefficient CH/CL/CW ppm/°C ±20 10/10/25 25°C, each pot ppm/°C pF See Circuit #3, Spice Macromodel FN8248.2 October 19, 2005 X9429 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Typ. Max. Unit Test Conditions 1 mA fSCL = 400kHz, SDA = Open, Other Inputs = VSS 100 µA fSCL = 400kHz, SDA = Open, Other Inputs = VSS ICC1 VCC supply current (nonvolatile write) ICC2 VCC supply current (move wiper, write, read) ISB VCC current (standby) 5 µA SCL = SDA = VCC, Addr. = VSS ILI Input leakage current 10 µA VIN = VSS to VCC ILO Output leakage current 10 µA VOUT = VSS to VCC VIH Input HIGH voltage VCC x 0.7 VCC x 0.5 V VIL Input LOW voltage -0.5 VCC x 0.1 V VOL Output LOW voltage 0.4 V IOL = 3mA Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (RH - RL)/63, single pot (4) Typical = individual array resolutions. ENDURANCE AND DATA RETENTION Parameter Min. Unit Minimum endurance 100,000 Data changes per bit per register Data retention 100 Years CAPACITANCE Symbol CI/O(5) CIN(5) Test Max. Unit Test Conditions Input/output capacitance (SDA) 8 pF VI/O = 0V Input capacitance (A0, A2,and A3 and SCL) 6 pF VIN = 0V POWER-UP TIMING Symbol tRVCC (6) Parameter VCC Power-up ramp rate Min. 0.2 Typ. Max. Unit 50 V/msec POWER-UP AND POWER-DOWN REQUIREMENTS There are no restrictions on the power-up or power-down conditions of VCC and the voltage applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW. The VCC ramp rate spec is alway in effect. Notes: (5) This parameter is periodically sampled and not 100% tested (6) Sample tested only. 14 FN8248.2 October 19, 2005 X9429 A.C. TEST CONDITIONS Circuit #3 SPICE Macro Model Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x 0.5 RTOTAL RH CL CH CW RL 10pF EQUIVALENT A.C. LOAD CIRCUIT 10pF 5V 2.7V 25pF RW 1533Ω SDA Output 100pF 100pF AC TIMING (Over recommended operating conditions) Symbol Parameter Min. Max. Unit 400 kHz fSCL Clock frequency 100 tCYC Clock cycle time 2500 ns tHIGH Clock high time 600 ns tLOW Clock low time 1300 ns tSU:STA Start setup time 600 ns tHD:STA Start hold time 600 ns tSU:STO Stop setup time 600 ns tSU:DAT SDA data input setup time 100 ns tHD:DAT SDA data input hold time 30 ns tR SCL and SDA rise time 300 ns tF SCL and SDA fall time 300 ns 900 ns tAA SCL low to SDA data output valid time tDH SDA data output hold time 50 ns TI Noise suppression time constant at SCL and SDA inputs 50 ns 1300 ns tBUF Bus free time (prior to any transmission) tSU:WPA WP, A0, A2, A3 setup time 0 ns tHD:WPA WP, A0, A2, A3 hold time 0 ns 15 FN8248.2 October 19, 2005 X9429 HIGH-VOLTAGE WRITE CYCLE TIMING Symbol Parameter tWR Typ. Max. Unit 5 10 ms High-voltage write cycle time (store instructions) XDCP TIMING Symbol Max. Unit Wiper response time after the third (last) power supply is stable 10 µs tWRL Wiper response time after instruction issued (all load instructions) 10 µs tWRID Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 10 µs tWRPO Note: Parameter Min. (8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. TIMING DIAGRAMS START and STOP Timing (START) (STOP) tR tF SCL tSU:STA tHD:STA tSU:STO tR tF SDA Input Timing tCYC tHIGH SCL tLOW SDA tSU:DAT tHD:DAT tBUF Output Timing SCL SDA tAA 16 tDH FN8248.2 October 19, 2005 X9429 XDCP Timing (for All Load Instructions) (STOP) SCL LSB SDA tWRL VW/RW XDCP Timing (for Increment/Decrement Instruction) SCL SDA Wiper Register Address Inc/Dec Inc/Dec tWRID VW/RW Write Protect and Device Address Pins Timing (START) SCL (STOP) ... (Any Instruction) ... SDA ... tSU:WPA tHD:WPA WP A0, A2 A3 17 FN8248.2 October 19, 2005 X9429 APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers +VR VR VW/RW I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Application Circuits Noninverting Amplifier VS Voltage Regulator + VO – VIN VO (REG) 317 R1 R2 Iadj R1 R2 VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 Offset Voltage Adjustment R1 Comparator with Hysteresis R2 VS VS – + – 100kΩ VO VO + TL072 10kΩ } 10kΩ } 10kΩ R1 R2 VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min) +5V 18 FN8248.2 October 19, 2005 X9429 Application Circuits (continued) Attenuator Filter C VS + R2 R1 VS VO – – R VO + R3 R4 R2 All RS = 10kΩ R1 GO = 1 + R2/R1 fc = 1/(2πRC) V O = G VS -1/2 ≤ G ≤ +1/2 R1 R2 } } Inverting Amplifier Equivalent L-R Circuit VS R2 C1 – VS VO + + – R1 ZIN V O = G VS G = - R2/R1 R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 Function Generator C R2 – + R1 – } RA + } RB frequency ∝ R1, R2, C amplitude ∝ RA, RB 19 FN8248.2 October 19, 2005 X9429 PACKAGING INFORMATION 14-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .193 (4.9) .200 (5.1) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15) .010 (.25) Gage Plane 0° - 8° Seating Plane .019 (.50) .029 (.75) Detail A (20X) .031 (.80) .041 (1.05) See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 20 FN8248.2 October 19, 2005 X9429 PACKAGING INFORMATION 16-Lead Plastic SOIC (300 Mil Body) Package Type S 0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) PIN 1 INDEX PIN 1 0.014 (0.35) 0.020 (0.51) 0.403 (10.2 ) 0.413 ( 10.5) (4X) 7° 0.092 (2.35) 0.105 (2.65) 0.003 (0.10) 0.012 (0.30) 0.050 (1.27) 0.010 (0.25) 0.020 (0.50) X 45° 0.050" Typical 0° - 8 ° 0.0075 (0.19) 0.010 (0.25) 0.050" Typical 0.420" 0.015 (0.40) 0.050 (1.27) FOOTPRINT 0.030" Typical 16 Places NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 21 FN8248.2 October 19, 2005