XILINX XC5210

Technical
Data
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XC5200
Logic Cell Array Family
Preliminary (v1.0)
•
April 1995
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TABLE OF CONTENTS
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
XC5200 Family Compared to XC4000 Family . . . . . . . . . . . . . . . . . . . . . . . . .
2
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Development System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
VersaBlock Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
General Routing Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
XC5200
Logic Cell Array Family
R
Preliminary (v1.0)
Product Description
Features
• Fully supported by XACT® Development System
— Includes complete support for XACT-Performance™,
X-BLOX™, Unified Libraries, Relationally Placed
Macros (RPMs), XDelay, and XChecker™
— Wide selection of PC and workstation platforms
— Interfaces to more than 100 third-party CAE tools
• High-density family of Field-Programmable Gate Arrays
(FPGAs)
• Design- and process-optimized for low cost
— 0.6-µm three-layer metal (TLM) process
Description
• System performance up to 50 MHz
• SRAM-based, in-system reprogrammable architecture
The XC5200 Field-Programmable Gate Array Family is
engineered to deliver the lowest cost of any FPGA family.
By optimizing the new XC5200 architecture for TLM
technology and 0.6-µm CMOS SRAM process, dramatic
advances have been made in silicon efficiency. These
advances position the XC5200 family as a cost-effective,
high-volume alternative to gate arrays.
• Flexible architecture with abundant routing resources
— VersaBlock™ logic module
— VersaRing™ I/O interface
— Dedicated cell-feedthrough path
— Hierarchical interconnect structure
— Extensive registers/latches
— Dedicated carry logic for arithmetic functions
— Cascade chain for wide input functions
— Dedicated IEEE 1149.1 boundary-scan logic
— Internal 3-state bussing capability
— Four global low-skew clock or signal distribution nets
— Globally selectable CMOS or TTL input thresholds
— Output slew-rate control
— 8-mA sink current per output
Building on experiences gained with three previous
successful SRAM FPGA families, the XC5200 family
brings a robust feature set to high-density programmable
logic design. The VersaBlock logic module, the VersaRing
I/O interface, and a rich hierarchy of interconnect
resources combine to enhance design flexibility and
reduce time-to-market.
Complete support for the XC5200 family is delivered
through the familiar XACT software environment. The
XC5200 family is fully supported on popular workstation
and PC platforms. Popular design entry methods are fully
supported, including ABEL, schematic capture, and
synthesis. Designers utilizing logic synthesis can use their
existing Synopsys, Viewlogic, Mentor, and Exemplar tools
to design with the XC5200 devices.
• Configured by loading binary file
— Unlimited reprogrammability
— Six programming modes, including high-speed
Express™ mode
• 100% factory tested
• 100% footprint compatibility for common packages
Table 1.
Initial XC5200 Field-Programmable Gate Array Family Members
Device
XC5202
XC5204
XC5206
XC5210
XC5215
2,200 2,700
3,900 4,800
6,000 7,500
10,000 12,000
14,000 18,000
8x8
10 x 12
14 x 14
18 x 18
22 x 22
Number of CLBs
64
120
196
324
484
Number of Flip-Flops
256
480
784
1,296
1,936
Number of I/Os
84
124
148
196
244
TBUFs per Horizontal Longline
10
14
16
20
24
Typical Gate Range
VersaBlock Array
1
XC5200 Logic Cell Array Family
Preliminary (v1.0)
XC5200 Family Compared to XC4000 Family
• XC5200 devices have no dedicated wide edge
decoders. The XC5200 carry logic, unlike the XC4000
architecture, can be used to cascade function
generators to implement wide AND and OR functions,
for example.
For those readers already familiar with the XC4000 family
of Xilinx Field-Programmable Gate Arrays, here is a
concise description of the similarities and differences
between the XC4000 and XC5200 families.
• The XC5200 family contains a flexible coupling of logic
and local routing resources called the VersaBlock. The
XC5200 VersaBlock element includes the Configurable
Logic Block (CLB), a Local Interconnect Matrix (LIM),
and direct connects to neighboring VersaBlocks.
Superficially, the XC5200 family is quite similar to the
XC4000 family. Both use CMOS SRAM technology. Both
use 4-input lookup tables with unshared inputs. Both have
a dedicated fast carry track, and dedicated boundary-scan
logic in the input/output blocks (IOBs).
• XC5200 CLBs are roughly equivalent to two XC4000
CLBs. Each XC5200 CLB contains four 4-input function
generators and four registers, which are configured as
four independent Logic Cells™ (LCs). The output from
each function generator can be brought out as a CLB
output and/or drive the D input of a flip-flop. Pairs of
logic cells can be combined to form a 5-input function
generator.
XC5200 and XC4000 devices are footprint and pin-out
compatible; their pin names and pin locations are
identical. XC5200 devices offer the same configuration
options as XC4000 devices, and they can be intermixed
with XC4000 devices in a configuration daisy chain.
There are also, however, significant differences between
the two families:
• There are four direct feedthrough paths per CLB, one
per LC. These paths can provide extra data input lines
or serve as local routes without consuming any logic
resources.
• XC5200 lookup tables cannot be used as RAM.
• The XC5200 family offers dedicated carry logic, but
differs from the XC4000 family in that the sum is
generated in an additional function generator in the
adjacent column. An XC5200 device thus uses twice as
many function generators for adders, subtracters,
accumulators, and some counters. Note, however, that
a loadable up/down counter requires the same number
of function generators in both families.
• The XC5200 family has a global reset, whereas the
XC4000 family has both a global set and a global reset.
• Unlike the XC4000 family, each register can be
configured as either an edge-triggered D flip-flop or a
transparent, level-sensitive latch.
• There are no dedicated IOB flip-flops, but there are fast
direct connects to adjacent CLBs.
Table 2.
Four Generations of Xilinx Field-Programmable Gate Array Families
Parameter
XC5200
XC4000
XC3000A/XC3100A
XC2000
Function generators per CLB
4
3
2
2
Logic inputs per CLB
20
9
5
4
Logic outputs per CLB
12
4
2
2
Low-skew global buffers
4
8
2
2
User RAM
no
yes
no
no
Dedicated decoders
no
yes
no
no
Cascade chain
yes
no
no
no
Fast carry logic
yes
yes
no
no
Internal 3-state drivers
yes
yes
yes
no
IEEE boundary scan
yes
yes
no
no
Output slew-rate control
yes
yes
yes
no
Power-down option
no
no
yes
yes
Crystal oscillator circuit
no
no
yes
yes
2
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Table 3.
Architectural Overview
Routing Resource Comparison
Resource
XC5200
XC4000
Single-length Lines
10
8
Double-length Lines
4
4
Longlines
8
6
Direct Connects
8
0
yes
no
VersaRing
Figure 1 presents a simplified, conceptual overview of the
XC5200 architecture. Similar to conventional FPGAs, the
XC5200 family consists of programmable IOBs,
programmable logic blocks, and programmable
interconnect. Unlike other FPGAs, however, the logic and
local routing resources of the XC5200 family are
combined in flexible VersaBlocks. General-purpose
routing connects to the VersaBlock through the General
Routing Matrix (GRM).
VersaBlock: Abundant Local Routing Plus Versatile
Logic
• The TLM process allows significant improvements in the
routing structure. Each XC5200 VersaBlock element
has complete intra-CLB routing, the LIM, and offers four
direct routing connections to each of the four
neighboring CLBs (North, South, East, and West). Any
function generator or flip-flop thus has unrestricted
connectivity to 19 other function generators or flipflops: three in its own CLB, and 16 in the adjacent
CLBs. These direct connects do not compete with the
general routing resources (see Table 3).
The basic logic element in each VersaBlock structure is
the Logic Cell, shown in Figure 2. Each LC contains a 4input function generator (F), a storage device (FD), and
control logic. There are five independent inputs and three
outputs to each LC. The independence of the inputs and
outputs allows the software to maximize the resource
utilization within each LC. Each Logic Cell also contains a
direct feedthrough path that does not sacrifice the use of
either the function generator or the register; this feature is
a first for FPGAs. The storage device is configurable as
either a D flip-flop or a latch. The control logic consists of
carry logic for fast implementation of arithmetic functions,
which can also be configured as a cascade chain allowing
decode of very wide input functions.
• Each XC5200 3-state buffer (TBUF) can drive up to two
horizontal Longlines; each XC4000 TBUF accesses
only one horizontal Longline.
• There is a special racetrack, the VersaRing, between
the outer edge of the core CLB array and the ring of
IOBs, providing significant help in overcoming the
problems caused by early locking of I/O pins.
The XC5200 CLB consists of four LCs, as shown in
Figure 3. Each CLB has 20 independent inputs and 12
independent outputs. The top and bottom pairs of LCs can
be configured to implement 5-input functions. The
challenge of FPGA implementation software has always
been to maximize the usage of logic resources. The
XC5200 family addresses this issue by surrounding each
CLB with two types of local interconnect — the LIM and
direct connects. These two interconnect resources,
combined with the CLB, form the VersaBlock, represented
in Figure 4.
• There are no internal pull-ups for XC5200 Longlines.
Input/Output Blocks (IOBs)
VersaRing
GRM
VersaBlock
GRM
VersaBlock
GRM
VersaBlock
VersaBlock
GRM
VersaBlock
GRM
VersaBlock
VersaRing
VersaRing
CO
GRM
DO
DI
D
GRM
VersaBlock
GRM
VersaBlock
F4
GRM
Q
FD
F3
VersaBlock
F2
F
F1
VersaRing
X
CI
X4955
CE CK
CLR
X4956
Figure 1.
XC5200 Architectural Overview
Figure 2.
3
XC5200 Logic Cell (Four LCs per CLB)
XC5200 Logic Cell Array Family
LC3
Preliminary (v1.0)
CO
GRM
DO
4
DI
D
F4
Q
24
24
FD
TS
F3
F2
4
CLB
F
LC3
F1
4
X
LC2
4
4
DO
LC0
DI
D
4
LC1
LC2
F4
4
Q
LIM
FD
F3
F2
F
4
4
F1
X
Direct Connects
Figure 4.
LC1
X5707
VersaBlock
DO
DI
D
F4
Q
The LIM provides 100% connectivity of the inputs and
outputs of each LC in a given CLB. The benefit of the LIM
is that no general routing resources are required to
connect feedback paths within a CLB. The LIM connects
to the GRM via 24 bidirectional nodes.
FD
F3
F2
F
F1
X
The direct connects allow immediate connections to
neighboring CLBs, once again without using any of the
general interconnect. These two layers of local routing
resource improve the granularity of the architecture,
effectively making the XC5200 family a “sea of logic cells.”
Each VersaBlock has four 3-state buffers that share a
common enable line and directly drive horizontal
Longlines, creating robust on-chip bussing capability. The
VersaBlock allows fast, local implementation of logic
functions, effectively implementing user designs in a
hierarchical fashion. These resources also minimize local
routing congestion and improve the efficiency of the
general interconnect, which is used for connecting larger
groups of logic. It is this combination of both fine-grain and
coarse-grain architecture attributes that maximize logic
utilization in the XC5200 family. This symmetrical structure
takes full advantage of the third metal layer, freeing the
placement software to pack user logic optimally with
minimal routing restrictions.
LC0
DO
DI
D
F4
Q
FD
F3
F2
F
F1
X
CI
CE CK
CLR
X4957
Figure 3.
Configurable Logic Block
4
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VersaRing I/O Interface
contained within each VersaBlock. Throughout the
XC5200 interconnect, an efficient multiplexing scheme, in
combination with TLM, was used to improve the overall
efficiency of silicon usage.
The interface between the IOBs and core logic has been
redesigned in the XC5200 family. The IOBs are
completely decoupled from the core logic. The XC5200
IOBs contain dedicated boundary-scan logic for added
board-level testability, but do not include input or output
registers. This approach allows a maximum number of
IOBs to be placed around the device, improving the I/O-togate ratio and decreasing the cost per I/O. A “freeway” of
interconnect cells surrounding the device forms the
VersaRing, which provides connections from the IOBs to
the internal logic These incremental routing resources
provide abundant connections from each IOB to the
nearest VersaBlock, in addition to Longline connections
surrounding the device. The VersaRing eliminates the
historic trade-off between high logic utilization and pin
placement flexibility. These incremental edge resources
give users increased flexibility in preassigning (i.e.,
locking) I/O pins before completing their logic designs.
This ability accelerates time-to-market, since PCBs and
other system components can be manufactured
concurrent with the logic design.
Performance Overview
The XC5200 family has been benchmarked with many
designs running synchronous clock rates up to 40 MHz. The
performance of any design depends on the circuit to be
implemented, and the delay through the combinatorial and
sequential logic elements, plus the delay in the interconnect
routing. Table 4 shows some performance numbers for
representative circuits, using worst-case timing parameters
for the Engineering Sample (ES) speed grade. A rough
estimate of timing can be made by assuming 6 ns per logic
level, which includes direct-connect routing delays. More
accurate estimations can be made using the information in
the Switching Characteristic Guideline section.
General Routing Matrix
The GRM is functionally similar to the switch matrices
found in other architectures, but it is novel in its tight
coupling to the logic resources contained in the
VersaBlocks. Advanced simulation tools were used during
the development of the XC5200 architecture to determine
the optimal level of routing resources required. The
XC5200 family contains six levels of interconnect
hierarchy — a series of single-length lines, double-length
lines, and Longlines all routed through the GRM. The
direct connects, LIM, and logic-cell feedthrough are
Table 4.
Performance for Several Common Circuit Functions
XC5200 Speed Grade
Function
-6
-5
9 ns
8 ns
24-bit Accumulator
32 MHz
39 MHz
16-to-1 Multiplexer
16 ns
13 ns
16-bit Unidirectional Loadable Counter
40 MHz
50 MHz
16-bit U/D Counter
40 MHz
50 MHz
16-bit Adder
24 ns
20 ns
24-bit Loadable U/D Counter
36 MHz
42 MHz
16-bit Decoder from Input Pad
5
-4
XC5200 Logic Cell Array Family
Preliminary (v1.0)
Development System
Xilinx offers XACT development system interfaces to the
following design environments:
The powerful features of the XC5200 device family require
an equally powerful, yet easy-to-use, set of development
tools. Xilinx provides an enhanced version of the Xilinx
Automatic CAE Tools (XACT), optimized for the XC5200
family.
• Viewlogic Systems (Viewdraw, Viewsim)
• Mentor Graphics V8 (NETED, QuickSim, Design
Architect, QuickSim II)
• OrCAD (SDT, VST)
As with other logic technologies, the basic methodology
for XC5200 FPGA design consists of three interrelated
steps: design entry, implementation, and verification.
Popular generic tools are used for entry and simulation
(for example, Viewlogic Systems’s Viewdraw schematic
editor and Viewsim simulator), but architecture-specific
tools are needed for implementation.
• Synopsys (Design Compiler, FPGA Compiler)
• Xilinx-ABEL (State Machine module generator)
• X-BLOX (Graphical Mode Generator)
Many other environments are supported by third-party
vendors. Currently, more than 100 packages are
supported.
All Xilinx development system software is integrated under
the Xilinx Design Manager (XDM™), providing designers
with a common user interface regardless of their choices
of entry and verification tools. XDM simplifies the selection
of command-line options with pull-down menus and online
help text. Application programs ranging from schematic
capture to Partitioning, Placement, and Routing (PPR)
can be accessed from XDM, while the program-command
sequence is generated and stored for documentation prior
to execution. The XMAKE command, a design compilation
utility, automates the entire implementation process,
automatically retrieving the design’s input files and
performing all the steps needed to create configuration
and report files.
The unified schematic library for the XC5200 FPGA
reflects the wide variety of logic functions that can be
implemented in these versatile devices. The library
contains over 400 primitives and macros, ranging from 2input AND gates to 16-bit accumulators, and includes
arithmetic functions, comparators, counters, data
registers, decoders, encoders, I/O functions, latches,
Boolean functions, multiplexers, shift registers, and barrel
shifters.
Designing with macros is as easy as designing with
standard SSI/MSI functions. The “soft macro” library
contains detailed descriptions of common logic functions,
but does not contain any partitioning or routing
information. The performance of these macros depends,
therefore, on how the PPR software processes the design.
RPMs, on the other hand, do contain predetermined
partitioning and relative placement information, resulting
in an optimized implementation for these functions. Users
can create their own library elements — either soft macros
or RPMs — based on the macros and primitives of the
standard library.
Several advanced features of the XACT system facilitate
XC5200 FPGA design. RPMs — schematic-based macros
with relative location constraints to guide their placement
within the FPGA — help to ensure an optimized
implementation for common logic functions. An
abundance of local routing permits RPMs to be contained
within a single VersaBlock or to span across multiple
VersaBlocks. XACT-Performance allows designers to
enter the exact performance requirements during design
entry, at the schematic level, to guide PPR.
The X-BLOX design language is a graphics-based highlevel description language (HDL) that allows designers to
use a schematic editor to enter designs as a set of generic
modules. The X-BLOX compiler synthesizes and
optimizes the modules for the target device architecture,
automatically choosing the appropriate architectural
resources for each function.
Design Entry
Designs can be entered graphically, using schematiccapture software, or in any of several text-based formats
(such as Boolean equations, state-machine descriptions,
and high-level design languages).
The XACT design environment supports hierarchical
design entry, with top-level drawings defining the major
functional blocks, and lower-level descriptions defining the
logic in each block. The implementation tools
automatically combine the hierarchical elements of a
design. Different hierarchical elements can be specified
with different design entry tools, allowing the use of the
most convenient entry method for each portion of the
design.
Xilinx and third-party CAE vendors have developed library
and interface products compatible with a wide variety of
design-entry and simulation environments. A standard
interface-file specification, Xilinx Netlist File (XNF), is
provided to simplify file transfers into and out of the XACT
development system.
6
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Design Implementation
The XACT development system supports both simulation
and in-circuit debugging techniques. For simulation, the
system extracts the post-layout timing information from
the design database. This data can then be sent to the
simulator to verify timing-critical portions of the design
database using XDELAY, the Xilinx static timing analyzer
tool. Back-annotation — the process of mapping the
timing information back into the signal names and
symbols of the schematic — eases the debugging effort.
The design implementation tools satisfy the requirements
for an automated design process. Logic partitioning, block
placement, and signal routing are performed by the PPR
program. The partitioner takes the logic from the entered
design and maps the logic into the architectural resources
of the FPGA (such as the logic blocks, I/O blocks, and 3state buffers). The placer then determines the best
locations for the blocks, depending on their connectivity
and the required performance. The router finally connects
the placed blocks together.
For in-circuit debugging, the XACT development system
includes a serial download and readback cable
(XChecker) that connects the FPGA in the system to the
PC or workstation through an RS232 serial port. The
engineer can download a design or a design revision into
the system for testing. The designer can also single-step
the logic, read the contents of the numerous flip-flops on
the device, and observe internal logic levels. Simple
modifications can be downloaded into the system in a
matter of minutes.
The
PPR
algorithms
support
fully
automatic
implementation of most designs. However, for demanding
applications, the user may exercise various degrees of
control over the automated implementation process.
Optionally, user-designated partitioning, placement, and
routing information can be specified as part of the designentry process. The implementation of highly structured
designs can benefit greatly from the basic floorplanning
techniques familiar to designers of large gate arrays.
The PPR program includes XACT-Performance, a feature
that allows designers to specify the timing requirements
along entire paths during design entry. Timing path
analysis routines in PPR then recognize and
accommodate the user-specified requirements. Timing
requirements can be entered on the schematic in a form
directly relating to the system requirements (such as the
targeted minimum clock frequency, or the maximum
allowable delay on the data path between two registers).
So, while the timing of each individual net is not
predictable, the overall performance of the system along
entire signal paths is automatically tailored to match usergenerated specifications.
Design Verification
The high development cost associated with common
mask-programmed gate arrays necessitates extensive
simulation to verify a design. Due to the custom nature of
masked gate arrays, mistakes or last-minute design
changes cannot be tolerated. A gate-array designer must
simulate and test all logic using simulation software.
Simulation describes what happens in a system under
worst-case situations. However, simulation can be tedious
and slow, and simulation vectors must be generated. A
few seconds of system time can take weeks to simulate.
Programmable-gate-array users, however, can use incircuit debugging techniques in addition to simulation.
Because Xilinx devices are reprogrammable, designs can
be verified in real time without the need for extensive
simulation vectors.
7
XC5200 Logic Cell Array Family
Preliminary (v1.0)
Detailed Functional Description
CLB Logic
Figure 3 shows the logic in the XC5200 CLB, which
consists of four Logic Cells (LC[3:0]). Each Logic Cell
consists of an independent 4-input Lookup Table (LUT),
and a D-Type flip-flop or latch with common clock, clock
enable, and clear, but individually selectable clock polarity.
Additional logic features provided in the CLB are:
• High-speed carry propagate logic.
• High-speed pattern decoding.
• High-speed direct connection to flip-flop D-inputs.
• Each flip-flop can be programmed individually as either
a transparent, level-sensitive latch or a D flip-flop.
• Four 3-state buffers with a shared Output Enable.
• Two 4-input LUTs can be combined to form an
independent 5-input LUT.
5-Input Functions
Figure 5 illustrates how the outputs from the LUTs from
LC0 and LC1 can be combined with a 2:1 multiplexer
(F5_MUX) to provide a 5-input function. The outputs from
the LUTs of LC2 and LC3 can be similarly combined.
CO
DO
DI
Q
D
FD
I1
I2
I3
I4
F4
F3
F2
F1
F
X
LC1
F5_MUX
DO
I5
DI
D
Q
out
Qout
FD
F4
F3
F2
F1
F
X
CI
CE CK
5-Input Function
Figure 5.
Two LUTs in Parallel Combined to Create a 5-input Function
8
CLR
LC0
X5710
R
Carry Function
shown, which also generates the half-sum for the four-bit
adder. An adjacent CLB is responsible for XORing the
half-sum with the corresponding carry-out. Thus an adder
or counter requires two LCs per bit. Notice that the carry
chain requires an initialization stage, which the XC5200
family accomplishes using the carry initialize (CY_INIT)
macro and one additional LC.
The XC5200 family supports a carry-logic feature that
enhances the performance of arithmetic functions such as
counters, adders, etc. A carry multiplexer (CY_MUX)
symbol on a schematic is used to indicate the XC5200
carry logic. This symbol represents the dedicated 2:1
multiplexer in each LC that performs the one-bit highspeed carry propagate per logic cell (four bits per CLB).
The XC5200 library contains a set of RPMs and arithmetic
functions designed to take advantage of the dedicated
carry logic. Using and modifying these macros makes it
much easier to implement customized RPMs, freeing the
designer from the need to become an expert on
architectures.
While the carry propagate is performed inside the LC, an
adjacent LC must be used to complete the arithmetic
function. Figure 6 represents an example of an adder
function. The carry propagate is performed on the CLB
carry out
A3
or
B3
A3 and B3
to any two
CO
DO
DI
DO
XOR
X half sum3
F4
F3
F2
F1
FD
XOR
X
LC3
A2
or
B2
A2 and B2
to any two
D
F4
F3
F2
F1
DO
DI
Q
D
FD
CY_MUX
XOR
X
half sum2
F4
F3
F2
F1
XOR
X
A1 and B1
to any two
D
F4
F3
F2
F1
DO
DI
Q
D
FD
CY_MUX
XOR
X
half sum1
F4
F3
F2
F1
A0 and B0
to any two
DO
DI
XOR
X
F4
F3
F2
F1
XOR
X
CI
LC1
DO
DI
CE CK
CLR
Q
D
FD
CY_MUX
sum1
carry0
Q
D
Q
FD
LC1
A0
or
B0
sum2
LC2
DO carry1
DI
Q
FD
LC2
A1
or
B1
sum3
LC3
DO carry2
DI
Q
D
FD
CY_MUX
CO
DI
Q
D
F4
F3
F2
F1
carry3
half sum0
LC0
F4
F3
F2
F1
FD
XOR
X
CI
CE CK
CLR
sum0
LC0
carry in
0
CY_MUX
F=0
Figure 6.
Initialization of
carry chain (One Logic Cell)
X5709
XC5200 CY_MUX Used for Adder Carry Propagate
9
XC5200 Logic Cell Array Family
Preliminary (v1.0)
Cascade Function
CY_MUXes. Note that AND and OR cascading are
specific cases of a general decode. In AND cascading all
bits are decoded equal to logic one, while in OR
cascading all bits are decoded equal to logic zero. The
flexibility of the LUT achieves this result.
Each CY_MUX can be connected to the CY_MUX in the
adjacent LC to provide cascadable decode logic. Figure 7
illustrates how the 4-input function generators can be
configured to take advantage of these four cascaded
cascade out
CO
DO
DI
A15
F4
A14
F3
A13
F2
A12
F1
out
Q
D
FD
CY_MUX
AND
X
LC3
DO
DI
D
A11
A10
A9
A8
F4
F3
F2
F1
Q
FD
CY_MUX
AND
X
LC2
DO
DI
D
A7
F4
A6
F3
A5
F2
A4
F1
Q
FD
CY_MUX
AND
X
LC1
DO
DI
Q
D
A3
F4
A2
F3
A1
F2
A0
F1
FD
CY_MUX
AND
X
CE CK
CI
CLR
LC0
cascade in
CY_MUX
F=0
Figure 7.
Initialization of
carry chain (One Logic Cell)
XC5200 CY_MUX Used for Decoder Cascade Logic
10
X5708
R
3-State Buffers
Start-Up
The XC5200 family has four dedicated TBUFs per CLB.
The four buffers are individually configurable through four
configuration bits to operate as simple non-inverting
buffers or in 3-state mode. When in 3-state mode the
CLB’s output enable (TS) control signal drives the enable
to all four buffers (see Figure 8). Each TBUF can drive up
to two horizontal Longlines
On start-up, all XC5200 internal flip-flops are reset. The
XC5200 devices do not support the “INIT=” attribute.
Thus, the XC5200 family has only a global reset (GR)
signal. The user can assign the pin location for the GR
signal and use it to reset asynchronously all of the flipflops in the design without using general routing
resources. The user can also assign a positive or negative
polarity to GR.
Oscillator
Boundary Scan
The XC5200 oscillator (OSC52) divides the internal 16MHz clock or a user clock that is connected to the “C” pin.
The user then has the choice of dividing by 4, 16, 64, or
256 for the “OSC1” output and dividing by 2, 8, 32, 128,
1024, 4096, 16384, or 65536 for the “OSC2” output. The
division is specified via a “DIVIDEn_BY=x” attribute on the
symbol, where n=1 for OSC1, or n=2 for OSC2. The
OSC5 macro is used where an internal oscillator is
required. The CK_DIV macro is applicable when a user
clock input is specified (see Figure 9).
XC5200 devices support all the mandatory boundary-scan
instructions specified in the IEEE standard 1149.1. A Test
Access Port (TAP) and registers are provided that
implement the EXTEST, SAMPLE/PRELOAD, and
BYPASS instructions. The TAP can also support two
USERCODE instructions.
Boundary-scan operation is independent of individual IOB
configuration and package type. All IOBs are treated as
independently controlled bidirectional pins, including any
unbonded IOBs. Retaining the bidirectional test capability
after configuration provides flexibility for interconnect
testing.
TS
Also, internal signals can be captured during EXTEST by
connecting them to unbonded IOBs, or to the unused
outputs in IOBs used as unidirectional input pins. This
technique partially compensates for the lack of INTEST
support.
CLB
CLB
LC3
The public boundary-scan instructions are always
available prior to configuration. After configuration, the
public instructions and any USERCODE instructions are
only available if specified in the design. While SAMPLE
and BYPASS are available during configuration, it is
recommended that boundary-scan operations not be
performed during this transitory period.
LC2
LC1
LC0
Horizontal
Longlines
In addition to the test instructions outlined above, the
boundary-scan circuitry can be used to configure the
Logic Cell Array (LCA™) device, and to read back the
configuration data.
X5706
Figure 8.
XC5200 3-State Buffer
OSC5
All of the XC4000 boundary-scan modes are supported in
the XC5200 family. Three additional outputs for the User
Register are provided (Reset, Update, and Shift),
representing the decoding of the corresponding state of
the boundary-scan internal state machine. For details on
boundary scan, refer to “Boundary Scan in XC4000
Devices — Application Note” on pages 8-45 through 8-42
of the 1994 Xilinx Programmable Logic Data Book.
OSC1
OSC2
CK_DIV
CLK
Figure 9.
OSC1
OSC2
XC5200 Oscillator Macros
11
XC5200 Logic Cell Array Family
Preliminary (v1.0)
VersaBlock Routing
Direct Connects
Local Interconnect Matrix
The unidirectional direct-connect segments are connected
to the logic input/output pins through the CLB’s input and
output multiplexer array, and thus bypass the
programmable routing matrix altogether. These lines are
intended to increase the routing channel utilization where
possible, while simultaneously reducing the delay incurred
in speed-critical connections.
The GRM connects to the VersaBlock via 24 bidirectional
ports (M0-M23). Excluding direct connections, global nets,
and 3-statable Longlines, all VersaBlock inputs and
outputs connect to the GRM via these 24 ports. Four 3statable unidirectional signals (TQ0-TQ3) drive out of the
VersaBlock directly onto the horizontal Longlines. Two
horizontal global nets (GH0 and GH1) and two vertical
global nets (GV0 and GV1) connect directly to every CLB
clock pin; they can connect to other CLB inputs via the
GRM. Each CLB also has four unidirectional direct
connects to each of its four neighboring CLBs. These
direct connects can also feed directly back to the CLB
(see Figure 10).
The direct connects also provide a high-speed path from
the edge CLBs to the VersaRing input/output buffers, and
thus reduce set-up time, clock-to-out, and combinational
propagation delay.
The direct connects are ideal for developing customized
RPM cells. Using direct connects improves the macro
performance, and leaves the other routing channels intact
for improved routing. Direct connects can also route
through a CLB using one of the four cell-feedthrough
paths.
In addition, each CLB has 16 direct inputs, four direct
connections from each of the neighboring CLBs. These
direct connections provide high-speed local routing that
bypasses the GRM.
The 13 CLB outputs (12 LC outputs plus a Vcc/GND
signal) connect to the eight VersaBlock outputs via the
output multiplexers, which consist of eight fully populated
13-to-1 multiplexers. Of the eight VersaBlock outputs, four
signals drive each neighboring CLB directly, and provide a
direct feedback path to the input multiplexers. The four
remaining multiplexer outputs can drive the GRM through
four TBUFs (TQ0-TQ3). All eight multiplexer outputs can
connect to the GRM through the bidirectional M0-M23
signals. All eight signals also connect to the input
multiplexers and are potential inputs to that CLB.
CLB inputs have several possible sources: the 24 signals
from the GRM, 16 direct connections from neighboring
VersaBlocks, four signals from global, low-skew buffers
(GH0, GH1, GV0, and GV1), and the four signals from the
CLB output multiplexers. Unlike the output multiplexers,
the input multiplexers are not fully populated; i.e., only a
subset of the available signals can be connected to a
given CLB input. The flexibility of LUT input swapping and
LUT mapping compensates for this limitation. For
example, if a 2-input NAND gate is required, it can be
mapped into any of the four LUTs, and use any two of the
four inputs to the LUT.
12
R
To GRM
M0-M23
24
TS
4
Global Nets
8
COUT
North
4
South
4
East
4
West
4
4
4
To
Longlines
and GRM
TQ0-TQ3
4
Direct to
East
CLB
5
Input
Multiplexers
LC3
5
LC2
5
LC1
5
LC0
3
3
VCC /GND
3
Output
Multiplexers
8
4
3
Direct North
CLK
4
Feedback
4
Direct West
CE
CLR
CIN
4
4
Direct South
X5724
Figure 10. VersaBlock Details
13
XC5200 Logic Cell Array Family
Preliminary (v1.0)
General Routing Matrix
each CLB, and are driven by similar buffers at the
periphery of the array from the VersaRing I/O Interface.
The General Routing Matrix, shown in Figure 11, provides
flexible bidirectional connections to the Local Interconnect
Matrix through a hierarchy of different-length metal
segments in both the horizontal and vertical directions. A
programmable interconnect point (PIP) establishes an
electrical connection between two wire segments. The
PIP, consisting of a pass transistor switch controlled by a
memory element, provides bidirectional (in some cases,
unidirectional) connection between two adjoining wires. A
collection of PIPs inside the General Routing Matrix and in
the Local Interconnect Matrix provides connectivity
between various types of metal segments. A hierarchy of
PIPs and associated routing segments combine to provide
a powerful interconnect hierarchy:
Bus-oriented microprocessor designs are accommodated
by using horizontal Longlines in conjunction with the 3state buffers in the CLB and in the VersaRing. Additionally,
programmable keeper cells at the periphery can be
enabled to retain the last valid logic level on the Longlines
when all buffers are in 3-state mode.
Longlines connect to the single-length or double-length
lines, or to the logic inside the CLB, through the General
Routing Matrix. The only manner in which a Longline can
be driven is through the four 3-state buffers; therefore, a
Longline-to-Longline or single-line-to-Longline connection
through PIPs in the General Routing Matrix is not
possible. Again, as a general rule, long- and global-line
connections to the General Routing Matrix are
unidirectional, with the signal direction from these lines
toward the routing matrix.
• Forty bidirectional single-length segments per CLB
provide ten routing channels to each of the four
neighboring CLBs in four directions.
The XC5200 family has no pull-ups on the ends of the
Longlines sourced by TBUFs. Consequently, wired
functions (i.e., WAND and WORAND) and wide
multiplexing functions requiring pull-ups for undefined
states (i.e., bus applications) must be implemented in a
different way. In the case of the wired functions, the same
functionality can be achieved by taking advantage of the
carry/cascade logic described above, implementing a
wide logic function in place of the wired function. In the
case of 3-state bus applications, the user must insure that
all states of the multiplexing function are defined. This
process is as simple as adding an additional TBUF to
drive the bus High when the previously undefined states
are activated.
• Sixteen bidirectional double-length segments per CLB
provide four routing channels to each of four other (nonneighboring) CLBs in four directions.
• Eight horizontal and eight vertical bidirectional Longline
segments span the width and height of the chip,
respectively.
• Two low-skew horizontal and vertical unidirectional
global-line segments span each row and column of the
chip, respectively.
Single- and Double-Length Lines
The single- and double-length bidirectional line segments
make up the bulk of the routing channels. The doublelength lines hop across every other CLB to reduce the
propagation delays in speed-critical nets. Regenerating
the signal strength is recommended after traversing three
or four such segments. XACT place-and-route software
automatically connects buffers in the path of the signal as
necessary. Single- and double-length lines cannot drive
onto Longlines and global lines; Longlines and global lines
can, however, drive onto single- and double-length lines.
As a general rule, Longline and global-line connections to
the programmable routing matrix are unidirectional, with
the signal direction from these lines toward the routing
matrix.
Global Clock Buffers
Global buffers in Xilinx FPGAs are special buffers that
drive a dedicated routing network called Global Lines, as
shown in Figure 12. This network is intended for high-fanout clocks or other control signals, to maximize speed and
minimize skewing while distributing the signal to many
loads.
The XC5200 family has a total of four global buffers
(BUFG symbol in the library), each with its own dedicated
routing channel. Two are distributed vertically and two
horizontally throughout the LCA.
Longlines
Longlines are used for high-fan-out signals, 3-state
busses, low-skew nets, and faraway destinations. Row
and column splitter PIPs in the middle of the array
effectively double the total number of Longlines by
electrically dividing them into two separated half-lines. The
horizontal Longlines are driven by the 3-state buffers in
14
R
GRM
GRM
VersaBlock
GRM
GRM
VersaBlock
VersaBlock
GRM
VersaBlock
1
GRM
VersaBlock
VersaBlock
2
GRM
GRM
VersaBlock
GRM
VersaBlock
VersaBlock
3
4
Six Levels of Routing Hierarchy
1
Single-length Lines
2
Double-length Lines
GRM
4
4
24
24
TS
CLB
LC3
3
4
Direct Connects
4
4
4
Longlines and Global Lines
LC2
4
4
LC1
6 LC0
5
6
LIM
Local Interconnect Matrix
LIM
Logic Cell Feedthrough
Path (Contained within each
Logic Cell)
4
4
Direct Connects
Figure 11. XC5200 Interconnect Structure
15
5
X4963
XC5200 Logic Cell Array Family
Preliminary
Global Lines
The input buffer has globally selected CMOS and TTL
input thresholds. The input buffer is invertible and also
provides a programmable delay line to assure reliable
chip-to-chip set-up and hold times. Minimum ESD
protection is 5 KV using the Human Body Model.
Two pairs of horizontal and vertical global lines provide
low-skew clock signals to the CLBs. Global lines are
driven by low-skew buffers inside the VersaRing. The
global lines provide direct input only to the CLB clock pins.
The global lines also connect to the General Routing
Matrix to provide access from these lines to the function
generators and other control signals.
VersaRing
Four clock input pads at the corners of the chip, as shown
in Figure 12, provide a high-speed, low-skew clock
network to each of the four global-line buffers. In addition
to the dedicated pad, the global lines can be sourced by
internal logic. PIPs from several routing channels within
the VersaRing, inside the IOI cell, can also be configured
to drive the global-line buffers.
8
2
8
8
2
2
Pad
2
GRM
VersaRing Input/Output Interface
Pad
10
Interconnect
The VersaRing, shown in Figure 13, is positioned between
the core logic and the pad ring; it has all the routing
resources of a VersaBlock without the CLB logic. The
VersaRing decouples the pad ring’s pitch from the core’s
pitch. Each VersaRing Cell provides up to four pad-cell
connections on one side, and connects directly to the CLB
ports on the other side. Depending on placement and padcell pitch, any number of pad cells to a maximum of four
can be connected to a VersaRing cell. Note: there are no
direct connects from the Pads on top and bottom edges.
Pad
4
4
VersaBlock
Pad
8
8
2
Pad
2
GRM
Pad
10
Interconnect
Input/Output Pad
Pad
4
The I/O pad, shown in Figure 14, consists of an input buffer
and an output buffer. The output driver is an 8-mA full-rail
CMOS buffer with 3-state control. Two slew-rate control
modes are supported to minimize bus transients. Both the
output buffer and the 3-state control are invertible.
VersaBlock
4
Pad
2
8
2
8
X5705
Figure 13. VersaRing I/O Interface
GCK1
GCK4
Vcc
I
PAD
O
T
GCK2
GCK3
X4964
X5704
Figure 14. XC5200 I/O Block
Figure 12. Global Lines
16
R
Configuration
into the LCA data-frame format. The up and down
selection generates starting addresses at either zero or
3FFFF, to be compatible with different microprocessor
addressing conventions. The Master Serial Mode
generates CCLK and receives the configuration data in
serial form from configuration data in serial form from a
Xilinx serial-configuration PROM.
Configuration is the process of loading design-specific
programming data into one or more LCA devices to define
the functional operation of the internal blocks and their
interconnections. This is somewhat like loading the
command registers of a programmable peripheral chip.
Each configuration bit defines the state of a static memory
cell that controls either a function LUT bit, a multiplexer
input, or an interconnect pass transistor. The XACT
development system translates the design into a netlist
file. It automatically partitions, places, and routes the logic
and generates the configuration data in PROM format.
Peripheral Modes
The two Peripheral modes accept byte-wide data from a
bus. A READY/BUSY status is available as a handshake
signal. In the asynchronous mode, the internal oscillator
generates a CCLK burst signal that serializes the bytewide data. In the synchronous mode, an externally
supplied clock input to CCLK serializes the data.
Modes
Slave Serial Mode
In the Slave Serial mode, the LCA device receives serialconfiguration data on the rising edge of CCLK and, after
loading its configuration, passes additional data out,
resynchronized on the next falling edge of CCLK. Multiple
slave devices with identical configurations can be wired
with parallel DIN inputs so that the devices can be
configured simultaneously.
The XC5200 family has seven modes of configuration,
selected by a 3-bit input code applied to the LCA mode
pins (M0, M1, and M2). There are three self-clocking
Master modes, two Peripheral modes, a Slave serial
mode, and a new high-speed Slave parallel mode called
the Express. See Table 5.
Brief descriptions of the seven modes are provided below.
For details on all modes except Express, see pages 2-32
through 2-41 of the 1994 Xilinx Programmable Logic Data
Book.
Daisy Chaining
Multiple devices may be daisy-chained together so that
they may be programmed using a single bitstream. The
first device in the chain may be set to operate in any
mode. All devices except the first device in the chain must
be set to operate in Slave Serial mode.
Master Modes
The Master modes use an internal oscillator to generate
CCLK for driving potential slave devices, and to generate
address and timing for external PROM(s) containing the
configuration data. Master Parallel (up or down) modes
generate the CCLK signal and PROM addresses, and
receive byte parallel data, which is internally serialized
Table 5.
All CCLK pins are tied together and the data chain passes
from DOUT to DIN of successive devices along the chain.
Configuration Modes
Mode
M2
M1
M0
CCLK
Data
Master Serial
0
0
0
output
Bit-Serial
Slave Serial
1
1
1
input
Bit-Serial
Master Parallel up
1
0
0
output
Byte-Wide, 00000 ↑
Master Parallel down
1
1
0
output
Byte-Wide, 3FFFF ↓
Peripheral Synchronous *
0
1
1
input
Byte-Wide
Peripheral Asynchronous
1
0
1
output
Byte-Wide
Express
0
1
0
input
Byte-Wide
Reserved
0
0
1
—
—
* Peripheral Synchronous can be considered byte-wide Slave Parallel
17
XC5200 Logic Cell Array Family
Preliminary
+5V
M0
M1
CS1
M2
M0
CS1
DOUT
D0-D7
DATA BUS
+5V
INIT
M2
To Additional
Optional
Daisy-Chained
Devices
DOUT
D0-D7
Optional
Daisy-Chained
XC5200
XC5200
5K
PROGRAM
M1
PROGRAM
PROGRAM
INIT
INIT
CCLK
CCLK
CCLK
X6153
To Additional
Optional
Daisy-Chained
Devices
Figure 15. Express Mode
Express Mode
The Express mode (see Figure 15) is similar to the Slave
serial mode, except that data is processed one byte per
CCLK cycle instead of one bit per CCLK cycle. An
external source is used to drive CCLK while byte-wide
data is loaded directly into the configuration data shift
registers. In this mode the XC5200 family is capable of
supporting a CCLK frequency of 10 MHz, which is
equivalent to an 80-MHz serial rate, because eight bits of
configuration data are being loaded per CCLK cycle. An
XC5210 in the Express mode, for instance, can be
configured in about 2 ms. The Express mode does not
support CRC error checking, but does support constantfield error checking.
device is daisy-chained with devices from other Xilinx
families.
If the first device is configured in the Express mode,
additional devices may be daisy-chained only if every
device in the chain is also configured in the Express
mode. CCLK pins are tied together and D7-D0 pins are
tied together for all devices along the chain. A status
signal is passed from DOUT to CS1 of successive devices
along the chain. The lead device in the chain has its CS1
input tied High (or floating, since there is an internal pullup). All devices receive and recognize the preamble and
length count, but frame data is accepted only when CS1 is
High and the device’s configuration memory is not already
full. The status pin DOUT is pulled LOW two internaloscillator cycles (nominally 1 MHz per cycle) after INIT is
recognized as High, and remains Low until the device’s
configuration memory is full. Then DOUT is pulled High to
signal the next device in the chain to accept the
configuration data on the D7-D0 bus.
In the Express configuration mode, an external signal
drives the CCLK input(s) of the LCA device(s). The first
bytes of parallel configuration data must be available at
the D inputs of the LCA devices a short set-up time before
each rising CCLK edge. Subsequent data bytes are
clocked in on each consecutive rising CCLK edge. See
Figure 16.
How to Delay Configuration After Power-Up
The Express mode is only supported by the XC5200
family. It may not be used, therefore, when an XC5200
For details on how to delay configuration after power-up,
refer to page 2-32 of the 1994 Xilinx Programmable Logic
Data Book.
18
R
CCLK
1
TIC
INIT
TCD 3
2 T
DC
BYTE
0
D0-D7
BYTE
1
BYTE
2
BYTE
3
Serial Data Out
(DOUT)
LCA Filled
Internal INIT
RDY/BUSY
CS1
X6154
Description
CCLK
Symbol
Min
Max
Units
INIT (High) Setup time required
1
TIC
5
µs
DIN Setup time required
2
TDC
50
ns
3
TCD
0
ns
CCLK High time
TCCH
50
ns
CCLK Low time
TCCL
50
ns
CCLK Frequency
FCC
DIN Hold time required
10
MHz
Preliminary
Figure 16. Express Mode Programming Switching Characteristics
Clear Internal Logic
When reprogramming the XC5200 chip, a contention-free
state must be reached before memory initialization can
begin. In this state internal control lines sequence
activities in the following order: long lines are disabled,
output drivers are forced Low, and interconnect lines are
discharged. Each of these operations requires one cycle
of the 1-MHz Initialization clock. This sequencing is
important only when reprogramming, because the
contention-free state is immediately entered when
configuring from a power-on state.
Format
Table 6 describes the XC5200 configuration data stream.
Table 7 provides details of the internal configuration data
structure.
Configuration Sequence
Figure 17 illustrates the XC5200 start-up sequence. It is
described in detail in the sections below.
19
XC5200 Logic Cell Array Family
Unified XC5200 Bitstream Format
Data Type
Value
Fill Byte
11111111
Preamble
11110010
Length Counter
COUNT(23:0)
Fill Byte
11111111
Start Byte
11111110
Data Frame *
DATA(N-1:0)
Cyclic Redundancy Check or
Constant Field Check
CRC(3:0) or
0110
Fill Nibble
1111
Extend Write Cycle
FFFFFF
Postamble
11111110
Fill Bytes (30)
FFFF…FF
VCC
3V
Boundary Scan
Instructions
Available:
No
Yes
Generate
One Time-Out Pulse
of 4 ms
PROGRAM
= Low
Yes
EXTEST*
SAMPLE/PRELOAD*
BYPASS
CONFIGURE*
Completely Clear
Configuration
Memory
~1.3 µs per Frame
(*only when PROGRAM = High)
INIT
High? if
Master
Yes
No
Sample
Mode Lines
Master CCLK
Goes Active after
50 to 250 µs
Load One
Configuration
Data Frame
Frame
Error
Legend:
Yes
Pull INIT Low
and Stop
LDC Output = L, HDC Output = H
Table 6.
Preliminary
No
(unshaded)
Only once per bitstream
(light)
Once per data frame
(dark)
Once per device
Configuration
memory
Full
Yes
No
Pass
Configuration
Data to DOUT
CCLK
Count Equals
Length
Count
Yes
Internal Configuration Data Structure
Device
VersaBlock
Array
PROM
Size
(bits)
Xilinx
Serial Prom
Needed
XC5202
8x8
42,448
XC1765
XC5204
10 x 12
70,736
XC1728
XC5206
14 x 14
106,320
XC17128
XC5210
18 x 18
165,520
XC17256
XC5215
22 x 22
237,776
XC17256
No
Start-Up
Sequence
F
EXTEST
SAMPLE PRELOAD
BYPASS
USER 1
USER 2
CONFIGURE
READBACK
Operational
If Boundary Scan
is Selected
Figure 17. Start-up Sequence
Bits per Frame = (34 x number of Rows) + 28 for the
top + 28 for the bottom + 4 splitter bits + 8 start bits + 8
error check bits + 4 fill bits + 4 extended write bits
Number of Frames = (12 x number of Columns) + 7 for
the left edge + 8 for the right edge + 1 splitter bit
Program Data = (Bits per Frame x Number of Frames)
+ 48 header bits + 8 postamble bits + 280 fill bits
PROM Size = Program Data
20
I/O Active
Table 7.
SAMPLE/PRELOAD
BYPASS
X6037
R
Clear Address Registers
During this phase the configuration address registers are
cleared to ensure that they will contain at most a single
token at all times. Prior to memory initialization, the
XC5200 device eliminates the possibility of multiple
tokens within the address register, as is typically the case
when powering on.
Configuration
The length counter begins counting immediately upon
entry into the configuration state. In slave-mode operation
it is important to wait at least two cycles of the internal
1-MHz clock oscillator after INIT is recognized before
toggling CCLK and feeding the serial bitstream.
Configuration will not begin until the internal configuration
logic reset is released, which happens two cycles after
INIT goes High. A master device’s configuration is
delayed from 32 to 256 µs to ensure proper operation with
any slave devices driven by the master device.
Power-On Time-Out
An internal power-on reset circuit is triggered when power
is applied. When VCC reaches the voltage at which
portions of the LCA begin to operate (i.e., performs a
write-and-read test of a sample pair of configuration
memory bits), the programmable I/O buffers are 3-stated
with active high-impedance pull-up resistors. A time-out
delay — nominally 4 ms — is initiated to allow the powersupply voltage to stabilize. For correct operation the
power supply must reach VCC(min) by the end of the timeout, and must not dip below it thereafter.
A preamble field at the beginning of the configuration data
stream indicates that the next 24 bits represent the length
count. The length count equals the total number of
configuration bits needed to load the complete
configuration data to all daisy-chained devices. Once the
preamble and length-count values have been passed
through to the next device in the daisy-chain, DOUT is
held High to prevent start bits from reaching any daisychained devices. After fully configuring itself, the device
passes serial data to downstream daisy-chained devices
via DOUT until the full length count is reached.
There is no distinction between master and slave modes
with regard to the time-out delay. Instead, the INIT line is
used to ensure that all daisy-chained devices have
completed initialization. Since XC2000 devices do not
have this signal, extra care must be taken to guarantee
proper operation when daisy-chaining them with XC5200
devices. For proper operation with XC3000 devices, the
RESET signal, which is used in XC3000 to delay
configuration, should be connected to INIT.
Errors in the configuration bitstream are checked at the
end of a frame of data. The device does not check the
preamble or length count for errors. In a daisy-chained
configuration, configuration data for downstream devices
are not checked for errors. If an error is detected after
reading a frame, the ERR pin (also known as INIT) is
immediately pulled Low and all configuration activity
ceases. However, a master or Peripheral Asynchronous
device will continue outputting a configuration clock and
incrementing the PROM address indefinitely even though
it will never complete configuration. A reprogram or
power-on must be applied to remove the device from this
state.
If the time-out delay is insufficient, configuration should be
delayed by holding the INIT pin Low until the power supply
has reached operating levels.
During all three phases — Power-on, Initialization, and
Configuration — DONE is held Low; HDC, LDC, and INIT
are active; DOUT is driven; and all I/O buffers are
disabled.
Start-Up and Operation
The XC5200 start-up sequence is identical to that of the
XC4000 family. Each of these events may occur in any
order: (a) DONE is pulled High; and/or (b) user I/Os
become active; and/or (c) Internal Reset is deactivated.
As a configuration option, the three events may be
triggered by a user clock rather than by CCLK, or the startup sequence may be delayed by externally holding the
DONE pin Low.
Initialization
This phase clears the configuration memory and
establishes the configuration mode.
The configuration memory is cleared at the rate of one
frame per internal clock cycle (nominally 1 MHz). An opendrain bidirectional signal, INIT, is released when the
configuration memory is completely cleared. The device
then tests for the absence of an external active-low level
on INIT. The mode lines are sampled two internal clock
cycles later (nominally 2 µs).
In any mode, the clock cycles of the start-up sequence
hare not included in the length count. The length of the
bitstream is greater than the length count.
The master device waits an additional 32 µs to 256 µs
(nominally 64-128 µs) to provide adequate time for all of
the slave devices to recognize the release of INIT as well.
Then the master device enters the Configuration phase.
21
XC5200 Logic Cell Array Family
Preliminary
Pin Functions During Configuration
CONFIGURATION MODE:
SLAVE
<1:1:1>
MASTER-SER
<0:0:0>
SYN.PERIPH
<0:1:1>
<M2:M1:M0>
ASYN.PERIPH
<1:0:1>
MASTER-HIGH
<1:1:0>
MASTER-LOW
<1:0:0>
A16
A17
TDI
TCK
TMS
TDI
TCK
TMS
TDI
TCK
TMS
TDI
TCK
TMS
TDI
TCK
TMS
A16
A17
TDI
TCK
TMS
M1 (HIGH) (I)
M0 (HIGH) (I)
M2 (HIGH) (I)
M1 (LOW) (I)
M0 (LOW) (I)
M2 (LOW) (I)
M1 (HIGH) (I)
M0 (HIGH) (I)
M2 (LOW) (I)
M1 (LOW) (I)
M0 (HIGH) (I)
M2 (HIGH) (I)
M1 (HIGH) (I)
M0 (LOW) (I)
M2 (HIGH) (I)
M1 (LOW) (I)
M0 (LOW) (I)
M2 (HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT-ERROR
HDC (HIGH)
LDC (LOW)
INIT-ERROR
HDC (HIGH)
LDC (LOW)
INIT-ERROR
HDC (HIGH)
LDC (LOW)
INIT-ERROR
HDC (HIGH)
LDC (LOW)
INIT-ERROR
HDC (HIGH)
LDC (LOW)
INIT-ERROR
DONE
PROGRAM (I)
DONE
PROGRAM (I)
DONE
PROGRAM (I)
DATA 7 (I)
DONE
PROGRAM (I)
DATA 7 (I)
DONE
PROGRAM (I)
DATA 7 (I)
DONE
PROGRAM (I)
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 6 (I)
DATA 5 (I)
CSO (I)
DATA 4 (I)
DATA 3 (I)
RS (I)
DATA 2 (I)
DATA 1 (I)
RDY/BUSY
DATA 0 (I)
DOUT
CCLK (O)
TDO
WS (I)
DATA 6 (I)
DATA 5 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
RCLK
DATA 0 (I)
DOUT
CCLK (O)
TDO
A0
A1
A2
A3
A4
A5
A6
A7
DATA 2 (I)
DATA 1 (I)
RCLK
DATA 0 (I)
DOUT
CCLK (O)
TDO
A0
A1
A2
A3
A4
A5
A6
A7
A8
A8
A9
A10
A11
A12
A13
A14
A15
A9
A10
A11
A12
A13
A14
A15
DATA 4 (I)
DATA 3 (I)
DIN (I)
DOUT
CCLK (I)
TDO
DIN (I)
DOUT
CCLK (O)
TDO
DATA 2 (I)
DATA 1 (I)
RDY/BUSY
DATA 0 (I)
DOUT
CCLK (I)
TDO
CS1 (I)
USER
OPERATION
GCK1-I/O
I/O
TDI-I/O
TCK-I/O
TMS-I/O
I/O
I/O
I/O
I/O
GCK2-I/O
I/O
I/O
I/O
I/O
DONE
PROGRAM
I/O
GCK3-I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CCLK (I)
TDO-I/O
I/O
GCK4-I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ALL OTHERS
Represents a 50-kΩ to 100-kΩ pull-up before and during configuration
* INIT is an open-drain output during configuration
(I) Represents an input
(O) Represents an output
Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a
50-kΩ to 100-kΩ pull-up resistor.
22
R
Pin Descriptions
Permanently Dedicated Pins
User I/O Pins That Can Have Special Functions
Vcc
RDY/BUSY
Eight or more (depending on package type) connections
to the nominal +5-V supply voltage. All must be
connected.
During peripheral modes, this pin indicates when it is
appropriate to write another byte of data into the LCA
device. The same status is also available on D7 in
Asynchronous Peripheral mode, if a read operation is
performed when the device is selected. After
configuration, this is a user-programmable I/O pin.
GND
Eight or more (depending on package type) connections
to ground. All must be connected.
RCLK
During Master Parallel configuration, each change on the
A0-15 outputs is preceded by a rising edge on RCLK, a
redundant output signal. After configuration, this is a userprogrammable I/O pin.
CCLK
During configuration, Configuration Clock is an output of
the LCA in master modes or Asynchronous Peripheral
mode, but is an input to the LCA in Slave Serial mode and
Synchronous Peripheral mode.
M0, M1, M2
After configuration, CCLK has a weak pull-up resistor and
can be selected as Readback Clock.
As mode inputs, these pins are sampled before the start of
configuration to determine the configuration mode to be
used.
DONE
After configuration, M0, M1, and M2 become userprogrammable I/O.
This is a bidirectional signal with optional pull-up resistor.
As an output, it indicates the completion of the
configuration process. The configuration program
determines the exact timing, the clock source for the Lowto-High transition, and enable of the pull-up resistor.
TDO
If boundary scan is used, this is the Test Data Output.
If boundary scan is not used, this pin becomes userprogrammable I/O.
As an input, a Low level on DONE can be configured to
delay the global logic initialization or the enabling of
outputs.
TDI, TCK, TMS
If boundary scan is used, these pins are Test Data In, Test
Clock, and Test Mode Select inputs, respectively, coming
directly from the pads, bypassing the IOBs. These pins
can also be used as inputs to the CLB logic after
configuration is completed.
PROGRAM
This is an active-Low input, held Low during configuration,
that forces the LCA to clear its configuration memory.
When PROGRAM goes High, the LCA executes a
complete clear cycle, before it goes into a WAIT state and
releases INIT. After configuration, it has an optional pullup resistor.
If the boundary scan option is not selected, all boundary
scan functions are inhibited once configuration is
completed. These pins become user-programmable I/O.
HDC
High During Configuration is driven High until
configuration is completed. It is available as a control
output indicating that configuration is not yet completed.
After configuration, this is a user-programmable I/O pin.
23
XC5200 Logic Cell Array Family
Preliminary
Pin Descriptions
LDC
D0 - D7
Low During Configuration is driven Low until configuration
completes. It is available as a control output indicating that
configuration is not yet completed. After configuration, this
is a user-programmable I/O pin.
During Master Parallel and peripheral configuration
modes, these eight input pins receive configuration data.
After configuration, they are user-programmable I/O pins.
DIN
INIT
During Slave Serial or Master Serial configuration modes,
this is the serial configuration data input receiving data on
the rising edge of CCLK.
Before and during configuration, this is a bidirectional
signal. An external pull-up resistor is recommended.
As an active-Low open-drain output, INIT is held Low
during the power stabilization and internal clearing of the
configuration memory. As an active-Low input, it can be
used to hold the LCA device in the internal WAIT state
before the start of configuration. Master-mode devices
stay in a WAIT state an additional 30 to 300 µs after INIT
has gone High.
During parallel configuration modes, this is the D0 input.
After configuration, DIN is a user-programmable I/O pin.
DOUT
During configuration in any mode, this is the serial
configuration data output that can drive the DIN of daisychained slave LCA devices. DOUT data changes on the
falling edge of CCLK, 1.5 CCLK periods after it was
received at the DIN input. After configuration, DOUT is a
user-programmable I/O pins.
During configuration, a Low on this output indicates that a
configuration data error has occurred. After configuration,
this is a user-programmable I/O pin.
GCK1 - GCK4
Unrestricted User-Programmable I/O Pins
Four Global Inputs each drive a dedicated internal global
net with short delay and minimal skew. If not used for this
purpose, any of these pins is a user-programmable I/O
pin.
I/O
A pin that can be configured to be input and/or output after
configuration is completed. Before configuration is
completed, these pins have an internal high-value pull-up
resistor that defines the logical level as High.
CS0, CS1, WS, RS
These four inputs are used in peripheral modes. The chip
is selected when CS0 is Low and CS1 is High. While the
chip is selected, a Low on Write Strobe (WS) loads the
data present on the D0 - D7 inputs into the internal data
buffer; a Low on Read Strobe (RS) changes D7 into a
status output: High if Ready, Low if Busy, and D0…D6 are
active Low. WS and RS should be mutually exclusive, but
if both are Low simultaneously, the Write Strobe overrides.
After configuration, these are user-programmable I/O
pins.
A0 - A17
During Master Parallel mode, these 18 output pins
address the configuration EPROM. After configuration,
these are user-programmable I/O pins.
Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a
50-kΩ to 100-kΩ pull-up resistor.
24
R
Absolute Maximum Ratings
Symbol
Description
Units
VCC
Supply voltage relative to GND
-0.5 to +7.0
V
VIN
Input voltage with respect to GND
-0.5 to VCC +0.5
V
VTS
Voltage applied to 3-state output
-0.5 to VCC +0.5
V
TSTG
Storage temperature (ambient)
-65 to +150
°C
TSOL
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
+260
°C
Junction temperature in plastic packages
+125
°C
Junction temperature in ceramic packages
+150
°C
TJ
Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings
conditions for extended periods of time may affect device reliability.
Operating Conditions
Symbol
VCC
Description
Supply voltage relative to GND
Commercial:
Supply voltage relative to GND
Industrial:
Supply voltage relative to GND
Military:
Min
Max
4.75
5.25
V
-40°C to 85°C
4.5
5.5
V
-55°C to 125°C
4.5
5.5
V
0°C to 70°C
Units
VIHT
High-level input voltage — TTL configuration
2.0
VCC
V
VILT
Low-level input voltage — TTL configuration
0
0.8
V
VIHC
High-level input voltage — CMOS configuration
70%
100%
VCC
VILC
Low-level input voltage — CMOS configuration
0
20%
VCC
TIN
Input signal transition time
250
ns
DC Characteristics Over Operating Conditions
Symbol
Description
Min
VOH
High-level output voltage @ IOH = -8.0 mA, VCC min
3.86
VOL
Low-level output voltage @ IOL = 8.0 mA, VCC max (Note 1)
0.4
V
ICCO
Quiescent LCA supply current (Note 1)
15
mA
IIL
Leakage current
+10
µA
CIN
Input capacitance (sample tested)
15
pF
IRIN
Pad pull-up (when selected) @ VIN = 0V (sample tested)
0.25
mA
-10
0.02
Max
Units
V
Note: 1. With no output current loads, all package pins at VCC or GND, and the LCA configured with a MakeBits tie option.
25
XC5200 Logic Cell Array Family
Preliminary
Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from
benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating
conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the
XACT timing calculator and used in the simulator.
Speed Grade
Description
-6
-5
-4
Max
(ns)
Max
(ns)
Max
(ns)
XC5206
9.4
8.8
XC5210
9.4
8.8
XC5206
9.9
8.9
XC5210
9.9
8.9
XC5206
14.8
12.7
XC5210
14.8
12.7
Symbol
Device
TBUFG
XC5202
Global Signal Distribution
From pad through global buffer, to any clock (CK)
XC5204
XC5215
Internal Clock to Output Pad Delay
From clock (CK) to output pad (fast), using direct connect
between Q and output (O)
TOKPOF
XC5202
XC5204
XC5215
From clock (CK) to output pad (slew-limited), using direct
connect between Q and output (O)
TOKPOS
XC5202
XC5204
XC5215
Note:
1.
Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array
size.
26
R
Longline Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from
benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating
conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the
XACT timing calculator and used in the simulator.
Speed Grade
Description
-6
-5
-4
Max
(ns)
Max
(ns)
Max
(ns)
XC5206
4.0
3.6
XC5210
4.0
3.6
XC5206
5.3
4.8
XC5210
5.3
4.8
XC5206
2.4
2.2
XC5210
2.4
2.2
Symbol
Device
TIO
XC5202
TBUF driving a Longline
TS
I
O
TBUF
I to Longline, while TS is Low; i.e., buffer is constantly active
XC5204
XC5215
TS going Low to Longline going from floating High or Low to
active Low or High
TON
XC5202
XC5204
XC5215
TS going High to TBUF going inactive, not driving Longline
TOFF
XC5202
XC5204
XC5215
Note:
1.
Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array
size.
27
XC5200 Logic Cell Array Family
Preliminary
Guaranteed Input and Output Parameters (Pin-to-Pin)
All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also
be derived indirectly from the Global Buffer specifications. The XACT delay calculator uses this indirect method, and may
overestimate because of worst-case assumptions. When there is a discrepancy between these two methods, the values
listed below should be used, and the derived values should be considered conservative overestimates.
Speed Grade
Description
Global Clock to Output Pad (fast)
CLB
TBUFG
Direct
Connect
-4
Max
(ns)
Max
(ns)
Max
(ns)
XC5206
17.2
15.4
XC5210
17.2
15.4
XC5206
21.7
19.0
XC5210
21.7
19.0
XC5206
1.2
0.5
XC5210
1.2
0.5
XC5206
3.0
2.5
XC5210
3.0
2.5
XC5206
7.5
6.4
XC5210
7.5
6.4
XC5206
0
0
XC5210
0
0
Symbol
Device
TICKOF
XC5202
(Max)
.
.
.
.
Global Clock-to-Output Delay
-5
XC5204
IOB
FD
-6
XC5215
Global Clock to Output Pad (slew-limited)
CLB
TBUFG
Direct
Connect
TICKO
XC5204
IOB
(Max)
.
.
.
.
FD
Global Clock-to-Output Delay
XC5202
XC5215
Input Set-up Time (no delay) to CLB Flip-Flop
IOB
Input
Set-up
& Hold
Time
Direct
Connect
TPSUF
XC5204
CLB
(Min)
FD
TBUFG
XC5215
Input Hold Time (no delay) to CLB Flip-Flop
IOB
Input
Set-up
& Hold
Time
Direct
Connect
TPHF
(Min)
TBUFG
XC5215
Input Set-up Time (with delay) to CLB Flip-Flop
Input
Set-up
& Hold
Time
Direct
Connect
TPSU
(Min)
TBUFG
XC5215
Input Hold Time (with delay) to CLB Flip-Flop
IOB
Direct
Connect
TPH
(Min)
FD
1.
2.
3.
XC5202
XC5204
CLB
TBUFG
Note:
XC5202
XC5204
CLB
FD
Input
Set-up
& Hold
Time
XC5202
XC5204
CLB
FD
IOB
XC5202
XC5215
These measurements assume that the flip-flop has a direct connect to or from the IOB. XACT-Performance can be
used to assure that direct connects are used.
When testing outputs (fast or slew-limited), half of the outputs on one side of the device are switching.
Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array
size.
28
R
IOB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from
benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating
conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the
XACT timing calculator and used in the simulator.
Speed Grade
Description
Symbol
-6
-5
-4
Max
(ns)
Max
(ns)
Max
(ns)
Input
Propagation Delays from CMOS or TTL Levels
Pad to I (no delay)
TPI
5.4
4.9
Pad to I (with delay)
TPID
11.1
10.2
Output (O) to Pad (fast)
TOPF
4.6
4.5
Output (O) to Pad (slew-limited)
TOPS
9.4
8.3
3-state to Pad active (fast)
TTSONF
6.9
6.6
Output
Propagation Delays to CMOS or TTL Levels
3-state to Pad active (slew-limited)
TTSONS
11.6
10.4
Internal GTS to Pad active (fast)
TGTSF
17.7
15.9
Internal GTS to Pad active (slew-limited)
TGTSS
22.3
19.7
Note:
1.
2.
Timing is measured at pin threshold, with 50-pF external capacitance loads. Slew-limited output rise/fall times are
approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce,
see pages 8-8 through 8-10 of the 1994 Xilinx Programmable Logic Data Book.
Unused and unbonded IOBs are configured by default as inputs with internal pull-up resistors.
29
XC5200 Logic Cell Array Family
Preliminary
CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from
benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating
conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the
XACT timing calculator and used in the simulator.
Speed Grade
Description
Symbol
-6
Min
(ns)
-5
Max
(ns)
Min
(ns)
-4
Max
(ns)
Combinatorial Delays
F inputs to X output
DI inputs to DO output (Logic-Cell Feedthrough)
F inputs via F5_MUX to DO output
TILO
TIDO
TIMO
5.5
4.2
7.1
4.5
3.3
5.7
Carry Delays
Incremental delay per bit
Carry-in overhead from DI
Carry-in overhead from F
Carry-out overhead to DO
TCY
TCYDI
TCYL
TCYO
0.7
1.7
3.6
3.9
0.6
1.5
3.2
3.1
Sequential Delays
Clock (CK) to out (Q) (Flip-Flop)
Gate (Latch enable) going active to out (Q)
TCKO
TGO
5.4
8.6
4.4
6.8
Set-up Time Before Clock (CK)
F inputs
F inputs via F5_MUX
DI input
CE input
TICK
TMICK
TDICK
TEICK
2.1
3.6
0.5
1.2
1.5
2.7
0.3
0.9
Hold Times After Clock (CK)
F inputs
F inputs via F5_MUX
DI input
CE input
TCKI
TCKMI
TCKDI
TCKEI
0
0
0
0
0
0
0
0
Clock Widths
Clock High Time
Clock Low Time
TCH
TCL
6.0
6.0
6.0
6.0
Reset Delays
Width (High)
Delay from CLR to Q (Flip-Flop)
Delay from CLR to Q (Latch)
TCLRW
TCLR
TCLRL
6.0
Global Reset Delays (see Note 2)
Width (High)
Delay from internal GCLR to Q
TGCLRW
TGCLR
6.0
Note:
1.
2.
Min
(ns)
Max
(ns)
6.0
7.3
6.1
5.8
4.8
6.0
12.4
10.2
The CLB K to Q output delay (TCKO) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold-time requirement (TCKDI) of any CLB on the same die.
Timing is based upon the XC5210 device. For other devices, see XACT Timing Calculator.
30
R
31
XC5200 Logic Cell Array Family
Preliminary (v1.0)
Top
R1C1
R1C2
R1C3
R1C4
R1C5
R1C6
R1C7
R1C8
R1C9
R1C10 R1C11 R1C12 R1C13 R1C14
R2C1
R2C14
R3C1
R3C14
R4C1
R4C14
R5C1
R5C14
R6C1
R6C14
R7C1
R7C14
R8C1
R8C14
R9C1
R9C14
R10C1
R10C14
R11C1
R11C14
R12C1
R12C14
R13C1
R13C14
Left
Right
R14C1 R14C2 R14C3 R14C4 R14C5 R14C6 R14C7 R14C8 R14C9 R14C10 R14C11 R14C12 R14C13 R14C14
Bottom
KEY:
I/O Pad
R#C#
CLB, identified by R#C# = row and column numbers
Figure 18. XC5206 CLB-to-Pad Relationship
32
R
Left
19
20
21
22
23
24
25
26
Bottom
R1C1
R2C1
R3C1
57
58
59
60
61
62
63
Right
Top
R1C1
18
17
127
126
125
R1C2
16
15
R3C14
124
123
122
R1C3
14
13
R14C1
R1C14
R14C2
R2C14
R14C3
129
128
R4C1
64
65
66
R14C4
R4C14
121
120
119
R1C4
12
11
10
R5C1
67
68
69
R14C5
R5C14
118
117
116
R1C5
9
8
7
R6C1
70
71
72
R14C6
R6C14
R1C6
6
5
4
R7C1
73
74
75
R14C7
R7C14
R1C7
3
2
1
37
38
39
R8C1
76
77
78
R14C8
R8C14
R1C8
148
147
146
40
41
42
R9C1
79
80
81
R14C9
R9C14
109
108
107
R1C9
145
144
143
43
44
45
R10C1
82
83
84
R14C10
R10C14
106
105
104
R1C10
142
141
140
46
47
48
R11C1
85
86
R14C11
R11C14
R12C1
87
88
R14C12
R12C14
101
100
99
R1C12
137
136
135
R14C13
R13C14
98
97
96
R1C13
134
133
132
R14C14
R14C14
27
28
29
30
31
32
33
34
35
36
49
50
51
52
53
54
55
56
Note:
R13C1
R14C1
89
90
91
92
93
115
114
113
112
111
110
103
102
R1C11
139
138
131
95
94
R1C14
130
Pad numbers (1, 2, …, 148) refer to die pads, not external device pins. Also see the XC5206 pinout table on pages 36-37.
Figure 19. XC5206 CLB-to-Pad Relationship (Detail)
33
XC5200 Logic Cell Array Family
Preliminary (v1.0)
Top
R1C1
R1C2
R1C3
R1C4
R1C5
R1C6
R1C7
R1C8
R1C9
R1C10 R1C11 R1C12 R1C13 R1C14 R1C15 R1C16 R1C17 R1C18
R2C1
R2C18
R3C1
R3C18
R4C1
R4C18
R5C1
R5C18
R6C1
R6C18
R7C1
R7C18
R8C1
R8C18
R9C1
R9C18
R10C1
R10C18
R11C1
R11C18
R12C1
R12C18
R13C1
R13C18
R14C1
R14C18
R15C1
R15C18
R16C1
R16C18
R17C1
R17C18
Left
Right
R18C1 R18C2 R18C3 R18C4 R18C5 R18C6 R18C7 R18C8 R18C9 R18C10 R18C11 R18C12 R18C13 R18C14 R18C15 R18C16 R18C17 R18C18
Bottom
KEY:
I/O Pad
R#C#
CLB, identified by R#C# = row and column numbers
Figure 20. XC5210 CLB-to-Pad Relationship
34
R
Left
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Bottom
R1C1
75
76
Right
Top
R18C1
R1C18
171
170
R1C1
24
23
R2C1
77
78
79
R18C2
R2C18
169
168
167
R1C2
22
21
20
R3C1
80
81
82
R18C3
R3C18
166
165
164
R1C3
19
18
17
R4C1
83
84
85
R18C4
R4C18
163
162
161
R1C4
16
15
14
R5C1
86
87
88
R18C5
R5C18
160
159
158
R1C5
13
12
R18C6
R6C18
157
156
155
R1C6
11
10
154
153
152
R1C7
9
8
7
R1C8
6
5
4
R1C9
3
2
1
R1C10
196
195
194
89
90
39
40
41
R6C1
42
43
44
R7C1
91
92
93
R18C7
R7C18
R8C1
94
95
96
R18C8
R8C18
R9C1
97
98
99
R18C9
R9C18
49
50
51
R10C1
100
101
102
R18C10
R10C18
52
53
54
R11C1
103
104
105
R18C11
R11C18
145
144
143
R1C11
193
192
191
R12C1
106
107
108
R18C12
R12C18
142
141
140
R1C12
190
189
188
139
138
137
R1C13
45
46
47
48
55
56
57
151
150
R13C1
109
110
R18C13
R13C18
R14C1
111
112
R18C14
R14C18
64
65
66
R15C1
113
114
115
R18C15
R15C18
67
68
69
R16C1
116
117
118
R18C16
70
71
72
R17C1
119
120
121
58
59
60
61
62
63
73
74
Note:
R18C1
122
123
149
148
147
146
187
186
R1C14
185
184
183
134
133
132
R1C15
182
181
180
R16C18
131
130
129
R1C16
179
178
177
R18C17
R17C18
128
127
126
R1C17
176
175
174
R18C18
R18C18
136
135
173
125
124
R1C18
172
Pad numbers (1, 2, …, 196) refer to die pads, not external device pins. Also see the XC5210 pinout table on pages 38-39.
Figure 21. XC5210 CLB-to-Pad Relationship (Detail)
35
XC5200 Logic Cell Array Family
Preliminary (v1.0)
XC5206 Pinouts
Pin Description †
PC84
PQ160
PQ208
PG191
Boundary
Scan Order
Pin Description †
PC84
PQ160
PQ208
PG191
Boundary
Scan Order
VCC
2
142
183
J4
-
37.
I/O
23
21
27
C10
255
1.
I/O (A8)
3
143
184
J3
87
38.
I/O
24
22
28
B10
258
2.
I/O (A9)
4
144
185
J2
90
39.
I/O
-
23
29
A9
261
3.
I/O
-
145
186
J1
93
40.
I/O
-
24
30
A10
267
4.
I/O
-
146
187
H1
99
41.
I/O
-
-
31
A11
270
5.
I/O
-
-
188
H2
102
42.
I/O
-
-
32
C11
273
6.
I/O
-
-
189
H3
105
43.
I/O
25
25
33
B11
279
7.
I/O (A10)
5
147
190
G1
111
44.
I/O
26
26
34
A12
282
8.
I/O (A11)
6
148
191
G2
114
45.
I/O
-
27
35
B12
285
9.
I/O
-
149
192
F1
117
46.
I/O
-
28
36
A13
291
10.
I/O
-
150
193
E1
123
GND
-
29
37
C12
-
GND
-
151
194
G3
-
-
-
-
38*
-
-
-
-
-
195*
-
-
-
-
-
39*
-
-
-
-
-
196*
-
-
47.
I/O
-
30
40
A15
294
297
11.
I/O
-
152
197
C1
126
48.
I/O
-
31
41
C13
12.
I/O
-
153
198
E2
129
49.
I/O
27
32
42
B14
303
13.
I/O (A12)
7
154
199
F3
138
50.
I/O
-
33
43
A16
306
14.
I/O (A13)
8
155
200
D2
141
51.
I/O
-
34
44
B15
309
15.
I/O
-
156
201
B1
150
52.
I/O
-
35
45
C14
315
16.
I/O
-
157
202
E3
153
53.
I/O
28
36
46
A17
318
17.
I/O (A14)
9
158
203
C2
162
54.
I/O
29
37
47
B16
321
18.
I/O (A15)
10
159
204
B2
165
55.
M1 (I/O)
30
38
48
C15
330
VCC
GND
31
39
49
D15
-
M0 (I/O)
32
40
50
A18
333
-
-
-
51*
-
-
-
-
-
52*
-
-
-
-
-
-
53*
-
-
D4
-
-
-
-
54*
-
-
3*
-
-
VCC
33
41
55
D16
-
4
C3
174
57.
M2 (I/O)
34
42
56
C16
336
11
160
205
D3
-
-
-
-
206*
-
-
-
-
-
207*
-
-
-
-
-
208*
-
-
-
-
-
1*
-
12
1
2
-
2
GND
-
56.
19.
GCK1 (A16, I/O)
13
20.
I/O (A17)
14
3
5
C4
177
58.
GCK2 (I/O)
35
43
57
B17
339
21.
I/O
-
4
6
B3
183
59.
I/O (HDC)
36
44
58
E16
348
22.
I/O
-
5
7
C5
186
60.
I/O
-
45
59
C17
351
23.
I/O (TDI)
15
6
8
A2
189
61.
I/O
-
46
60
D17
354
24.
I/O (TCK)
16
7
9
B4
195
62.
I/O
-
47
61
B18
360
25.
I/O
-
8
10
C6
198
63.
I/O (LDC)
37
48
62
E17
363
26.
I/O
-
9
11
A3
201
64.
I/O
-
49
63
F16
372
-
-
-
12*
-
-
65.
I/O
-
50
64
C18
375
-
-
-
13*
-
-
GND
-
51
67
G16
-
GND
-
10
14
C7
-
66.
I/O
-
52
68
E18
378
27.
I/O
-
11
15
A4
207
67.
I/O
-
53
69
F18
384
28.
I/O
-
12
16
A5
210
68.
I/O
38
54
70
G17
387
29.
I/O (TMS)
17
13
17
B7
213
69.
I/O
39
55
71
G18
390
30.
I/O
18
14
18
A6
219
70.
I/O
-
-
72
H16
396
31.
I/O
-
-
19
C8
222
71.
I/O
-
-
73
H17
399
32.
I/O
-
-
20
A7
225
72.
I/O
-
56
74
H18
402
33.
I/O
-
15
21
B8
234
73.
I/O
-
57
75
J18
408
34.
I/O
-
16
22
A8
237
74.
I/O
40
58
76
J17
411
35.
I/O
19
17
23
B9
246
75.
I/O (ERR, INIT)
41
59
77
J16
414
36.
I/O
20
18
24
C9
249
VCC
42
60
78
J15
-
GND
21
19
25
D9
-
GND
43
61
79
K15
-
VCC
22
20
26
D10
-
I/O
44
62
80
K16
420
76.
†
* Indicates unconnected package pins.
36
Leading number refers to bonded pad, shown in Figure 19.
R
XC5206 Pinouts (continued)
Pin Description †
PC84
PQ160
PQ208
PG191
Boundary
Scan Order
Pin Description †
PC84
PQ160
PQ208
PG191
Boundary
Scan Order
77.
I/O
45
63
81
K17
423
112. I/O (D3)
65
102
132
T9
588
78.
I/O
-
64
82
K18
426
113. I/O (RS)
66
103
133
U9
591
79.
I/O
-
65
83
L18
432
114. I/O
-
104
134
V9
600
80.
I/O
-
-
84
L17
435
115. I/O
-
105
135
V8
603
81.
I/O
-
-
85
L16
438
116. I/O
-
-
136
U8
612
82.
I/O
46
66
86
M18
444
117. I/O
-
-
137
T8
615
83.
I/O
47
67
87
M17
447
118. I/O (D2)
67
106
138
V7
618
84.
I/O
-
68
88
N18
450
119. I/O
68
107
139
U7
624
85.
I/O
-
69
89
P18
456
120. I/O
-
108
140
V6
627
GND
-
70
90
M16
-
121. I/O
-
109
141
U6
630
-
-
-
91*
-
-
GND
-
110
142
T7
-
-
-
-
92*
-
-
-
-
-
143*
-
-
86.
I/O
-
71
93
T18
459
-
-
-
144*
-
-
87.
I/O
-
72
94
P17
468
122. I/O
-
111
145
U5
636
88.
I/O
48
73
95
N16
471
123. I/O
-
112
146
T6
639
89.
I/O
49
74
96
T17
480
124. I/O (D1)
69
113
147
V3
642
90.
I/O
-
75
97
R17
483
125. I/O (RCLK-
70
114
148
V2
648
91.
I/O
-
76
98
P16
486
92.
I/O
50
77
99
U18
492
126. I/O
-
115
149
U4
651
127. I/O
-
116
150
T5
654
128. I/O (D0, DIN)
71
117
151
U3
660
129. I/O (DOUT)
72
118
152
T4
663
CCLK
73
119
153
V1
-
VCC
74
120
154
R4
-
-
-
-
155*
-
-
-
-
-
156*
-
-
-
-
-
157*
-
-
-
-
-
158*
-
-
75
121
159
U2
-
93.
I/O
51
78
100
T16
495
GND
52
79
101
R16
-
DONE
-
-
102*
-
-
53
80
103
U17
-
-
-
-
104*
-
-
-
-
-
105*
-
-
54
81
106
R15
-
-
-
107*
-
-
VCC
PROG
55
82
108
V18
-
94.
I/O (D7)
56
83
109
T15
504
95.
GCK3 (I/O)
57
84
110
U16
507
96.
I/O
-
85
111
T14
516
97.
I/O
98.
I/O (D6)
99.
-
86
112
U15
519
58
87
113
V17
522
I/O
-
88
114
V16
528
100. I/O
-
89
115
T13
531
101. I/O
-
90
116
U14
534
-
-
-
117*
-
-
-
-
-
118*
-
-
GND
102. I/O
103. I/O
-
91
119
T12
-
-
92
120
U13
540
-
93
121
V13
543
104. I/O (D5)
59
94
122
U12
552
105. I/O (CS0)
60
95
123
V12
555
106. I/O
-
-
124
T11
558
107. I/O
-
-
125
U11
564
108. I/O
-
96
126
V11
567
-
97
127
V10
570
61
98
128
U10
576
109. I/O
110. I/O (D4)
111. I/O
VCC
GND
62
99
129
T10
579
63
100
130
R10
-
64
101
131
R9
BUSY/RDY)
130. (I/O) TDO
GND
76
122
160
R3
-
131. I/O (A0, WS)
77
123
161
T3
9
132.
78
124
162
U1
15
-
125
163
P3
18
I/O (GCK4, A1)
133. I/O
134. I/O
-
126
164
R2
21
135. I/O (CS1, A2)
79
127
165
T2
27
136. I/O (A3)
80
128
166
N3
30
137. I/O
-
129
167
P2
33
138. I/O
-
130
168
T1
42
-
-
-
169*
-
-
-
-
-
170*
-
-
GND
-
131
171
M3
-
-
132
172
P1
45
139. I/O
140. I/O
-
-
133
173
N1
51
141. I/O (A4)
81
134
174
M2
54
142. I/O (A5)
82
135
175
M1
57
143. I/O
-
-
176
L3
63
144. I/O
-
136
177
L2
66
145. I/O
-
137
178
L1
69
146. I/O
-
138
179
K1
75
147. I/O (A6)
83
139
180
K2
78
148. I/O (A7)
84
140
181
K3
81
1
141
182
K4
-
GND
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 666 = BSCAN.UPD
37
XC5200 Logic Cell Array Family
Preliminary (v1.0)
XC5210 Pinouts
Pin Description †
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
VCC
I/O (A8)
I/O (A9)
I/O
I/O
I/O
I/O
I/O (A10)
I/O (A11)
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O (A12)
I/O (A13)
I/O
I/O
I/O
I/O
I/O (A14)
I/O (A15)
VCC
GND
GCK1 (A16, I/O)
I/O (A17)
I/O
I/O
I/O (TDI)
I/O (TCK)
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O (TMS)
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
PC84
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Boundary
PQ160 PQ208 PG223 PQ240 Scan Order
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206*
207*
208*
1*
2
3*
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
J4
J3
J2
J1
H1
H2
H3
G1
G2
H4
G4
F1
E1
G3
F2
D1
C1
E2
F3
D2
F4
E4
B1
E3
C2
B2
D3
D4
C3
C4
B3
C5
A2
B4
C6
A3
B5
B6
D5
D6
C7
A4
A5
B7
A6
D7
D8
C8
A7
B8
A8
B9
C9
D9
D10
C10
212
213
214
215
216
217
218
219*
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22*
23
24
25
26
27
28
29
30
31
Pin Description †
50.
51.
52.
53.
54.
111
114
117
123
126
129
135
138
141
150
153
162
165
171
174
177
183
186
189
195
198
201
210
213
222
225
231
234
237
243
246
249
255
258
261
267
270
273
279
282
285
291
294
297
306
309
318
321
327
55.
56.
57.
58.
59.
60.
61.
62.
63.
64.
65.
66.
67.
68.
69.
70.
71.
72.
73.
74.
75.
76.
77.
78.
79.
80.
81.
82.
83.
84.
85.
86.
87.
88.
89.
90.
91.
92.
93.
94.
95.
96.
97.
98.
99.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M1 (I/O)
GND
M0 (I/O)
VCC
M2 (I/O)
GCK2 (I/O)
I/O (HDC)
I/O
I/O
I/O
I/O (LDC)
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (ERR, INIT)
VCC
GND
100. I/O
†
* Indicates unconnected package pins.
38
PC84
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Boundary
PQ160 PQ208 PG223 PQ240 Scan Order
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51*
52*
53*
54*
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
B10
A9
A10
A11
C11
D11
D12
B11
A12
B12
A13
C12
D13
D14
B13
A14
A15
C13
B14
A16
B15
C14
A17
B16
C15
D15
A18
D16
C16
B17
E16
C17
D17
B18
E17
F16
C18
D18
F17
E15
F15
G16
E18
F18
G17
G18
H16
H17
G15
H15
H18
J18
J17
J16
J15
K15
K16
32
33
34
35
36
37*
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83*
84
85
86
87
88
89
90
91
92
Leading number refers to bonded pad, shown in Figure 21.
330
333
339
342
345
351
354
357
363
366
369
375
378
381
387
390
393
399
402
405
411
414
417
426
429
432
435
444
447
450
456
459
462
468
471
474
480
483
486
492
495
504
507
510
516
519
522
528
531
534
540
R
XC5210 Pinouts (continued)
Pin Description †
101.
102.
103.
104.
105.
106.
107.
108.
109.
110.
111.
112.
113.
114.
115.
116.
117.
118.
119.
120.
121.
122.
123.
124.
125.
126.
127.
128.
129.
130.
131.
132.
133.
134.
135.
136.
137.
138.
139.
140.
141.
142.
143.
144.
145.
146.
147.
148.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
DONE
VCC
PROG
I/O (D7)
GCK3 (I/O)
I/O
I/O
I/O
I/O
I/O (D6)
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O (D5)
I/O (CS0)
I/O
I/O
I/O
I/O
I/O (D4)
I/O
VCC
GND
I/O (D3)
PC84
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
Boundary
PQ160 PQ208 PG223 PQ240 Scan Order
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102*
103
104*
105*
106
107*
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
K17
K18
L18
L17
L16
L15
M15
M18
M17
N18
P18
M16
N15
P15
N17
R18
T18
P17
N16
T17
R17
P16
U18
T16
R16
U17
R15
V18
T15
U16
T14
U15
R14
R13
V17
V16
T13
U14
V15
V14
T12
R12
R11
U13
V13
U12
V12
T11
U11
V11
V10
U10
T10
R10
R9
T9
93
94
95
96
97
98*
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143*
144
145
146
147
148
149
150
151
152
Pin Description †
543
546
552
555
558
564
567
570
576
579
588
591
600
603
606
612
615
618
624
627
630
636
639
648
651
660
663
666
672
675
678
684
687
690
696
699
708
711
714
720
723
726
732
735
738
744
747
756
149.
150.
151.
152.
153.
154.
155.
156.
157.
158.
159.
I/O (RS)
I/O
I/O
I/O
I/O
I/O (D2)
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O (D1)
160.
161.
162.
163.
164.
165.
166.
167. I/O (RCLK-
PC84
Boundary
PQ160 PQ208 PG223 PQ240 Scan Order
66
67
68
69
70
103
104
105
106
107
108
109
110
111
112
113
114
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
U9
V9
V8
U8
T8
V7
U7
V6
U6
R8
R7
T7
R6
R5
V5
V4
U5
T6
V3
V2
153
154
155
156
157
158*
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
759
768
771
780
783
786
792
795
798
804
807
810
816
819
822
828
831
834
840
71
72
73
74
75
76
77
78
79
80
81
82
83
84
1
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
149
150
151
152
153
154
155*
156*
157*
158*
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
U4
T5
U3
T4
V1
R4
U2
R3
T3
U1
P3
R2
T2
N3
P4
N4
P2
T1
R1
N2
M3
P1
N1
M4
L4
M2
M1
L3
L2
L1
K1
K2
K3
K4
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195*
196
197
198
199
200
201
202
203
204*
205
206
207
208
209
210
211
843
846
855
858
9
15
18
21
27
30
33
39
42
45
51
54
57
66
69
75
78
81
87
90
93
99
102
105
-
BUSY/RDY)
168.
169.
170.
171.
I/O
I/O
I/O (D0, DIN)
I/O (DOUT)
CCLK
VCC
172. I/O (TDO)
GND
173. I/O (A0, WS)
174. GCK4 (I/O, A1)
175. I/O
176. I/O
177. I/O (CS1, A2)
178. I/O (A3)
179. I/O
180. I/O
181. I/O
182. I/O
183. I/O
184. I/O
GND
185. I/O
186. I/O
187. I/O
188. I/O
VCC
189. I/O (A4)
190. I/O (A5)
191. I/O
192. I/O
193. I/O
194. I/O
195. I/O (A6)
196. I/O (A7)
GND
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 666 = BSCAN.UPD
39
XC5200 Logic Cell Array Family
Preliminary (v1.0)
Physical Dimensions
0.045 x 45°
Pin 1 ID
11
75
1
74
12
1.190
± 0.005
1.154
± 0.004
32
54
33
1.154 ± 0.004
Dimensions in Inches
Lead Pitch 50 Mil
0.175
± 0.010
53
1.190 ± 0.005
Top View
0.045
0.028
0.045
0.004
–C–
0.100
± 0.010
0.017
0.020
1.000 Typ
1.120 ± 0.010
Side View
X3426
84-Pin Plastic PLCC (PC84)
31.20 Sq
0.10
28.00 Sq
120
–C–
81
121
80
0.28 ± 0.05
5°- 7°
160
41
Pin 1 ID
1
40
Top View
Dimensions in Millimeters
Lead Pitch 0.65 mm
Side View
160-Pin Plastic PQFP (PQ160)
40
3.38 ± 0.20
Stand-Off
0.10-0.36
X3434
R
0.100 Typ
S/R 0.890 Sq
V
U
0.070 Dia Typ
(191 Places)
T
R
P
N
M
L
1.860
± 0.019 Sq
K
J
1.700
Typ
H
G
F
E
Stand-Off Pin
(4 Places)
D
C
Top Edge Chamfer
0.010 X 45° Typ
B
A
0.050 X 45°
Pin #1 Side
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Dielectric
Coat
Bottom View
Chamfer
0.030 ± 0.010 X 45°
(3 Places)
0.050
± 0.010
Top View
Gold Plate
Pin #1 Index
Top Side
0.090
± 0.010
0.008
(4 Places)
Dimensions in Inches
0.018 ± 0.002
Au Plated Kovar
0.050 X 0.025
0.130
± 0.010
0.005 R Typ
X3438
Side View
191-Pin Ceramic PGA (PG191)
30.60 Sq
28.00 Sq
156
0.08
–C–
105
104
157
0.13 ± 0.25
12 - 16°
208
53
Pin 1 ID
1
52
0.064 Ref
3.67
3.17
Top View
Dimensions in Millimeters
Lead Pitch 0.50
Side View
208-Pin Plastic PQFP (PQ208)
41
Stand-Off
0.25 Min
X3439
XC5200 Logic Cell Array Family
Preliminary (v1.0)
0.100 Typ
0.070 Dia Typ
(223 Places)
Stand-Off Pin
(4 Places)
0.050 X 45°
Pin #1 Side
S/R 0.899 Max Sq
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1.860
± 0.019 Sq
1.700
Typ
Top Edge Chamfer
0.010 X 45° TYP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Dielectric
Coat
Bottom View
Chamfer
0.030 ± 0.010 X 45°
(3 Places)
0.050
± 0.010
0.008
(4 Places)
Top View
Gold Plate
Pin #1 Index
Top Side
0.090-0.110
Dimensions in Inches
0.018 ± 0.002
Au Plated Kovar
0.050 X 0.025
0.005 R Typ
0.130
± 0.010
Side View
X3441
223-Pin Ceramic PGA (PG223)
Pin 1 ID
240
181
#1Pin
180
34.60
32.00
0.020
Typ
121
60
61
120
Top View
Dimensions in Millimeters
Lead Pitch 0.50 mm
12–16° (2 Halves)
3.50
3.30
Stand-Off
0.25 Min
0.14-0.30
0.10
Side View
–C–
240-Pin Plastic PQFP (PQ240)
42
X3442
R
Ordering Information
XC5210-6PQ208C
Example:
Temperature Range
Number of Pins
Package Type
Device Type
Speed Grade
Component Availability
PINS
84
160
191
208
223
240
TYPE
PLASTIC
PLCC
PLASTIC
PQFP
CERAMIC
PGA
PLASTIC
PQFP
CERAMIC
PGA
PLASTIC
PQFP
CODE
PC84
PQ160
PG191
PQ208
PG223
PQ240
-7
CI
CI
CI
CI
-6
CI
CI
CI
CI
-5
C
C
C
C
-7
CI
CI
CI
CI
CI
-6
CI
CI
CI
CI
CI
-5
CI
CI
CI
CI
CI
XC5206
XC5210
C = Commercial = 0° to +70°C
I = Industrial = -40° to +85°C
Number of Available I/O Pins
Package Type
Device
Max
I/O
PC84
PQ160
PG191
PQ208
XC5206
148
65
133
148
148
XC5210
196
65
133
164
43
PG223
PQ240
196
196
R
The Programmable Logic Company
SM
2100 Logic Drive, San Jose CA 95124-3400
Tel: (408) 559-7778
FAX: (408) 559-7114
0401300
Printed in U.S.A.
P/N 0401300 E2