TOREX XC6109N36ANR

XC6109 Series
ETR0206_005
Voltage Detector with External Delay Type Capacitor
■GENERAL DESCRIPTION
The XC6109 series is highly precise, low power consumption voltage detector, manufactured using CMOS and laser trimming
technologies.
With the built-in delay circuit, connecting the delay capacitance pin to the capacitor enables the IC to provide an arbitrary
release delay time.
Using an ultra small package (SSOT-24), the series is suited for high density mounting.
Both CMOS and N-channel open drain output configurations are available.
■APPLICATIONS
■FEATURES
●Microprocessor reset circuitry
Highly Accurate
: +2%
(Setting Voltage Accuracy>1.5V)
●Charge voltage monitors
: +30mV
●Memory battery back-up switch circuits
●Power failure detection circuits
(Setting Voltage Accuracy<1.5V)
Low Power Consumption
: 0.9μA
(TYP., VDF=1.9V, VIN= 2.0V)
: 0.8V ~ 5.0V
Detect Voltage Range
in 100mV increments
Operating Voltage Range
: 0.7V ~ 6.0V
Detect Voltage Temperature Characteristics
: ±100ppm/ OC (TYP.)
Output Configuration
: CMOS or
N-channel open drain
Operating Temperature Range : -40 OC ~ +85 OC
CMOS
Built-In Delay Circuit, Delay Pin Available
Ultra Small Package
■TYPICAL APPLICATION CIRCUIT
: SSOT-24
■TYPICAL PERFORMANCE
CHARACTERISTICS
●Release Delay Time vs. Delay Capacitance
XC6109xxxA N
(No resistor needed for
CMOS output products)
Release Delay Time: TDR (ms)
VIN(MIN.)=0.7V,VIN(MAX.)=6.0V
10000
Tr=5μs, Ta=25℃
1000
100
10
1
0.1
0.0001
0.001
0.01
0.1
Delay
Capacitance:
Cd
(μF)
Delay Capacitance: Cd (μF)
1
1/14
XC6109 Series
■PIN CONFIGURATION
■PIN ASSIGNMENT
PIN NUMBER
PIN NAME
FUNCTION
1
VIN
Input
2
VSS
Ground
3
Cd
Delay Capacitance
4
VOUT
Output (Detect ”L”)
■PRODUCT CLASSIFICATION
●Ordering Information
XC6109 ①②③④⑤⑥
DESIGNATOR
DESCRIPTION
①
Output Configuration
② ③
Detect Voltage
08 ~ 50
④
Output Delay & Hysteresis
A
: Built-in delay pin & hysteresis 5% (TYP.)
⑤
Package
N
: SSOT-24
⑥
Device Orientation
R
: Embossed tape, standard feed
L
: Embossed tape, reverse feed
2/14
SYMBOL
DESCRIPTION
C
: CMOS output
N
: N-ch open drain output
: e.g. 18→1.8V
XC6109
Series
■BLOCK DIAGRAMS
(1) XC6109C (CMOS Output)
(2) XC6109N (N-ch Open Drain Output)
■ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
Ta = 25OC
RATINGS
UNITS
Input Voltage
VIN
VSS - 0.3 ~ 7.0
V
Output Current
IOUT
10
mA
Output Voltage
XC6109C (*1)
XC6109N (*2)
VOUT
VSS - 0.3 ~ VIN + 0.3
VSS - 0.3 ~ 7.0
V
Delay Pin Voltage
VCD
VSS-0.3 ~ VIN + 0.3
V
Delay Pin Current
ICD
5.0
mA
SSOT-24
Pd
150
mW
Operating Temperature Range
Ta
- 40 ~ + 85
O
C
Storage Temperature Range
Tstg
- 40 ~ + 125
O
C
Power Dissipation
NOTE:
*1: CMOS output
*2: N-ch open drain output
3/14
XC6109 Series
■ELECTRICAL CHARACTERISTICS
Ta = 25OC
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
CIRCUIT
Operating Voltage
Detect Voltage
VIN
VDF
VDF(T)=0.8~5.0V (*1)
VDF(T)=0.8~5.0V
0.7
6.0
V
V
①
Hysteresis Width
VHYS
VIN=1.0~6.0V
V
①
Supply Current 1
ISS1
μA
②
Supply Current 2
ISS2
VDF
x 0.02
-
E-1
VDF
x 0.05
0.80
0.90
1.00
0.90
1.10
1.20
μA
②
0.01
0.36
0.1
0.7
0.8
1.6
mA
③
1.2
2.0
1.6
2.3
mA
④
μA
③
IOUT1
Output Current
IOUT2
CMOS
output
Leak
N-ch Open
Current
Drain
Output
Temperature
Characteristics
Delay Resistance (*7)
Delay Pin Sink Current
Delay Capacitance Pin
Threshold Voltage
(*6)
ILEAK
UVDF
UTa・VDF
Rdelay
ICD
VTCD
Unspecified Operating
Voltage (*8)
VUNS
Detect Delay Time (*9)
TDF0
Release Delay Time
(*10)
TDR0
VDF(T)=0.8~1.9V
VDF(T)=2.0~3.9V
VDF(T)=4.0~5.0V
VDF(T)=0.8~1.9V
VIN=VDF x 1.1
VDF(T)=2.0~3.9V
VDF(T)=4.0~5.0V
VIN=0.7V
VDS=0.5V(Nch)
VIN=1.0V (*2)
VDS=0.5V(Nch)
VIN=2.0V (*3)
VDS=0.5V(Nch)
(*4)
VIN=3.0V
VDS=0.5V(Nch)
(*5)
VIN=4.0V
VDS=0.5V(Nch)
VIN=VDFx1.1
VDS=0.5V (P-ch)
VIN=VDF x 0.9
VDF
x 0.08
1.70
1.90
2.00
1.80
2.00
2.20
-
E-2
-
0.20
-
-
0.20
0.40
-40 OC<Ta<85 OC
-
±100
-
ppm/OC
①
VIN=6.0V, Cd=0V
Cd=0.5V, VIN=0.7V
VIN=1.0V
VIN=6.0V
1.6
8
0.4
2.9
2.0
60
0.5
3.0
2.4
0.6
3.1
MΩ
μA
⑤
⑤
V
⑥
VIN=0~0.7V
-
0.3
0.4
V
⑦
-
30
230
μs
⑧
-
30
200
μs
⑧
VIN=6.0V, VOUT=6.0V, Cd: Open
VIN=6.0 down to 0.7V
Cd: Open
VIN=0.7~6.0V
Cd: Open
NOTE:
*1: VDF(T): Setting Detect Voltage
*2: VDF(T)＞1.0V
*3: VDF(T)＞2.0V
*4: VDF(T)＞3.0V
*5: VDF(T)＞4.0V
*6: This numerical value is applied only to the XC6109C series (CMOS output).
*7: Calculated from the voltage value and the current value of both ends of the resistor.
*8: The maximum voltage of the VOUT in the range of the VIN 0 to 0.7V. This numerical value is applied only to the XC6109C series
(CMOS output).
*9: Time which ranges from the state of VIN =VDF to the VOUT reaching 0.6V when the VIN falls without connecting to the Cd pin.
*10: Time which ranges from the state of VIN= VDF +VHYS to the VOUT reaching 5.4V when the VIN rises without connecting to the Cd pin.
4/14
XC6109
Series
■VOLTAGE CHART
SYMBOL
E-1
E-2
DETECT VOLTAGE (*1)
(V)
OUTPUT CURRENT (*2)
(mA)
PARAMETER
SETTING DETECT
VOLTAGE
VDF(T)
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
MIN.
0.770
0.870
0.970
1.070
1.170
1.270
1.370
1.470
1.568
1.666
1.764
1.862
1.960
2.058
2.156
2.254
2.352
2.450
2.548
2.646
2.744
2.842
2.940
3.038
3.136
3.234
3.332
3.430
3.528
3.626
3.724
3.822
3.920
4.018
4.116
4.214
4.321
4.410
4.508
4.606
4.704
4.802
4.900
VDF
TYP.
0.800
0.900
1.000
1.100
1.200
1.300
1.400
1.500
1.600
1.700
1.800
1.900
2.000
2.100
2.200
2.300
2.400
2.500
2.600
2.700
2.800
2.900
3.000
3.100
3.200
3.300
3.400
3.500
3.600
3.700
3.800
3.900
4.000
4.100
4.200
4.300
4.400
4.500
4.600
4.700
4.800
4.900
5.000
IOUT2
MAX.
0.830
0.930
1.030
1.130
1.230
1.330
1.430
1.530
1.632
1.734
1.836
1.938
2.040
2.142
2.244
2.346
2.448
2.550
2.652
2.754
2.856
2.958
3.060
3.162
3.264
3.366
3.468
3.570
3.672
3.774
3.876
3.978
4.080
4.182
4.284
4.386
4.488
4.590
4.692
4.794
4.896
4.998
5.100
MIN.
TYP.
-0.40
-0.20
-0.60
-0.30
-0.80
-0.40
-1.00
-0.50
-1.20
-0.60
-1.30
-0.65
NOTE:
*1: When VDF(T)≦1.4V, the detection accuracy is ±30mV. When VDF(T)≧1.5V, the detection accuracy is ±2%.
*2: This numerical value is applied only to the XC6109C series (CMOS output).
5/14
XC6109 Series
■TEST CIRCUITS
Circuit 1
Circuit 2
VIN
A
VOUT
(No resistor needed for
CMOS output products)
Cd
VSS
Circuit 3
Circuit 4
VIN
VOUT
A
Cd
VSS
Circuit 5
Circuit 6
(No resistor needed for
CMOS output products)
Circuit 7
Circuit 8
(No resistor needed for
CMOS output products)
Waveform Measurement Point
6/14
XC6109
Series
■OPERATIONAL EXPLANATION
A typical circuit example is shown in Figure 1, and the timing chart of Figure 1 is shown in Figure 2 on the next page.
① As an early state, the input voltage pin is applied sufficiently high voltage to the release voltage and the delay capacitance
(Cd) is charged to the input pin voltage. While the input pin voltage (VIN) starts dropping to reach the detect voltage
(VDF) (VIN > VDF), the output voltage (VOUT) keeps the “High” level (=VIN).
② When the input pin voltage keeps dropping and becomes equal to the detect voltage (VIN = VDF), an N-ch transistor for
the delay capacitance discharge is turned ON, and starts to discharge the delay capacitance. For the internal circuit,
which uses the delay capacitance pin as power input, the reference voltage operates as a comparator of VIN, and the
output voltage changes into the “Low” level (≦VIN×0.1). The detect delay time (TDF) is defined as time which ranges
from VIN =VDF to the VOUT of “Low” level (especially, when the Cd pin is not connected: TDF0).
③ While the input pin voltage keeps below the detect voltage, and 0.7V or more, the delay capacitance is discharged to the
ground voltage (=VSS) level. Then, the output voltage (VOUT) maintains the “Low” level.
④ While the input pin voltage drops to 0.7V or less and it increases again to 0.7V or more, the output voltage may not be
able to maintain the “Low” level. Such an operation is called “Unspecified Operation”, and voltage which occurs at the
output pin voltage is defined as unstable operating voltage (VUNS).
⑤ While the input pin voltage increases more than 0.7V and it reaches to the release voltage level (VIN＜VDF +VHYS), the
output voltage (VOUT) maintains the “Low” level.
⑥ When the input pin voltage continues to increase more than 0.7V up to the release voltage level (= VDF + VHYS), the N-ch
transistor for the delay capacitance discharge will be turned OFF, and the delay capacitance will be started discharging
via a delay resistor (Rdelay). The internal circuit, which uses the delay capacitance pin as power input, will operate as a
hysteresis comparator (Rise Logic Threshold: VTLH=VTCD, Fall Logic Threshold: VTHL=VSS) while the input pin voltage
keeps higher than the detect voltage (VIN > VDF).
⑦ While the input pin voltage becomes equal to the release voltage or higher and keeps the detect voltage or higher, the
delay capacitance (Cd) will be charged up to the input pin voltage. When the delay capacitance pin voltage (VCD)
reaches to the delay capacitance pin threshold voltage (VTCD), the output voltage changes into the “High” (=VIN) level.
TDR is defined as time which ranges from VIN =VDF+VHYS to the VOUT of “High” level (especially when the Cd pin is not
connected: TDR0). TDR can be given by the formula (1).
TDR = −Rdelay×Cd×In (1−VTCD / VIN) +TDR0 …(1)
* In = a natural logarithm
The release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0MΩ(TYP.) and
the delay capacitance pin threshold voltage is VIN /2 (TYP.)
TDR=Rdelay×Cd×0.69 …(2)
* Rdelay is 2.0MΩ(TYP.)
As an example, presuming that the delay capacitance is 0.68μF, TDR is :
2.0×106×0.68×10-6×0.69=938(ms)
* Note that the release delay time may remarkably be short when the delay capacitance is not discharged to the ground
(=VSS) level because time described in ③ is short.
⑧ While the input pin voltage is higher than the detect voltage (VIN > VDF), therefore, the output voltage maintains the
“High”(=VIN) level.
●Release Delay Time Chart
Delay Capacitance [Cd]
(μF)
0.01
0.022
0.047
0.1
0.22
0.47
1
Release Delay Time [TDR] (TYP.)
(ms)
13.8
30.4
64.9
138
304
649
1380
Release Delay Time [TDR] (MIN. ~ MAX.)
(ms)
11.0 ~ 16.6
24.3 ~ 36.4
51.9 ~ 77.8
110 ~ 166
243~ 364
519 ~ 778
1100 ~ 1660
7/14
XC6109 Series
■OPERATIONAL EXPLANATION (Continued)
Figure 1: Typical application circuit example
The circuit which uses the delay
Capacitance pin as power input.
VIN
M2
RSEN=R1+R2+R3
M4
R1
-
VOUT
Rdelay
R2
+
VIN
Vref
M5
R3
M3
M1
Cd
VSS
Delay Capacitor [Cd]
N-ch transictor for the delay
Capacitance discharge.
Cd
Figure 2: The timing chart of Figure 1
Input Voltage: VIN
Release Voltage: VDF+VHYS
Detect Voltage: VDF
Minimum Operating Voltage (0.7V)
Delay Capacitance Pin Voltage: VCD
Delay Capacitance Pin Threshold Voltage: VTCD
Output Pin Voltage: VOUT
①
③
②
8/14
④
⑤
⑦
⑥
⑧
XC6109
Series
■NOTES ON USE
1. Use this IC within the stated maximum ratings. Operation beyond these limits may cause degrading or permanent
damage to the device.
2. The input pin voltage drops by the resistance between power supply and the VIN pin, and by through current at
operation of the IC.
At this time, the operation may be wrong if the input pin voltage falls below the minimum operating
voltage range. In CMOS output, for output current, drops in the input pin voltage similarly occur.
Oscillation of the
circuit may occur if the drops in voltage, which caused by through current at operation of the IC, exceed the hysteresis
voltage. Note it especially when you use the IC with the VIN pin connected to a resistor.
3. Note that a rapid and high fluctuation of the input pin voltage may cause a wrong operation.
4. When there is a possibility of which the input pin voltage falls rapidly (e.g.: 6.0V to 0V) at release operation with the
delay capacitance pin (Cd) connected to a capacitor, use a schottky barrier diode connected between the VIN pin and
5.
the Cd pin as the Figure 3 shown below.
When N-ch open drain output is used, output voltages VOUT at voltage detection and release are determined by a
pull-up resistor tied to the output pin. A resistance value of the pull-up resistor can be selected with referring to the
followings. (Refer to Figure 4)
During detection, the formula is given as
VOUT=Vpull/(1+Rpull/RON)
where Vpull is pull-up voltage and RON (*1) is ON resistance of N-ch driver M5 (RON=VDS/IOUT1 from the electrical
characteristics table).
For example, when VIN=2.0V (*2), RON = 0.5/0.8×10-3=625Ω(MIN.) and if you want to get VOUT less than 0.1V when
Vpull=3.0V, Rpull can be calculated as follows;
Rpull=(Vpull /VOUT-1)×RON=(3/0.1-1)×625≒18ｋΩ
Therefore, pull-up resistance should be selected 18kΩ or higher.
(*1) VIN is smaller, RON is bigger
(*2) For the calculation, the lowest VIN should be used among of the VIN range
During release, the formula is given as
VOUT=Vpull/(1+Rpull/Roff)
where Vpull is pull-up voltage Roff is OFF resistance of N-ch driver M5 (Roff=VOUT/ILEAK=15MΩ from the
electrical characteristics table)
For examples, if you want to get VOUT larger than 5.99V when Vpull is 6.0V, Rpull can be calculated as follows;
6
Rpull=(Vpull/VOUT-1)×Roff=(6/5.99-1)×15×10 ≒25kΩ
Therefore, pull-up resistance should be selected 25kΩ or below.
(No resistor needed
for CMOS output
products)
Note: Roff=VOUT/ILEAK
Figure 3: Circuit example with the delay capacitance pin
(Cd) connected to a schottky barrier diode
Figure 4: Circuit example of XC6109N Series
9/14
XC6109 Series
■TYPICAL PERFORMANCE CHARACTERISTICS
(1) Supply Current vs. Input Voltage
(2) Detect Voltage vs. Ambient Temperature
XC6109x25A N
XC6109x25A N
2.0
2.55
Detect Voltage: VDF (V)
Supply Current: ISS (μA)
Ta=85℃
1.5
25℃
1.0
-40℃
0.5
0.0
2.50
2.45
0
1
2
3
4
5
6
-50
-25
Input V oltage: V IN (V )
0
25
50
75
100
A mbient Temperature: Ta ( ℃ )
(3) Hysteresis Voltage vs. Ambient Temperature
XC6109x25A N
Hysteresis Voltage :
VHYS (V)
0.20
0.15
0.10
0.05
-50
-25
0
25
50
75
100
A mbient Temperature: Ta ( ℃ )
(4) Output Voltage vs. Input Voltage
XC6109C25A N
No Pull-up
4.0
XC6109N25AN
Output Voltage: VOUT (V)
Pull-up=V IN R=100kΩ
4.0
Output Voltage: VOUT (V)
3.0
Ta=85℃
25℃
-40℃
2.0
1.0
0.0
-1.0
0
10/14
0.5
1
1.5
2
Input V oltage: V IN (V )
2.5
3
3.0
Ta=85℃
2.0
25℃
1.0
-40℃
0.0
-1.0
0
0.5
1
1.5
2
2.5
Supply
Voltage:
Input
Voltage:
VINVIN
(V) (V)
3
XC6109
Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(5) Output Current vs. Input Voltage
XC6109C08A N
XC6109x50A N
VDS(N-ch)=0.5V
Ta=-40℃
3.0
25℃
2.0
85℃
1.0
VDS(P-ch)=0.5V
0.0
Output Current: IOUT (mA)
Output Current: IOUT (mA)
4.0
Ta=85℃
-0.5
-1.0
25℃
-1.5
-2.0
0.0
0
1
2
3
4
5
0
6
1
Input Voltage: V IN (V )
(6) Cd Pin Sink Current vs. Input Voltage
Delay Resistance: Rdelay
(MΩ )
Cd Pin Sink Current: ICD (mA)
4
Ta=-40℃
25℃
1.5
1.0
85℃
0.5
0.0
3.5
3
2.5
2
1.5
1
-50
0
1
2
3
4
Input V oltage: V IN (V )
5
6
(8) Release Delay Time vs. Delay Capacitance
-25
25
50
75
100
(9) Detect Delay Time vs. Delay Capacitance
XC6109xxxA N
VIN(MIN.)=0.7V,VIN(MAX.)=6.0V
VIN(MIN.)=0.7V, VIN(MAX.)=6.0V
100
10
1
0.001
0.01
0.1
Delay Capacitance: Cd (μF)
1
Tf=5μs, Ta=25℃
100000
Detect Delay Time: TDF (μs)
Tr=5μs, Ta=25℃
1000
0.1
0.0001
0
Ambient Temperature: Ta (℃ )
XC6109xxxA N
10000
6
V CD=0.0V VIN=6.0V
VDS=0.5V
2.0
5
XC6109xxxAN
3.0
2.5
2
3
4
Input V oltage: V IN (V )
(7) Delay Resistance vs. Ambient Temperature
XC6109x50A N
Release Delay Time: TDR (ms)
-40℃
10000
1000
100
10
1
0.0001
0.001
0.01
0.1
1
Delay Capacitance: Cd (μF)
11/14
XC6109 Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(10) Leak Current vs. Ambient Temperature
(11) Leak Current vs. Supply Voltage
XC6109N25AN
XC6109N25AN
V IN=6.0V
Leak Carrent: ILEAK ( μ A)
Leak Carrent: ILEAK ( μ A)
V IN=6.0V V OUT=6.0V
0.25
0.20
0.15
0.10
-50
-25
0
25
50
75
Ambient Temperature: Ta (℃ )
12/14
100
0.25
0.20
0.15
0.10
0
1
2
3
4
5
Supply Voltage: VOUT (V)
6
XC6109
Series
■PACKAGING INFORMATION
●SSOT-24
■MARKING RULE
●SSOT-24
4
①
1
3
②
④
2
SSOT-24
(TOP VIEW)
① Represents output configuration and integer number of detect voltage
CMOS output (XC6109C Series)
N-ch Open Drain output (XC6109N Series)
MARK VOLTAGE (V)
A
0.x
B
1.x
C
2.x
D
3.x
E
4.x
F
5.x
PRODUCT SERIES
XC6109C0xxNx
XC6109C1xxNx
XC6109C2xxNx
XC6109C3xxNx
XC6109C4xxNx
XC6109C5xxNx
MARK VOLTAGE (V)
K
0.x
L
1.x
M
2.x
N
3.x
P
4.x
R
5.x
PRODUCT SERIES
XC6109N0xxNx
XC6109N1xxNx
XC6109N2xxNx
XC6109N3xxNx
XC6109N4xxNx
XC6109N5xxNx
②Represents decimal number of detect voltage
MARK
N
P
R
S
T
U
V
X
Y
Z
VOLTAGE (V)
x.0
x.1
x.2
x.3
x.4
x.5
x.6
x.7
x.8
x.9
PRODUCT SERIES
XC6109xx0xNx
XC6109xx1xNx
XC6109xx2xNx
XC6109xx3xNx
XC6109xx4xNx
XC6109xx5xNx
XC6109xx6xNx
XC6109xx7xNx
XC6109xx8xNx
XC6109xx9xNx
④Represents production lot number
0 to 9, A to Z or inverted characters of 0 to 9, A to Z repeated/
(G, I, J, O, Q, W excepted)
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XC6109 Series
1. The products and product specifications contained herein are subject to change without
notice to improve performance characteristics.
Consult us, or our representatives
before use, to confirm that the information in this datasheet is up to date.
2. We assume no responsibility for any infringement of patents, patent rights, or other
rights arising from the use of any information and circuitry in this datasheet.
3. Please ensure suitable shipping controls (including fail-safe designs and aging
protection) are in force for equipment employing products listed in this datasheet.
4. The products in this datasheet are not developed, designed, or approved for use with
such equipment whose failure of malfunction can be reasonably expected to directly
endanger the life of, or cause significant injury to, the user.
(e.g. Atomic energy; aerospace; transport; combustion and associated safety
equipment thereof.)
5. Please use the products listed in this datasheet within the specified ranges.
Should you wish to use the products under conditions exceeding the specifications,
please consult us or our representatives.
6. We assume no responsibility for damage or loss due to abnormal use.
7. All rights reserved. No part of this datasheet may be copied or reproduced without the
prior permission of TOREX SEMICONDUCTOR LTD.
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