XRD66092 ...the analog plus company TM CMOS 750 KSPS, 12-Bit Analog-to-Digital Converter with Serial Logic Interface Port April 1996-1 FEATURES • • • • • • • • • • • • • • • 12-Bit Monotonic ADC with DNL = +1 LSB, INL = +2.5 LSB SNR > 66 dB Sampling Frequency < 750 kHz Internal Track and Hold Single 5 V Supply Rail-to-Rail Input Range VREF Range: 1.5 V to VDD CMOS Low Power: 175 mW (typ) Binary and Two’s Complement Digital Output Mode Serial Port ESD: 2000 V Minimum Underflow and Overflow Outputs Precision Aperture Output 6 Reference Resistor Taps Latch-Up Free APPLICATIONS • • • • • Control Systems Instrumentation DAS Sonar Digital Radio Separate pins for VRT and VRB allow flexibility for analog input (VIN) and the reference voltage range (VREF). GENERAL DESCRIPTION The XRD66092 is a 12-bit 750 kHz subranging Analog-to-Digital Converter with an internal track and hold. Data is presented at the serial output port every clock cycle with a 2.5 cycle pipeline delay. LINV and MINV enable binary and 2’s complement data formatting. 6 ladder tap pins provide for transfer function adjustment. The XRD66092 operates with a single supply ranging from +3 V to +5 V while consuming less than 175 mW of power (typical). SIMPLIFIED BLOCK DIAGRAM GND VDD (3 Pads) (3 Pads) VDD GND LINV MINV VRT REF Ladder Over LSB Comparators R5 R4 S/H Latch R9 R8 R7 OFW D11 Encoder and Error Correction Logic D10-D0 Under Output Register MSB Comparators Latch R12 UFW Clock Logic PLOAD SCLK SDO VRB VIN Aperture CLK Rev. 1.00 1996 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017 XRD66092 ORDERING INFORMATION Temperature Range PDIP –40 to +85°C XRD66092AIP 2 1/2 –40 to +85°C 1 SOIC XRD66092AID 1 2 1/2 PIN CONFIGURATIONS R5 GND VIN VDD R8 R12 R4 VRB VRT VDD VDD GND GND MINV DNL (LSB) Package Type Part No. INL (LSB) See Packaging Section for Package Dimensions 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 R5 GND VIN VDD R8 R12 R4 VRB VRT VDD VDD GND GND MINV R9 R7 N/C PLOAD CLK OFW Aperture SCLK GND VDD SDO N/C UFW LINV 28 Pin PDIP (0.600”) 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 R9 R7 N/C PLOAD CLK OFW Aperture SCLK GND VDD SDO N/C UFW LINV 28 Pin SOIC (Jedec, 0.300) PIN OUT DEFINITIONS PIN NO. NAME DESCRIPTION PIN NO. NAME DESCRIPTION 1 R5 Ref. Resistor Ladder Tap (5/16 VREF) 15 LINV Invert LSB (Active High) 2 GND Analog Ground (Substrate) 16 UFW Underflow Bit 3 VIN Analog Input 17 N/C No Connection 4 VDD Analog Positive Supply 18 SDO Serial Data Out 5 R8 Ref. Resistor Ladder Tap (1/2 VREF) 19 VDD Digital Positive Supply 6 R12 Ref. Resistor Ladder Tap (3/4 VREF) 20 GND Digital Ground (Substrate) 7 R4 Ref. Resistor Ladder Tap (1/4 VREF) 21 SCLK Serial Clock 8 VRB Negative Reference 22 Aperture Aperture Delay Sync 9 VRT Positive Reference 23 OFW Overflow Bit 10 VDD Analog Positive Supply 24 CLK Clock 11 VDD Analog Positive Supply 25 PLOAD Serial Shift Register Data Load 12 GND Analog Ground (Substrate) 26 N/C No Connection 13 GND Analog Ground (Substrate) 27 R7 Ref. Resistor Ladder Tap (7/16 VREF) 14 MINV Invert MSB (Active High) 28 R9 Ref. Resistor Ladder Tap (9/16 VREF) Rev. 1.00 2 XRD66092 ELECTRICAL CHARACTERISTICS TABLE Unless Otherwise Specified: VDD = 5 V, FS = 750 kHz (50% Duty Cycle), VREF(+) = 5.0 V, VREF(–) = GND, TA = 25°C, VIN Connected through 39Ω Parameter Symbol Min 25°C Typ Max Units 750 Bits kHz +1 +2.5 LSB LSB Test Conditions/Comments KEY FEATURES Resolution Sampling Rate 12 FS ACCURACY1 Differential Non-Linearity Integral Non-Linearity (See NO TAG) Zero Scale Error Full Scale Error DNL INL +1/2 +2 EZS EFS +10 –10 Best Fit Line (Max INL – Min INL)/2 LSB LSB REFERENCE VOLTAGES Positive Ref. Voltage Negative Ref. Voltage Differential Ref. Voltage3 Ladder Resistance VRT VRB VREF 1.5 GND 1.5 RL VDD VDD V V V Ω 550 4.5 to 5 V is recommended for specified performance, VREF(+) – VREF(–) ANALOG INPUT Input Bandwidth (–3 dB)4 Input Voltage Range Input Capacitance Sample5 Input Capacitance Convert5 Aperture Delay from Clock BW VIN CIN 10 50 8 20 MHz V p-p pF pF ns 2.4 0.8 V V VREF(–) tAP VREF(+) DIGITAL INPUTS Logical “1” Voltage Logical “0” Voltage Leakage Currents 6 CLK, MINV, LINV, SCLK, PLOAD Input Capacitance Clock Timing Clock Period Rise & Fall Time7 “High” Time “Low” Time Duty Cycle Serial Register Timing Shift Clock Period Shift Clock to Data Delay Minimum Pulse Width PLOAD Clock↑ to PLOAD↓ For Valid D11 VIH VIL IIN VIN=GND to VDD 10 5 50 µs ns ns ns % 20 50 0 ns ns ns ns 1.33 tR, tF tPWH tPWL tSC tSD tS tCP µA pF 15 665 665 110 COUT=15 pF DIGITAL OUTPUTS Logical “1” Voltage Logical “1” Source Current Logical “0” Voltage Logical “0” Sink Current Tristate Leakage Data Valid Delay 1/FS VOH IOH VOL IOL IOZ tDL VDD-0.5 4 0.5 4 1 30 Rev. 1.00 3 V mA V mA µA ns ILOAD = 4 mA VOH = VDD-0.5 ILOAD = 4 mA VOL = 0.5 V VOUT=GND to VDD XRD66092 ELECTRICAL CHARACTERISTICS TABLE (CONT’D) Parameter Symbol Min 25°C Typ Max Units Test Conditions/Comments POWER SUPPLIES8 Operating Voltage (VDD) Current (VDD) VDD IDD 5 35 45 V mA AC PARAMETERS Signal Noise Ratio SNR 66 dB VIN = 5 Vp-p, 1 kHz NOTES 1 Tester measures code transitions by dithering the voltage of the analog input (VIN). The difference between the measured and the ideal code width (VREF/4096) is the DNL error. The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage. Accuracy is a function of the sampling rate (FS). 2 Guaranteed. Not tested. 3 Specified values guarantee functionality. Refer to other parameters for accuracy. 4 –3 dB bandwidth is a measure of performance of the A/D input stage (S/H amplifier). Refer to other parameters for accuracy within the specified bandwidth. 5 A 39Ω resistor should be put in series with VIN to dampen transients associated with inductive output impedance of typical op amps. 6 All inputs have diodes to VDD and GND. Input(s) MINV and LINV have internal pull down(s). Input DC currents will not exceed specified limits for any input voltage between GND and VDD. 7 Condition to meet aperture delay specifications (tAP, tAJ). Actual rise/fall time can be less stringent with no loss of accuracy. 8 GND pins are internally connected through the silicon substrate. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3 VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Storage Temperature . . . . . . . . . . . . . . –65 to +150°C VRT & VRB . . . . . . . . . . . . . . . VDD +0.5 to GND –0.5 V Lead Temperature (Soldering 10 seconds) . . +300°C All Inputs . . . . . . . . . . . . . . . . VDD +0.5 to GND –0.5 V Package Power Dissipation Rating @ 75°C PDIP. SOIC . . . . . . . . . . . . . . . . . . . . . . . . . 1000mW Derates above 75°C . . . . . . . . . . . . . . . . . 14mW/°C Digital Outputs . . . . . . . . . . . VDD +0.5 to GND –0.5 V NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. 3 GND refers to AGND and DGND. Rev. 1.00 4 XRD66092 1/FS tPWL tPWH N+1 CLK N+2 Pipeline Delay tAP DATA N+1 N Analog Input VIN N+2 N+3 Sampling Points N–3 tDL N–2 N–1 N N+1 Figure 1. XRD66092 Timing Diagram DNL Output Codes LSB Best Fit Line 7 V(N+1) Real Transfer Line Analog Input 6 V(N) 5 EFS INL N+1 Output Codes 4 N Ideal Transfer Line 3 N–1 Code Width (N) = V(N+1) – V(N) LSB = [ VRT – VRB ] / 4096 2 LSB 1 DNL(N) = [ V(N+1) – V(N) ] – LSB Analog Input (Volt) EZS Figure 2. DNL Measurement Figure 3. INL Error Calculation (which appears just after the PLOAD strobe). Each bit is output on the rising edge of SCLK. UFW: Underflow (Output) This signal indicates when the Analog Input (VIN) goes below the VRB range, and is normally at a low logic level. When VIN < VRB, UFW will go high and the data bits will show negative full scale (i.e. all 0’s if MINV & LINV are low). SCLK: Serial Data Port Clock The SCLK controls the output of the serial port through SDO. SDO is updated on every rising edge of SCLK. The PLOAD signal will override the SCLK signal. OFW: Underflow (Output) This signal indicates when the Analog Input (VIN) goes above the VRB range, and is normally at a low logic level. When VIN > VRB, OFW will go high and the data bits will show positive full scale (i.e. all 0’s if MINV & LINV are low). PLOAD: Serial data port shift register load: When PLOAD is low (i.e. level triggered not edge triggered) the current parallel data will be loaded into the shift register. PLOAD overrides SCLK. When PLOAD is high, the data can be shifted out through the SDO pin with SCLK. SDO: Serial Data output After the internal shift register is updated using the PLOAD signal, the SDO pin outputs the A/D result starting with the MSB Rev. 1.00 5 XRD66092 Sampling DATA N Time = N Time = N N-3 DATA VALID CLK CLK N-3 DATA VALID tCP PLOAD PLOAD tS tSC SCLK tSD tSD D11 SDO D10 D1 D0 SDO Trailing Zeroes Sample N –3 Data Note: Avoid SCLK and CLK Clock Edges Being Coincident DB11 DB11 available on falling edge of PLOAD Figure 4. Serial Port Timing Chart der). The value of VIN at the high to low transition of APERTURE is the value that will be digitized. A system can monitor this signal and adjust the CLK phase to accurately synchronize the sampling point to an external event. APERTURE: Aperture Delay Sync (output) This signal is high when the internal sample/hold function is sampling VIN, and goes low when it is in the hold mode (when the ADC is comparing the stored input value to the reference ladMINV LINV VRT VIN mid scale VRB 0 0 0 1 1 0 1 1 111 . . . 11 111 . . . 10 100 . . . 00 100 . . . 01 011 . . . 11 011 . . . 10 000 . . . 00 000 . . . 01 100 . . . 01 100 . . . 00 111 . . . 10 111 . . . 11 000 . . . 01 000 . . . 00 011 . . . 10 011 . . . 11 011 . . . 11 000 . . . 00 111 . . . 11 100 . . . 00 000 . . . 01 000 . . . 00 011 . . . 10 011 . . . 11 100 . . . 01 100 . . . 00 111 . . . 10 111 . . . 11 binary inverted 2’s complement 2’s complement inverted binary Table 1. Output Data Format Truth Table MINV & LINV: Digital Output Format (inputs) be inverted. The OFW and UFW bits are not affected by these signals. These signals control the format of the digital output data bits DB0 – DB11. Normally both pins are held low so the data is in straight binary format (all 0’s when VIN=VRB; all 1’s when VIN=VRT). If MINV is pulled high then the MSB (DB11) will be inverted. If LINV is pulled high then the LSBs (DB0 – DB10) will MINV & LINV are meant to be static digital signals. If they are to change during operation they should only change when the CLK is low. Changing MINV and/or LINV when CLK is high is acceptable, but the effects on the digital outputs will not be seen until the output latch of the output register is enabled. MINV and Rev. 1.00 6 XRD66092 LINV have internal pull down devices. Please see the simplified logic circuit Figure 5. plications above 85°C. Up to 1.6 V is allowed for applications under 85°C. APPLICATION NOTES MINV or LINV 1MΩ VIN signals should not exceed VDD +0.5V or go below GND –0.5V. All pins have internal protection diodes that will protect them from short transients (<100µs) outside the supply range. SDO D D Q Q latch latch EN EN All GND pins are connected internally through the P– substrate. DC voltage differences between any GND pins will cause undesirable internal substrate currents. CLK The power supply (VDD) and reference voltage (VRT & VRB) pins should be decoupled with 0.1µF and 10µF capacitors to GND, placed as close to the chip as possible. Figure 5. MINV, LINV Simplified Logic Circuit The digital outputs should not drive long wires or buses. The capacitive coupling and reflections will contribute noise to the conversion. VIN Analog Input The reference tap pins can be used to create piecewise-linear transfer functions. By forcing voltages on these pins, a 7 segment transfer function can be made. See Figure 7. The XRD66L92 has a switched capacitor track and hold input stage. VIN is sampled at the high to low clock transition. The Figure 6. shows the equivalent input circuit. VDD 50Ω CL V7 41pF 50Ω DAC7 VIN 8pF VRT + VRB + − 2 GND V8 DAC8 CL 1.5pF V6 DAC6 CL V5 DAC5 CL at PHASE = 1 V4 DAC4 Figure 6. Equivalent Input Circuit VRT R12 R9 R8 R7 XRD66092 V3 R5 DAC3 V2 DAC2 R1 V1 Reference Ladder Taps VRB DAC1 These taps connect to every sixteenth point along the reference ladder; R4 is 4/16th up from VRB, R7 is 7/16ths up from VRB. These taps can be used to alter the transfer curve of the ADC. The internal interconnect resistance from the pin to the ladder is less than 3Ω for the even numbered taps, (i.e. R4,R6, etc.) and is approximately 10Ω for the odd numbered taps. DAC MP7228 Only the Ladder detail shown. Altering the transfer curve may be desirable to enhance or reduce the probability of codes for certain ranges of VIN. This is often referred to as probability density function shaping, or histogram shaping. 0.8 V maximum per tap is recommended for ap- Figure 7. A/D with Programmed Ladder Control for Creating a Piecewise Linear Transfer Function Rev. 1.00 7 XRD66092 PERFORMANCE CHARACTERISTICS Graph 1. DNL vs. FS Graph 2. INL vs. FS Graph 3. IDD vs. FS Graph 4. DNL Error Plot Graph 5. INL Error Plot Rev. 1.00 8 XRD66092 28 LEAD PLASTIC DUAL-IN-LINE (600 MIL PDIP) 28 15 E1 1 14 E D Seating Plane A2 A L A1 α C B B1 e MILLIMETERS INCHES SYMBOL eA eB MIN MAX MIN A 0.160 0.250 4.06 6.35 A1 0.015 0.070 0.38 1.78 A2 0.125 0.195 3.18 4.95 B 0.014 0.024 0.36 0.56 B1 0.030 0.070 0.76 1.78 C 0.008 0.014 0.20 0.38 D 1.380 1.565 35.05 39.75 E 0.600 0.625 15.24 15.88 E1 0.485 0.580 12.32 14.73 e eA 0.100 BSC 0.600 BSC MAX 2.54 BSC 15.24 BSC eB 0.600 0.700 15.24 17.78 L 0.115 0.200 2.92 5.08 α 0° 15° 0° Note: The control dimension is the inch column 15° Rev. 1.00 9 XRD66092 28 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) D 28 15 E H 1 14 C A Seating Plane α B e A1 L INCHES SYMBOL MILLIMETERS MIN MAX MIN A 0.093 0.104 2.35 2.65 A1 0.004 0.012 0.10 0.30 B 0.013 0.020 0.33 0.51 C 0.009 0.013 0.23 0.32 D 0.697 0.713 17.70 18.10 E 0.291 0.299 7.40 7.60 e 0.050 BSC MAX 1.27 BSC H 0.394 0.419 10.00 10.65 L 0.016 0.050 0.40 1.27 α 0° 8° 0° 8° Note: The control dimension is the millimeter column Rev. 1.00 10 XRD66092 Notes Rev. 1.00 11 XRD66092 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1996 EXAR Corporation Datasheet April 1996 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 1.00 12