TM This X76F400 device has been acquired by IC MICROSYSTEMS from Xicor, Inc. 4K ICmic IC MICROSYSTEMS 512 x 8 bit X76F400 Secure SerialFlash FEATURES DESCRIPTION •64-bit password security •One array (496 bytes) two passwords (16 bytes) —Read password —Write password •Programmable passwords •Retry counter register —Allows 8 tries before clearing of the array •32-bit response to reset (RST input) •8 byte sector write mode •1MHz clock rate •2-wire serial interface •Low power CMOS —2.5 to 5.5V operation —Standby current less than 1µA —Active current less than 3 mA •High reliability endurance: —100,000 write cycles •Data retention: 100 years •Available in: The X76F400 is a password access security supervisor, containing one 3968-bit Secure Serial Flash array. Access to the memory array can be controlled by two 64-bit passwords. These passwords protect read and write operations of the memory array. The X76F400 features a serial interface and software protocol allowing operation on a popular 2-wire bus. The bus signals are a clock input (SCL) and a bi-directional data input and output (SDA). The X76F400 also features a synchronous response to reset, providing an automatic output of a hard-wired 32-bit data stream, thereby meeting the industry standard for memory cards. The X76F400 utilizes Xicor’s proprietary Direct Write ™ cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. —8-lead, SOIC,TSSOP BLOCK DIAGRAM Retry Counter Data Transfer SCL SDA Erase Logic Array Access Enable Interface Logic 496 Byte EEPROM Array Password Array and Password Verification Logic RST ISO Reset Response Register REV 1.0 7/5/00 www.icmic.com Characteristics subject to change without notice. 1 of 14 X76F400 PIN DESCRIPTIONS If the X76F400 is in a nonvolatile write cycle a “no ACK” (SDA = High) response will be issued in Serial Clock (SCL) response to loading of the command byte. If a stop is issued prior to the nonvolatile write cycle, the write The SCL input is used to clock all data into and out of the device. Serial Data (SDA) operation will be terminated; the part will then reset and enter into a standby mode. (The basic sequence is illustrated in Figure 1.) SDA is an open drain serial data input/output pin. During a read cycle, data is shifted out on this pin. During a write cycle, data is shifted in on this pin. In all other cases, this pin is in a high impedance state. PIN NAMES Symbol Description SDA Serial Data Input/Output Reset (RST) SCL Serial Clock Input RST is a device reset pin. When RST is pulsed high, the X76F400 will output 32 bits of fixed data, which RST Reset Input VCC Supply Voltage VSS Ground NC No Connect conforms to the standard for “synchronous responseto-reset.” The part must not be in a write cycle for the response-to-reset to occur. See Figure 7. If power is interrupted during the response-to-reset, the response- to-reset will be aborted and the part will return to the standby state. The response to reset is “mask PIN CONFIGURATION programmable” only! SOIC DEVICE OPERATION The X76F400 memory array consists of 62 8-byte sectors. Read or write access to the array always begins at the first address of the sector. Read operations then can continue indefinitely. Write operations must total 8 bytes. There are two primary modes of operation for the X76F400; Protected READ and protected WRITE. Pro- VSS 1 8 VCC NC 2 7 RST SDA 3 6 SCL NC 4 5 NC RST TSSOP tected operations must be performed with one of two 8- byte passwords. The basic method of communication for the device is generating a start condition, then transmitting a com- VCC 1 8 NC 2 7 SCL NC 3 6 SDA VSS 4 5 NC mand, followed by the correct password. All parts will be shipped from the factory with all passwords equal to ‘0.’ The user must perform ACK polling to determine the validity of the password, prior to starting a data transfer After each transaction is completed, the X76F400 will reset and enter into a standby mode. This will also be (see Acknowledge Polling). Only after the correct password is accepted, and an ACK polling has been the response if an unsuccessful attempt is made to access a protected array. performed, can the data transfer occur. See Figure 1. To ensure the correct communication, RST must remain LOW under all conditions except when running a “response-to-reset sequence”. Data is transferred in 8-bit segments, with each transfer being followed by an ACK, generated by the receiving device. REV 1.0 7/5/00 www.icmic.com Characteristics subject to change without notice. 2 of 14 X76F400 Figure 1. X76F400 Device Operation Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA changes during SCL HIGH are Load Command/Address Byte reserved for indicating start and stop conditions. Refer to Figures 2 and 3. Load 8-Byte Password Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is Verify Password HIGH. The X76F400 continuously monitors the SDA and SCL lines for the start condition, and will not Acceptance by Use of ACK Polling respond to any command until this condition is met. A start may be issued to terminate the input of a control byte or the input data to be written. This will reset Read/Write Data Bytes the device and leave it ready to begin a new read or write command. Because of the push/pull output, a start cannot be generated while the part is outputting data. Starts are inhibited while a write is in progress. Retry Counter The X76F400 contains a retry counter. The retry counter allows 8 accesses with an invalid password before any action is taken. The counter will increment with any combination of incorrect passwords. If the retry counter overflows, the memory area and both of the passwords are cleared to “0.” If a correct password is received prior to retry counter overflow, the retry counter is reset and access is granted. Stop Condition All communications must be terminated by a stop condition. The stop condition is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to reset the device during a command or data input sequence, leaving the device in the standby power mode. As with starts, stops are inhibited when outputting data and while a write is in progress. Device Protocol The X76F400 supports a bi-directional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as a receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X76F400 will be considered a slave in all applications. Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting 8 bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the 8 bits of data. The X76F400 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write condition have been selected, the X76F400 will respond with an acknowl- edge after the receipt of each subsequent 8-bit word. Figure 2. Data Validity SCL SDA Data Stable REV 1.0 7/5/00 Data Change www.icmic.com Characteristics subject to change without notice. 3 of 14 X76F400 Figure 3. Definition of Start and Stop Conditions SCL SDA START Condition STOP Condition Table 1. X76F400 Instruction Set Command After Start Command Description Password Used 1 S5 S4 S3 S2 S1 S00 Sector Write Write 1 S5 S4 S3 S2 S1 S0 1 Sector Read Read 11111100 Change Write Password Write 11111110 Change Read Password Write 01010101 Password ACK Command None then return to the standby mode. All write/read operations require a password. with the nonvolatile write operation, it will issue a “noACK” in response. If the nonvolatile write operation is completed, an “ACK” will be returned and the host can then proceed with the rest of the protocol. PROGRAM OPERATIONS Data ACK Polling Sequence Illegal command codes will be disregarded. The part will respond with a “no-ACK” to the illegal byte and Sector Write The sector write mode requires issuing the 8-bit write command followed by the password and then the data bytes transferred as illustrated in Figure 4. The write command byte contains the address of the sector to be written. Data is written starting at the first address of a sector and 8 bytes must be transferred. After the last byte to be transferred is acknowledged, a stop condition is issued which starts the nonvolatile write cycle. If more or less than 8 bytes are transferred, the data in the sector remains unchanged. ACK Polling Once a stop condition is issued to indicate the end of the host’s write sequence, the X76F400 initiates the internal nonvolatile write cycle. In order to take advantage of the typical 5ms write cycle, ACK polling can begin immediately. This involves issuing the start condition followed by the new command code of 8 bits Write Sequence Completed Enter ACK Polling Issue START Issue New Command Code ACK Returned? NO YES PROCEED (first byte of the protocol). If the X76F400 is still busy REV 1.0 7/5/00 www.icmic.com Characteristics subject to change without notice. 4 of 14 X76F400 After the password sequence, there is always a nonvola- tile write cycle. This is done to discourage random guesses of the password if the device is being tampered with. In order to continue the transaction, the X76F400 READ OPERATIONS Read operations are initiated in the same manner as write operations but with a different command code. requires the master to perform a password ACK polling sequence with the specific command code of 55h. As Sector Read with regular acknowledge polling the user can either time out for 10ms and then issue the ACK polling once, With sector read, a sector address is supplied with the read command. Once the password has been or continuously loop as described in the flow. acknowledged data may be read from the sector. An acknowledge must follow each 8-bit data transfer. A If the password inserted is correct, the nonvolatile cycle in response to the password ACK polling read operation always begins at the first byte in the sector, but may stop at any time. Random accesses to sequence is over, and an “ACK” is returned. If the password inserted is incorrect, a “no ACK” is returned, even if the nonvolatile cycle is over. Therefore, the user cannot be certain that the password is incorrect until the 10ms write cycle time has elapsed. the array are not possible. Continuous reading from the array will return data from successive sectors. After reading the last sector in the array, the address is automatically set to the first sector in the array and data can continue to be read out. After the last bit has been read, a stop condition is generated without sending a preceding acknowledge. Password ACK Polling Sequence Password Load Completed Enter ACK Polling Issue START Issue Password ACK Command ACK Returned? NO YES PROCEED REV 1.0 7/5/00 www.icmic.com Characteristics subject to change without notice. 5 of 14 X76F400 START Figure 4. Sector Write Sequence (Password Required) Host Commands Write Password Write Command Write Password 7 0 Wait tWC OR Password ACK Command ACK ACK ACK ACK SDA S X76F400 Response STOP Password ACK Command ACK Host Commands ACK START If ACK, then Password Matches P Wait tWC Data ACK Polling ACK ACK X76F400 Response ACK No-ACK ACK S Figure 5. Acknowledge Polling SCL 8th CLK of 8th Pwd. Byte SDA ‘ACK’ CLK 8th CLK ‘ACK’ 8th Bit ‘ACK’ CLK ACK or No ACK START Condition START Figure 6. Sector Read Sequence (Password Required) Host Commands Read Password 7 0 Wait tWC OR Password ACK Command ACK ACK ACK SDA S ACK X76F400 Response Read Password Read Command STOP Password ACK Command ACK Host Commands ACK START If ACK, then Password Matches P REV 1.0 7/5/00 ACK X76F400 Response No-ACK S Data 0 www.icmic.com Data n Characteristics subject to change without notice. 6 of 14 X76F400 PASSWORDS Passwords are changed by sending the “change read password” or “change write password” commands in a normal sector write operation. A full 8 bytes containing the new password must be sent, following successful transmission of the current write password and a valid password ACK response. The user can use a repeated ACK polling command to check that a new password been written correctly. An ACK indicates that the has new password is valid. After initiating a nonvolatile write cycle, the RST pin must not be pulsed until the nonvolatile write cycle is complete. If not, the ISO response will not be activated. If the RST is pulsed HIGH and the CLK is within the RST pulse (meet the t NOL spec.) in the middle of an ISO transaction, it will output the 32 bit sequence again (starting at bit 0). Otherwise, this aborts the ISO operation and the part returns to standby state. If the RST is pulsed HIGH and the CLK is outside the RST pulse (in the middle of an ISO transaction), this aborts the ISO operation and the part returns to standby There is no way to read any of the passwords. state. RESPONSE-TO-RESET (DEFAULT = 19 40 AA 55) If power is interrupted during the response-to-reset, the response-to-reset will be aborted and the part will The ISO Response-to-reset is controlled by the RST and CLK pins. When RST is pulsed high during a clock return to the standby state. A response-to-reset is not available during a nonvolatile write cycle. pulse, the device will output 32 bits of data, one bit per clock, and it resets to the standby state. This conforms to the ISO standard for “synchronous response to reset.” The part must not be in a write cycle for the response-to-reset to occur. Figure 7. Response to RESET (RST) RST SCK SO 10 0 11 LSB Byte REV 1.0 7/5/00 0 00 0 1 0 0 0000 MSB LSB 0 0 1 0 1 0 1 0 1 www.icmic.com MSB MSB LSB MSB LSB 1 1 0 1 0 1 0 1 0 2 3 Characteristics subject to change without notice. 7 of 14 X76F400 ABSOLUTE MAXIMUM RATINGS COMMENT Temperature under bias .................... –65°C to +135°C Storage temperature ........................ –65°C to +150°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Voltage on any pin with respect to V SS ......................................... –1V to +7V This is a stress rating only; functional operation of the device (at these or any other conditions above those D.C. output current............................................... 5mA Lead temperature (soldering, 10 seconds).........300°C listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Supply Voltage Limits Commercial 0°C +70°C X76F400 4.5V to 5.5V Industrial –40°C +85°C X76F400 – 2.5 2.5V to 5.5V D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol Parameter ICC1 Min. VCC Supply current Max. Unit Test Conditions 1 mA fSCL = VCC x 0.1/VCC x 0.9 Levels @ 400 kHz, (Read) ICC2(3) SDA = Open RST = V SS VCC Supply current 3 mA fSCL = VCC x 0.1/VCC x 0.9 Levels @ 400 kHz, (Write) ISB1(1) SDA = Open RST = V SS VCC Supply current 1 µA V IL = VCC x 0.1, VIH = VCC x 0.9 fSCL = 400 kHz, fSDA = 400 kHz 1 µA V SDA = VSCC = VCC Other = GND or VCC–0.3V (Standby) ISB2(1) VCC Supply current (Standby) ILI Input leakage current 10 µA VIN = VSS to VCC ILO Output leakage current 10 µA VOUT = VSS to VCC VIL(2) Input LOW voltage –0.5 VCC x 0.1 V VIH Input HIGH voltage VCC x 0.9 VCC + 0.5 V 0.4 V (2) VOL Output LOW voltage IOL = 3mA CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol COUT CIN (3) (3) Test Max. Unit Conditions Output capacitance (SDA) 8 pF VI/O = 0V Input capacitance (RST, SCL) 6 pF VIN = 0V Notes: (1)Must perform a stop command after a read command prior to measurement (2)V IL min. and VIH max. are for reference only and are not tested (3)This parameter is periodically sampled and not 100% test REV 1.0 7/5/00 www.icmic.com Characteristics subject to change without notice. 8 of 14 X76F400 EQUIVALENT A.C. LOAD CIRCUIT 5V A.C. TEST CONDITIONS 3V 1.53KΟ 1.3KΟ Output Output 100pF Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x 0.5 Output load 100pF 100pF AC CHARACTERISTICS (TA = -40°C to +85°C, VCC = +2.5V to +5.5V, unless otherwise specified) Symbol Parameter Min. Max. Unit 0 1 MHz 0.9 µs fSCL SCL clock frequency tAA(2) SCL LOW to SDA data out valid 0.1 tBUF Time the Bus must be free before a new transmission can start 1.2 µs Start condition hold time 0.6 µs tLOW Clock LOW period 1.2 µs tHIGH tHD:STA Clock HIGH period 0.6 µs tSU:STA Start condition setup time (for a repeated start condition) 0.6 µs tHD:DAT Data in hold time 10 ns tSU:DAT Data in setup time 100 ns tR SDA and SCL rise time 20+0.1XCb(1) 300 ns tF SDA and SCL fall time 20+0.1XCb 300 ns tSU:STO (1) Stop condition setup time tDH Data out hold time 0.6 µs 0 µs 500 ns tNOL RST to SCL non-overlap tRDV RST LOW to SDA valid during response to reset 0 450 ns tCDV CLK LOW to SDA valid during response to reset 0 450 ns tRST RST high time 1.5 µs tSU:RST RST setup time 500 ns Notes: (1)Cb = total capacitance of one bus line in pF (2)tAA = 1.1µs Max below VCC = 2.5V. RESET AC SPECIFICATIONS Power Up Timing Symbol tPUR (1) tPUW (1) Parameter Min. (2) Typ. Max. Unit Time from power up to read 1 ms Time from power up to write 5 ms Notes: (1)Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. (2)Typical values are for TA = 25°C and VCC = 5.0V REV 1.0 7/5/00 www.icmic.com Characteristics subject to change without notice. 9 of 14 X76F400 Nonvolatile Write Cycle Timing Symbol Parameter tWC Typ. Write cycle time (1) Note: (1) Min. Max. Unit 10 ms 5 (1)tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Bus Timing tHIGH tF tLOW tR SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tBUF tDH SDA OUT Write Cycle Timing SCL SDA 8th Bit of Last Byte ACK tWC STOP Condition START Condition RST Timing Diagram—Response to a Synchronous Reset RST tRST tNOL CLK nd 1 CLK 2 CLK Pulse tRDV I/O REV 1.0 7/5/00 tHIGH_RST tNOL st tSU:RST Pulse rd tLOW_RST 3 CLK Pulse tCDV Data Bit (1) www.icmic.com Data Bit (2) Characteristics subject to change without notice. 10 of 14 X76F400 Pull Up Resistance in KΟ GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS 100 80 MIN RMAX 40 20 = -------------------------= 1.8KΟ I OLMIN 60 t R R MAX RMIN = C -----------------BUS 40 60 80 100 20 Bus Capacitance in pF REV 1.0 7/5/00 V CCMAX R tR = maximum allowable SDA rise time www.icmic.com Characteristics subject to change without notice. 11 of 14 X76F400 PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) Pin 1 Index Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25) 0.050 (1.27) 0.050" Typical 0.010 (0.25) X 45° 0.020 (0.50) 0.050" Typical 0° - 8° 0.0075 (0.19) 0.010 (0.25) 0.250" 0.016 (0.410) 0.037 (0.937) 0.030" Typical FOOTPRINT 8 Places NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.0 7/5/00 www.icmic.com Characteristics subject to change without notice. 12 of 14 X76F400 PACKAGING INFORMATION 8-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 .252 (6.4) BSC (4.3) .177 (4.5) .114 (2.9) .122 (3.1) .047 (1.20) .002 (.05) .006 (.15) .0075 (.19) .0118 (.30) .010 (.25) Gage Plane 0° – 8° Seating Plane .019 (.50) .029 (.75) (4.16) (7.72) Detail A (20X) (1.78) .031 (.80) .041 (1.05) (0.42) (0.65) All Measurements Are Typical See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.0 7/5/00 www.icmic.com Characteristics subject to change without notice. 13 of 14 X76F400 Ordering Information X76F400 P T G –V Device VCC Limits Blank = 5V ±10% 2.5 = 2.5V to 5.5V RoHS Compliant Lead Free package Blank – Standard package. Non lead free Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial= –40°C to +85°C Package S8 = 8-Lead SOIC V8 = 8-Lead TSSOP H = Die in waffle packs (Contact Factory) W = Die in wafer form (Contact Factory) Part Mark Convention 8-Lead SOIC X76F400 XG XX 8-Lead TSSOP Blank = 8-Lead SOIC G = RoHS compliant lead free YWW 7640XX Blank = 4.5 to 5.5V, 0 to 70°C I = 4.5 to 5.5V, -40 to +85°C AE = 2.5 to 5.5V, 0 to 70°C AF = 2.5 to 5.5V, -40 to +85°C AE = 2.5 to 5.5V, 0 to +70°C AF = 2.5 to 5.5V, -40 to +85°C Blank = 4.5 to 5.5V, 0 to +70°C I = 4.5 to 5.5V, -40 to +85°C ©Xicor, Inc. 2000 Patents Pending LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2.A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. REV 1.0 7/5/00 www.icmic.com Characteristics subject to change without notice. 14 of 14