5102ALP 16-Bit, 20 KHz A/D Converter +VDIG 1 44 +VANLOG DGND AGND -VDIG -VANLOG -VDIG SLEEP RST SLEEP HOLD BP/UP CODE TRK1 SSH/SDL CRS/FIN TRK2 SDATA SCKMOD CLKIN LPTSTATUS XOUT +VANLOG STBY AIN2 DGND -VANLOG +VDIG AGND TRK1 REFBUF TRK2 VREF CLKIN XOUT VREF AIN1 OUTMOD HOLD BP/UP AIN1 CH1/2 CODE AIN2 SCLK SDATA +LPTBIT +LPTV -LPTV -VANLOG DGND 23 Calibration SRAM Microcontroller + TEST + CH1/2 16-Bit charge Redistribution DAC SCKMOD + OUTMOD Comparator + AGND AGND 22 SCLK Memory NC Control - CRS/FIN -VDIG Clock Generator REFBUF SSH/SDL +VDIG STBY RST VA+ VA- DGND VD- VD+ +VAN FEATURES: DESCRIPTION: • Monolithic CMOS A/D converters - Inherent sampling architecture - 2-channel input multiplexer - Flexible serial output port • Conversion time - 5102A: 40 µ s • Linearity error: ±0.001% FS - Guaranteed no missing codes • Self-calibration maintains accuracy - Over time and temperature • Fully latchup protected Maxwell Technologies’ 5102ALPRP is a 16-bit monolithic CMOS analog-to-digital converter capable of 20 kHz throughput. On-chip self-calibration achieves nonlinearity of ±0.001% of FS and guarantees 16-bit no missing codes over the entire specified temperature range. Offset and full-scale errors are minimized during the calibration cycle, eliminating the need for external trimming. The 5102ALP each consist of a 2-channel input multiplexer, DAC, conversion and calibration microcontroller, clock generator, comparator, and serial communications port. The inherent sampling architecture of the device eliminates the need for an external track and hold amplifier. Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while improving the TID performance in most space environments. This product is available with screening up to Maxwell Technologies self-defined Class K. 01.17.05 REV 3 (858) 503-3300 Fax: (858) 503-3301 - www.maxwell.com All data sheets are subject to change without notice 1 ©2005 Maxwell Technologies Inc. All rights reserved. 5102ALP 16-Bit, 20 KHz A/D Converter TABLE 1. 5102ALP ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, ALL VOLTAGES WITH RESPECT TO GROUND) PARAMETER SYMBOL MIN MAX VD+ VDVA+ VA- -0.3 0.3 -0.3 0.3 6.0 -6.0 6.0 -6.0 Input Current, Any Pin Except Supplies 2 IIN -- ±10 mA Analog Input Voltage (AIN and VREF pins) VINA (VA-) -0.3 (VA+) 0.3 V Digital Input Voltage VIND -0.3 (VA+) 0.3 V TA -15 55 oC TSTG -65 150 oC UNIT DC Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog 1 UNIT V Ambient Operating Temperature Storage Temperature 1. In addition, VD+ must not be greater than (VA+) 0.3V. 2. Transient currents of up to 100 mA will not cause SCR latchup. Memory TABLE 2. 5102ALP RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, ALL VOLTAGES WITH RESPECT TO GROUND) PARAMETER SYMBOL MIN TYP MAX DC Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog VD+ VDVA+ VA- 4.5 -4.5 4.5 -4.5 5.0 -5.0 5.0 -5.0 VA+ -5.5 5.5 -5.5 Analog Reference Voltage VREF 2.5 4.5 (VA+) -0.5 AGND -VREF --- VREF VREF Analog Input Voltage 1 Unipolar Bipolar V VAIN V V 1. The 5102ALPRP can accept input voltage up to the analog supplies (VA+ and VA-). They will produce an output of all 1s for inputs above VREF and all 0s for inputs below AGND in unipolar mode and -VREF in bipolar mode, with binary coding (CODE = low). 01.17.05 REV 3 All data sheets are subject to change without notice 2 ©2005 Maxwell Technologies Inc. All rights reserved. 5102ALP 16-Bit, 20 KHz A/D Converter TABLE 3. ANALOG CHARACTERISTICS (TA = TMIN TO TMAX; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 4.5V; FULL-SCALE INPUT SINEWAVE, 200 HZ; CLKIN = 1.6 MHZ; fS = 20 KHZ; BIPOLAR MODE; FRN MODE; AIN1 AND AIN2 TIED TOGETHER, EACH CHANNEL TESTED SEPARATELY; ANALOG SOURCE IMPEDANCE = 50 W WITH 1000 PF TO AGND UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL MIN TYP MAX UNIT Resolution 1 RES 16 -- -- Bits Full Scale Error 2 Drift 3 FSE --- ±1 ±2 ±5 -- LSB DLSB Unipolar Offset 2 Drift 3 VOFF --- ±1 ±2 ±5 -- LSB DLSB Bipolar Offset 2 Drift 3 BOFF --- ±2 ±2 ±5 -- LSB DLSB Bipolar Negative Full Scale Error 2 Drift 2 BNFSE --- ±2 ±2 ±5 -- LSB DLSB Integral Nonlinearity INL -- -- ±3 LSB Differential Nonlinearity DNL -- ±1 -- LSB Peak Harmonic or Spurious Noise 2, 4 94 100 -- dB Total Harmonic Distortion 4 -- 0.002 -- % Signal-to-Noise Ratio 2, 4 0 dB Input -60 dB Input 87 -- 90 30 --- Noise 5 Unipolar Mode Bipolar Mode --- 35 70 --- Aperture Time -- 30 -- ns Aperture Jitter -- 100 -- ps Input Capacitance 6, 4 Unipolar Mode Bipolar Mode --- 335 215 --- Accuracy Memory Dynamic Performance (Bipolar Mode) dB µ Vrms Analog Input pF Conversion and Throughput Conversion Time 7 tc -- 40.625 -- µs Acquisition Time 8 ta -- 9.375 -- µs Throughput 9, 10 ftp -- 20 -- kHz Power Supplies 01.17.05 REV 3 All data sheets are subject to change without notice 3 ©2005 Maxwell Technologies Inc. All rights reserved. 5102ALP 16-Bit, 20 KHz A/D Converter TABLE 3. ANALOG CHARACTERISTICS (TA = TMIN TO TMAX; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 4.5V; FULL-SCALE INPUT SINEWAVE, 200 HZ; CLKIN = 1.6 MHZ; fS = 20 KHZ; BIPOLAR MODE; FRN MODE; AIN1 AND AIN2 TIED TOGETHER, EACH CHANNEL TESTED SEPARATELY; ANALOG SOURCE IMPEDANCE = 50 W WITH 1000 PF TO AGND UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL MIN TYP MAX Power Supply Current 11 Positive Analog Negative Analog (SLEEP High) Positive Digital Negative Digital IA+ IAID+ ID- ----- 8.5 -7.7 0.5 -0.5 12 -11 1.5 -1.5 Power Consumption 11, 12 (SLEEP High) (SLEEP Low) Pdo Pds --- 85 45 130 -- Power Supply Rejection 13 Positive Supplies Negative Supplies PSR PSR --- 84 84 --- UNIT mA mW dB Memory 1. Minimum resolution for which no missing codes are guaranteed over the specified temperature range. 2. Applies after calibration at any temperature within the specified temperature range. 3. Total drift over specified temperature range after calibration at power-up at 25°C. 4. Guaranteed by characterization (5102A die). 5. Wideband noise aliased into the baseband. Referred to the input. 6. Applied only in the track mode. When converting or calibrating, input capacitance will not exceed 30 pF. 7. Conversion time scales directly to the master clock speed. The times shown are for synchronous, internal loopback (FRN mode). In PDT, RBT, and SSC modes, asynchronrous delay between the falling edge of HOLD and the start of conversion may add to the apparent conversion time. This delay will not exceed 1 master clock cycle + 140 ns. 8. The 5102ALPRP requires 6 clock cycles of coarse charge, followed by a minimum of 5.625 µ s of fine charge. FRN mode allows 9 clock cycles for fine charge which provides for the minimum 5.625 µ s with a 1.6 MHz clock; however, in PDT, RBT, or SSC modes, at clock frequencies less than 1.6 MHz, fine charge may be less than 9 clock cycles. 9. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions affecting acquisition and conversion times described above. 10.Typical value (measured). 11. All outputs unloaded. All inputs at VD+ or DGND. 12.Power consumption in the sleep mode applies with no master clock applied (CLKIN held high or low). 13.With 300 mV p-p, 1 kHz ripple applied to each supply separately in the bipolar mode. Rejection improves by 6 dB in the unipolar mode to 90 dB. TABLE 4. 5102ALP SWITCHING CHARACTERISTICS (TA = TMIN TO TMAX; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; INPUTS: LOGIC 0 = 0V, LOGIC 1 = VD+; CL = 50 PF) PARAMETER SYMBOL MIN TYP MAX UNIT CLKIN Period 1, 2 tclk 0.5 -- 10 µs CLKIN Low Time tclkl 200 -- -- ns CLKIN High Time tclkh 200 -- -- ns 01.17.05 REV 3 All data sheets are subject to change without notice 4 ©2005 Maxwell Technologies Inc. All rights reserved. 5102ALP 16-Bit, 20 KHz A/D Converter TABLE 4. 5102ALP SWITCHING CHARACTERISTICS (TA = TMIN TO TMAX; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; INPUTS: LOGIC 0 = 0V, LOGIC 1 = VD+; CL = 50 PF) PARAMETER Crystal Frequency 1, 2 SYMBOL MIN TYP MAX UNIT fxtal -- 1.6 -- MHz -- 20 -- ms SLEEP Rising to Oscillator Stable 3 trst 150 -- -- ns RST to STBY Falling tdrrs -- 100 -- ns RST Rising to STBY Rising tcal -- 2,882,040 -- tclk CH1/2 Edge to TRK1, TRK2 Rising 5 tdrsh1 -- 80 -- ns CH1/2 Edge to TRK1, TRK2 Falling 5 tdfsh4 -- -- 68tclk + 260 ns HOLD to SSH Falling 6 tdfsh2 -- 60 -- ns HOLD to TRK1, TRK2, Falling 6 tdfsh1 66tclk -- 68tclk + 260 ns HOLD to TRK1, TRK2, SSH Rising 6 tdrsh -- 120 -- ns HOLD Pulse Width 7 thold 1tclk + 20 -- 63tclk ns HOLD to CH1/2 Edge 6 tdhlri 300 -- 64tclk ns HOLD Falling to CLKIN Falling 7 thcf 275 -- 1tclk + 10 ns SCLK Input Pulse Period tsclk 1000 -- -- ns SCLK Input Pulse Width Low tsckll 500 -- -- ns SCLK Input Pulse Width High tsclkh 500 -- -- ns SCLK Input Falling to SDATA Valid tdss -- 100 150 ns HOLD Falling to SDATA Valid - PDT Mode tdhs -- 140 230 ns TRK1, TRK2 Falling to SDATA Valid 8 tdts -- 65 125 ns SCLK Output Pulse Width Low tslkl -- 2tclk -- tclk SCLK Output Pulse Width High tslkh -- 2tclk -- tclk SDATA Valid Before Rising SCLK tss 2tclk - 100 -- -- ns SDATA Valid After Rising SCLK tsh 2tclk - 100 -- -- ns SDL Falling to 1st Rising SCLK trsclk -- 2tclk -- ns Last Rising SCLK to SDL Rising trsdl -- 2tclk 2tclk + 200 ns HOLD Falling to 1st Falling SCLK thfs 6tclk -- 8tclk + 200 ns CH1/2 Edge to 1st Falling SCLK tchfs -- 7tclk -- tclk Memory RST Pulse Width 4 PDT and RBT Modes FRN and SSC Modes 1. Minimum CLKIN period is 0.625 µ s is FRN mode (20 kHz sample rate). 2. External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency is 1.6 MHz in FRN mode (20 kHz sample rate). 3. With a 2.0 MHz crystal, two 33 pF loading capacitors and a 10 MW parallel resistor. 4. Guaranteed by initial characterization (5102A die). 5. These times are for FRN mode. 6. These times are for PDT and RBT modes. 01.17.05 REV 3 All data sheets are subject to change without notice 5 ©2005 Maxwell Technologies Inc. All rights reserved. 5102ALP 16-Bit, 20 KHz A/D Converter 7. When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must be latched by a falling edge of CLKIN. Conversion will begin on the next rising edge of CLKIN after HOLD is latched. 8. Only valid for TRK1, TRK2 falling when SCLK is low. If SCLK is high when TRK1, TRK2 falls, then SDATA is valid tdss time after the next falling SCLK. TABLE 5. 5102ALP DIGITAL CHARACTERISTICS (TA = TMIN TO TMAX; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%) PARAMETER MIN TYP MAX UNIT Calibration Memory Retention Power Supply Voltage VA+ & VD+ 1 VMR 2.0 -- -- V High-Level Input Voltage VIH 2.0 -- -- V Low-Level Input Voltage VIL -- -- 0.8 V High-Level Output Voltage 2 VOH (VD+) -1.0 -- -- V Low-Level Output Voltage - IOUT = 1.6 mA VOL -- -- 0.4 V Input Leakage Current IIN -- -- 10 µA COUT -- 9 -- pF Digital Output Pin Capacitance Memory SYMBOL 1. VA- and VD- can be any value from zero to -5V for memory retention. Neither VA- or VD- should be allowed to go positive. AIN1, AIN2 or VREF must not be greater than VA+ or VD+. This parameter is guaranteed by characterization. 2. IOUT = -100 µ A. This specification guarantees TTL compatibility (VOH = 2.4V @ IOUT = -40 µ A. LPT™ OPERATION Latchup Protection Technology (LPT™) automatically detects an increase in the supply current of the 5102ALP converter due to a single event effect and internally cycle the power to the converter off, then on, which restores the steady state operation of the device. If data outputs are connected to a bus with other bus driver circuits, all external data bus drivers must be tri-stated and individual pull up resistors to the supply voltage (if used on the data bus) must no be less than 10 K ohm typical to assure proper single event effect recovery. STATUS can also be used to generate an input to the system data processor indicating that an LPT™ cycle has occurred, and the protected device output accuracy may not be met until after the respective recovery time to the event. The STATUS signal is generated from an advanced CMOS logic gate output. This output may not exhibit a monotonic fall time and may even oscillate briefly while power is being restored to the protected device and the decoupling capacitance is charged. Loading on the STATUS output should be minimized because this signal is used internally by the 5102ALP. It is recommended that load current not exceed 2 mA and load capacitance be kept will below 1000 pF. 01.17.05 REV 3 All data sheets are subject to change without notice 6 ©2005 Maxwell Technologies Inc. All rights reserved. 5102ALP 16-Bit, 20 KHz A/D Converter 5102ALP LPTTM BLOCK DIAGRAM +VDIG Current Sense +VANA Switch Timer +LPTV Crowbar AIN 1 AIN 2 LPTBIT 5102A Control Logic LPTSTATUS Memory VREF -LPTV Switch -VDIG -VANA Current Sense LATCH-UP PROTECTION CIRCUIT (LPT) PIN DESCRIPTION PIN PIN NAME FUNCTION 18 LPTBIT The LPT circuit will crowbar the power supplies to the SEI5102ALPRP for as long as a logical high is applied. Used to verify operation of the LPT. Normally a logical low or ground is applied to this input. 26 -LPTV Negative power supply. VA- and VD- are connected and can be measured on this pin. Normally -5V. 27 +LPTV Positive power supply. VA+ and VD+ are connected and can be measured on this pin. Normally +5V. 01.17.05 REV 3 All data sheets are subject to change without notice 7 ©2005 Maxwell Technologies Inc. All rights reserved. 5102ALP 16-Bit, 20 KHz A/D Converter LATCH-UP PROTECTION CIRCUIT (LPT) PIN DESCRIPTION PIN 39 PIN NAME LPTSTATUS FUNCTION A 0 to 5V square-wave will output during a latch condition. Normally low. . FIGURE 1. RESET AND CALIBRATION TIMING Memory FIGURE 2. CONTROL OUTPUT TIMING FIGURE 3. CHANNEL SELECTION TIMING 01.17.05 REV 3 All data sheets are subject to change without notice 8 ©2005 Maxwell Technologies Inc. All rights reserved. 5102ALP 16-Bit, 20 KHz A/D Converter FIGURE 4. START CONVERSION TIMING FIGURE 5. SERIAL DATA TIMING Memory FIGURE 6. DATA TRANSMISSION TIMING 01.17.05 REV 3 All data sheets are subject to change without notice 9 ©2005 Maxwell Technologies Inc. All rights reserved. 5102ALP 16-Bit, 20 KHz A/D Converter FIGURE 7. BYPASS CIRCUIT +VDIG 1 +VANLOG 44 DGND AGND -VDIG -VANLOG -VDIG SLEEP RST SCKMOD LPTSTATUS XOUT +VANLOG STBY AIN2 DGND -VANLOG +VDIG AGND TRK1 REFBUF TRK2 VREF CRS/FIN AIN1 SSH/SDL OUTMOD HOLD BP/UP CH1/2 CODE SCLK SDATA +LPTBIT +LPTV NC -LPTV -VDIG -VANLOG DGND AGND +VDIG 22 +VANLOG 23 1 µF 1 µF 4.7 µF + + Memory CLKIN 4.7 µF + + Note: 1. Cap must be connected to the device for proper operation. 4.7 µ F analog side. 1 µ F digital side. 2. Unused logic inputs should be tied to +VD or DGND. FIGURE 8. POWER-UP RESET CIRCUIT +VD +5V 1N4148 R RST C 01.17.05 REV 3 All data sheets are subject to change without notice 10 ©2005 Maxwell Technologies Inc. All rights reserved. 5102ALP 16-Bit, 20 KHz A/D Converter Memory 44 PIN FRP SYMBOL DIMENSION MIN NOM MAX A 0.256 0.282 0.308 b 0.014 0.017 0.020 c 0.009 0.010 0.012 D 1.089 1.100 1.111 E 0.564 0.570 0.576 E1 -- -- 0.600 E2 0.410 0.430 0.450 E3 0.044 0.070 -- e 0.050 BSC L 0.455 0.465 0.475 Q 0.022 0.027 0.032 S1 0.005 -- -- N 44 F44 Note: All dimensions in inches 01.17.05 REV 3 All data sheets are subject to change without notice 11 ©2005 Maxwell Technologies Inc. All rights reserved. 5102ALP 16-Bit, 20 KHz A/D Converter Important Notice: These data sheets are created using the chip manufacturers published specifications. MAxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against MAxwell TechnologiesInc. must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts. Memory 01.17.05 REV 3 All data sheets are subject to change without notice 12 ©2005 Maxwell Technologies Inc. All rights reserved. 5102ALP 16-Bit, 20 KHz A/D Converter Product Ordering Options Memory 01.17.05 REV 3 All data sheets are subject to change without notice 13 ©2005 Maxwell Technologies Inc. All rights reserved. 5102ALP 16-Bit, 20 KHz A/D Converter Model Number 5102ALP - RP - F - X Screening Flow Multi Chip Module (MCM)1 K = Maxwell Self-Defined Class K H = Maxwell Self-Defined Class H I = Industrial (testing @ -40°C, +25°C, +110°C) E = Engineering (testing @ +25°C) F = Flat Pack Radiation Feature RP = RAD-PAK® package Base Product Nomenclature 16-Bit 20KHz A/D Converter Memory Package 1) Products are manufactured and screened to Maxwell Technologies self-defined Class H and Class K flows. 01.17.05 REV 3 All data sheets are subject to change without notice 14 ©2005 Maxwell Technologies Inc. All rights reserved.