54ACTQ544 Quiet Series Octal Registered Transceiver with TRI-STATE ® Outputs General Description Features The ACTQ544 is an inverting octal transceiver containing two sets of D-type registers for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent input and output control in either direction of data flow. The ’544 inverts data in both directions. The ACTQ utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series™ features GTO™ output control and undershoot corrector in addition to a split ground bus for superior performance. n Guaranteed simultaneous switching noise level and dynamic threshold performance n 8-bit inverting octal latched transceiver n Separate controls for data flow in each direction n Back-to-back registers for storage n Outputs source/sink 24 mA n 4 kV minimum ESD immunity Logic Symbols IEEE/IEC DS100248-1 DS100248-4 Pin Names Description OEAB A-to-B Output Enable Input (Active LOW) OEBA B-to-A Output Enable Input (Active LOW) CEAB A-to-B Enable Input (Active LOW) CEBA B-to-A Enable Input (Active LOW) LEAB A-to-B Latch Enable Input (Active LOW) LEBA B-to-A Latch Enable Input (Active LOW) A0 –A7 A-to-B Data Inputs or B-to-A TRI-STATE Outputs B0 –B7 B-to-A Data Inputs or A-to-B TRI-STATE Outputs GTO™ is a trademark of National Semiconductor Corporation. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. FACT Quiet Series™ is a trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100248 www.national.com 54ACTQ544 Quiet Series Octal Registered Transceiver with TRI-STATE Outputs August 1998 Connection Diagrams Pin Assignment for LCC Pin Assignment for DIP and Flatpak DS100248-3 Functional Description The ACTQ544 contains two sets of eight D-type latches, with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB) input must be LOW in order to enter data from A0 –A7 or take data from B0 –B7, as indicated in the Data I/O Control Table. With CEAB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the TRI-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA inputs. DS100248-2 Data I/O Control Table Inputs Latch Output LEAB OEAB Status Buffers H X X Latched High Z X H X Latched — L L X Transparent — X X H — High Z L X L — Driving CEAB H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA and OEBA www.national.com 2 Logic Diagram DS100248-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.national.com Absolute Maximum Ratings (Note 1) DC Latch-up Source or Sink Current Junction Temperature (TJ) CDIP If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) −0.5V to +7.0V ± 300 mA 175˚C Recommended Operating Conditions −20 mA +20 mA −0.5V to VCC + 0.5V Supply Voltage VCC ’ACTQ Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) (Note 2) 54ACTQ Minimum Input Edge Rate ∆V/∆t ’ACTQ Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65˚C to +150˚C 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. Note 2: Surface mount and plastic dip packaging is not recommended for applications requiring greater than 2000 temperature cycles from −40˚C to +125˚C. DC Characteristics for ’ACTQ Family Devices Symbol Parameter VCC 54ACTQ TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH VOL IIN Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Minimum High Level 4.5 4.4 Output Voltage 5.5 5.4 4.5 3.70 5.5 4.70 Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 Maximum Input V VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA V (Note 3) VIN = VIL or VIH IOH = −24 mA V IOH = −24 mA IOUT = 50 µA V (Note 3) VIN = VIL or VIH IOL = 24 mA IOL = 24 mA VI = VCC, GND 4.5 0.50 5.5 0.50 5.5 ± 1.0 µA 5.5 ± 10.0 µA VI, (OE) = VIL, VIH VO = VCC, GND 5.5 1.6 mA VI = VCC − 2.1V Leakage Current IOZT Maximum I/O Leakage Current ICCT Maximum ICC/Input www.national.com 4 DC Characteristics for ’ACTQ Family Devices Symbol Parameter (Continued) VCC 54ACTQ TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits 5.5 50 mA IOHD Minimum Dynamic Output Current (Note 4) 5.5 −50 mA ICC Maximum Quiescent 5.5 160.0 µA VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC 5.0 1.6 V 2–12, 13 5.0 −1.2 V IOLD Supply Current VOLP or GND (Note 5) Quiet Output Maximum Dynamic VOL VOLV Quiet Output (Notes 6, 7) Minimum Dynamic VOL 2–12, 13 (Notes 6, 7) Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: ICC for 54ACTQ @ 25˚C is identical to 74ACTQ@ 25˚C. Note 6: Plastic DIP package. Note 7: Max number of outputs defined as (n-1). Data Inputs are driven 0V to 3V, one output @ GND. Note 8: Max number of Data Inputs (n) switching (n-1) inputs switching 0V to 3V (’ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. AC Electrical Characteristics VCC Symbol Parameter (V) (Note 9) tPLH Propagation Delay tPHL Transparent Mode 54ACTQ TA = −55˚C to +125˚C CL = 50 pF Fig. Units Min Max 5.0 2.0 9.5 ns 5.0 2.0 11.0 ns 5.0 1.5 13.0 ns 5.0 1.5 9.0 ns No. An to Bn or Bn to An tPLH Propagation Delay tPHL LEBA, LEAB to An, Bn tPZH Output Enable Time tPZL OEBA or OEAB to An or Bn CEBA or CEAB to An or Bn tPHZ tPLZ Output Disable Time OEBA or OEAB to An or Bn CEBA or CEAB to An or Bn Note 9: Voltage Range 5.0 is 5.0V ± 0.5V Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design. Not tested. 5 www.national.com AC Operating Requirements 54ACTQ TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 11) Fig. Units Guaranteed Minimum Setup Time, HIGH or LOW ts 5.0 3.0 ns 5.0 1.5 ns 5.0 4.0 ns An or Bn to LEBA or LEAB th Hold Time, HIGH or LOW An or Bn to LEBA or LEAB tw Latch Enable, B to A Pulse Width, LOW Note 11: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol CIN CPD Typ Units Input Capacitance Parameter 4.5 pF Power Dissipation 80.0 pF Capacitance www.national.com 6 Conditions VCC = 5.0V VCC = 5.0V No. Physical Dimensions inches (millimeters) unless otherwise noted 28-Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E28A 24-Lead Ceramic Dual-In-Line Package (D) NS Package Number J24F 7 www.national.com 54ACTQ544 Quiet Series Octal Registered Transceiver with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Ceramic Flatpak (F) NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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