RENESAS 7220

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 7200 SERIES
7220
Group
User’s Manual
keep safety first in your circuit designs !
● Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury,
fire or property damage. Remember to give due consideration to safety when
making your circuit designs, with appropriate measures such as (i) placement
of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.
Notes regarding these materials
● These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the customer’s
application; they do not convey any license under any intellectual property rights,
or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
● Mitsubishi Electric Corporation assumes no responsibility for any damage, or
infringement of any third-party’s rights, originating in the use of any product
data, diagrams, charts or circuit application examples contained in these materials.
● All information contained in these materials, including product data, diagrams
and charts, represent information on products at the time of publication of these
materials, and are subject to change by Mitsubishi Electric Corporation without
notice due to product improvements or other reasons. It is therefore recommended
that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
● Mitsubishi Electric Corporation semiconductors are not designed or manufactured
for use in a device or system that is used under circumstances in which human
life is potentially at stake. Please contact Mitsubishi Electric Corporation or an
authorized Mitsubishi Semiconductor product distributor when considering the
use of a product contained herein for any specific purposes, such as apparatus
or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea
repeater use.
● The prior written approval of Mitsubishi Electric Corporation is necessary to
reprint or reproduce in whole or in part these materials.
● If these products or technologies are subject to the Japanese export control
restrictions, they must be exported under a license from the Japanese government
and cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of
JAPAN and/or the country of destination is prohibited.
● Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or the
products contained therein.
Preface
This manual describes the hardware of the Mitsubishi
CMOS 8-bit microcomputers 7220 group.
After reading this manual, the user should have a
through knowledge of the functions and features of
7220 group, and should be able to fully utilize the
product. The manual starts with specifications and
ends with application examples.
For details of software, refer to the “SERIES 740
<SOFTWARE> USER’S MANUAL.”
For details of development support tools, refer to the
“DEVELOPMENT SUPPORT TOOLS FOR
MICROCOMPUTERS” data book.
BEFORE USING THIS MANUAL
This user’s manual consists of the following chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development. The M37221M6-XXXSP/FP is used as a general example
in describing the functions of the 7220 group, unless other wise noted.
1. Organization
● CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer, pin configuration, pin description, functional
block diagram.
● CHAPTER 2 FUNCTIONAL DESCRIPTION
This chapter describes operation of each peripheral function.
● CHAPTER 3 ELECTRIC CHARACTERISTICS
This chapter describes electric characteristics and standard characteristics.
● CHAPTER 4 M37220M3-XXXSP/FP
This chapter describes differences between the M37220M3-XXXSP/FP and M37221M6-XXXSP/FP.
● CHAPTER 5 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on
setting examples of related registers.
● CHAPTER 6 APPENDIX
This chapter includes precautions for systems development using the microcomputer, a list of control
registers, the mask ROM confirmation forms (mask ROM version) and mark specification forms which
are to be submitted when ordering.
i
2. Register diagram
The figure of each register structure describes its functions, contents at reset, end attributes as follows:
Bit attributes (Note 2)
Bits
Values immediately after reset release (Note 1)
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1 1 1 1 1
0 0
CPU mode register (CPUM) (CM) [Address FB 16]
B
Name
0, 1 Fix these bits to “0.”
2
Stack page selection
bit (CM2)
Functions
0: 0 page
1: 1 page
3 Fix these bits to “1.”
to
5
After reset
R W
0
R W
1
R W
1
R W
Indeterminate R W
6, 7
: Bit in which nothing is assigned
Notes 1: Values immediately after reset release
0••••••“0” after reset release
1••••••“1” after reset release
?••••••Indeterminate after reset release
2: Bit attributes••••••The attributes of control register bits are classified into 3 types : read-only, write-only
and read and write. In the figure, these attributes are represented as follows :
W••••••Write
R••••••Read
R ••••••Read enabled
W ••••••Write enabled
— ••••••Read disabled
— ••••••Write disabled
✽ ••••••“0” can be set by software, but “1”
cannot be set.
ii
Table of contents
Table of contents
CHAPTER 1. OVERVIEW
1.1
1.2
1.3
1.4
Performance overview ..........................................................................................................
Pin configuration ...................................................................................................................
Pin description ......................................................................................................................
Functional block diagram ...................................................................................................
1-2
1-5
1-7
1-9
CHAPTER 2. FUNCTIONAL DESCRIPTION
2.1 Central processing unit ....................................................................................................... 2-2
2.1.1 Accumulator (A) ............................................................................................................. 2-2
2.1.2 Index register X (X), index register Y (Y) .................................................................. 2-2
2.1.3 Stack pointer (S) ............................................................................................................ 2-3
2.1.4 Program counter (PC) ................................................................................................... 2-6
2.1.5 Processor status register (PS) ..................................................................................... 2-6
2.2 Access area ............................................................................................................................ 2-8
2.2.1 Zero page (addresses 000016 to 00FF 16) .................................................................. 2-10
2.2.2 Special page (addresses FF0016 to FFFF16) ............................................................ 2-10
2.3 Memory assignment ........................................................................................................... 2-11
2.3.1 Internal RAM ................................................................................................................ 2-16
2.3.2 I/O ports (addresses 00C0 16 to 00CD16) ................................................................... 2-16
2.3.3 DA registers (addresses 00CE 16 and 00CF 16) .......................................................... 2-17
2.3.4 PWM registers (addresses 00D016 to 00D416 and 00F616) ..................................... 2-17
2.3.5 PWM output control registers (addresses 00D5 16 and 00D6 16) ............................. 2-17
2.3.6 Multi-master I2C-BUS related registers (addresses 00D716 to 00DB16) ................. 2-17
2.3.7 Serial I/O related registers (addresses 00DC16 and 00DD 16) ................................. 2-17
2.3.8 CRT display related registers (addresses 00E0 16 to 00EC16) ................................ 2-17
2.3.9 A-D control register (addresses 00EE 16 and 00EF16) .............................................. 2-18
2.3.10 Timer registers (addresses 00F016 to 00F316) ........................................................ 2-18
2.3.11 Timer mode registers (address 00F416, 00F516) .................................................... 2-19
2.3.12 CPU mode register (address 00FB16) ..................................................................... 2-19
2.3.13 Interrupt request registers (addresses 00FC 16 and 00FD 16) ................................. 2-19
2.3.14 Interrupt control registers (addresses 00FE 16 and 00FF16) .................................. 2-19
2.3.15 2 page register (addresses 021716 to 021B16 ) (only M37221M8/MA-XXXSP) .. 2-19
2.3.16 CRT display RAM (addresses 060016 to 06B7 16) .................................................. 2-19
2.3.17 ROM (addresses A00016 to FFFF16) ........................................................................ 2-19
2.3.18 CRT display ROM (addresses 1000016 to 11FFF16) .............................................. 2-19
2.4 Input/Output pins ................................................................................................................ 2-20
2.4.1 Programmable ports .................................................................................................... 2-20
2.4.2 Dedicated pins ............................................................................................................. 2-23
2.5 Interrupts .............................................................................................................................. 2-26
2.5.1 Interrupt sources .......................................................................................................... 2-27
2.5.2 Interrupt control ............................................................................................................ 2-29
2.6 Timers .................................................................................................................................... 2-34
2.6.1 Timer functions ............................................................................................................ 2-35
2.6.2 Timers 3 and timer 4 when reset and when executing STP instruction .............. 2-39
7220 Group User’s Manual
i
Table of contents
Table of contents
2.7 Serial I/O ............................................................................................................................... 2-40
2.7.1 Structure of serial I/O ................................................................................................. 2-40
2.7.2 Serial I/O register (address 00DD 16) ......................................................................... 2-42
2.7.3 Clock source generating circuit ................................................................................. 2-42
2.7.4 Serial input/output common transmission/reception mode ..................................... 2-42
2.7.5 Serial I/O data receive method (when an internal clock is selected) .................. 2-43
2.7.6 Serial I/O data transmit method (when an external clock is selected) ................ 2-44
2.7.7 Note when selecting a synchronous clock ............................................................... 2-45
2.8 Multi-master I2C-BUS interface ......................................................................................... 2-47
2.8.1 Construction of multi-master I2C-BUS interface ....................................................... 2-48
2.8.2 Multi-master I2C-BUS interface-related registers ..................................................... 2-49
2.8.3 START condition, STOP condition generation method ........................................... 2-58
2.9 A-D comparator ................................................................................................................... 2-61
2.10 PWM ..................................................................................................................................... 2-63
2.10.1 8-bit PWM registers (addresses 00D016 to 00D416 and 00F6 16)
/DA registers (addresses 00CE 16 and 00CF 16) .................................................... 2-64
2.10.2 14-bit PWM (DA output) ........................................................................................... 2-65
2.10.3 8-bit PWM (PWM0 to PWM5: address 00D0 16 to 00D4 16 and 00F6 16 ) ............. 2-67
2.10.4 14-bit PWM output control ........................................................................................ 2-69
2.10.5 8-bit PWM output control .......................................................................................... 2-70
2.11 CRT display function ....................................................................................................... 2-71
2.11.1 Display position .......................................................................................................... 2-74
2.11.2 Character size ............................................................................................................ 2-77
2.11.3 Memory for display .................................................................................................... 2-78
2.11.4 Color registers ............................................................................................................ 2-82
2.11.5 Multiline display ......................................................................................................... 2-84
2.11.6 Character border function ......................................................................................... 2-85
2.11.7 CRT output pin control ............................................................................................. 2-86
2.11.8 Raster coloring function ............................................................................................ 2-87
2.11.9 Clock for display ........................................................................................................ 2-88
2.12 ROM correction function ................................................................................................. 2-89
2.13 Software runaway detect function ................................................................................ 2-90
2.14 Low-power dissipation mode ......................................................................................... 2-91
2.14.1 Stop mode .................................................................................................................. 2-91
2.14.2 Wait mode .................................................................................................................. 2-93
2.14.3 Interrupts in low-power dissipation mode ............................................................... 2-93
2.15 Reset .................................................................................................................................... 2-95
2.15.1 Reset operation .......................................................................................................... 2-95
2.15.2 Internal state immediately after reset ..................................................................... 2-96
2.15.3 Notes for poweron reset ........................................................................................... 2-99
2.16 Clock generating circuit ................................................................................................ 2-100
2.17 Oscillation circuit ............................................................................................................ 2-101
CHAPTER 3. ELECTRICAL CHARACTERISTICS
3.1 Electrical characteristics ..................................................................................................... 3-2
3.2 Standard characteristics...................................................................................................... 3-6
ii
7220 Group User’s Manual
Table of contents
CHAPTER 4. M37220M3-XXXSP/FP
4.1
4.2
4.3
4.4
4.5
Performance overview .......................................................................................................... 4-2
Pin configuration ................................................................................................................... 4-4
Pin description ...................................................................................................................... 4-6
Functional block diagram ................................................................................................... 4-8
Functional description ......................................................................................................... 4-9
4.5.1 Access area .................................................................................................................. 4-10
4.5.2 Memory assignment ..................................................................................................... 4-11
4.5.3 Input/Output pins ......................................................................................................... 4-14
4.5.4 Interrupts ....................................................................................................................... 4-15
4.5.5 D-A converter ............................................................................................................... 4-17
4.5.6 CRT Display function .................................................................................................. 4-19
4.5.7 Internal state immediately after reset ....................................................................... 4-26
4.6 Electrical characteristics ................................................................................................... 4-28
4.7 Standard characteristics.................................................................................................... 4-32
CHAPTER 5. APPLICATION
5.1 Example of multi-line display............................................................................................. 5-2
5.1.1 Specifications ................................................................................................................. 5-2
5.1.2 Connection example ...................................................................................................... 5-2
5.1.3 General flowchart ........................................................................................................... 5-3
5.1.4 Set of display character data ....................................................................................... 5-6
5.1.5 Line counter.................................................................................................................... 5-7
5.1.6 Processing time ............................................................................................................. 5-8
5.1.7 Set of multiple interrupts .............................................................................................. 5-9
5.2 Notes on programming for OSD (M37220M3-XXXSP/FP) ........................................... 5-13
5.2.1 Setting of color registers ............................................................................................ 5-13
5.2.2 Setting of border selection register ........................................................................... 5-14
5.2.3 Number of display characters .................................................................................... 5-14
5.3 Usage example of ROM correction function (M37221M8/MA-XXXSP) ..................... 5-15
5.3.1 Connection example .................................................................................................... 5-15
5.3.2 Correction example ...................................................................................................... 5-15
5.3.3 E 2PROM map ............................................................................................................... 5-17
5.3.4 General flowchart ......................................................................................................... 5-19
5.3.5 Notes on use ................................................................................................................ 5-20
5.4 Example of I2C-BUS interface control (M37221Mx-XXXSP/FP) .................................. 5-21
5.4.1 Specifications ............................................................................................................... 5-21
5.4.2 Connection example .................................................................................................... 5-21
5.4.3 E 2PROM functions ....................................................................................................... 5-22
5.4.4 General flowchart ......................................................................................................... 5-23
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP) ............................ 5-26
5.5.1 Specifications ............................................................................................................... 5-26
5.5.2 Connection example .................................................................................................... 5-26
5.5.3 Single-chip color TV signal processor function ....................................................... 5-27
5.5.4 General flowchart ......................................................................................................... 5-28
5.5.5 Data setting according to key processing ................................................................ 5-34
5.5.6 Flowchart of data setting according to key processing .......................................... 5-36
5.5.7 Register map ................................................................................................................ 5-39
5.6 Application circuit example .............................................................................................. 5-45
5.6.1 Application circuit example 1 ..................................................................................... 5-45
5.6.2 Application circuit example 2 ..................................................................................... 5-46
7220 Group User’s Manual
iii
Table of contents
CHAPTER 6. APPENDIX
6.1 Package outline ..................................................................................................................... 6-2
6.2 Termination of unused pins ............................................................................................... 6-3
6.3 Notes on use ......................................................................................................................... 6-4
6.3.1 Notes on processor status register ............................................................................. 6-4
6.3.2 Notes on decimal operation ......................................................................................... 6-5
6.3.3 Notes on Interrupts ........................................................................................................ 6-5
6.3.4 Notes on serial I/O ........................................................................................................ 6-6
6.3.5 Notes on timer ............................................................................................................... 6-7
6.3.6 Notes on A-D comparator ............................................................................................. 6-8
6.3.7 Note on RESET pin ....................................................................................................... 6-8
6.3.8 Notes on input and output pins ................................................................................... 6-9
6.3.9 Note on JMP instruction ............................................................................................... 6-9
6.3.10 Note on multi-master I2C-BUS interface ................................................................. 6-10
6.3.11 Termination of unused pins ...................................................................................... 6-10
6.4 Counter measures against noise .................................................................................... 6-11
6.4.1 Shortest wiring length ................................................................................................. 6-11
6.4.2 connection of a bypass capacitor across V SS line and VCC line ............................ 6-13
6.4.3 Wiring to analog input pins ........................................................................................ 6-13
6.4.4 Oscillator concerns ...................................................................................................... 6-14
6.4.5 Setup for I/O ports ...................................................................................................... 6-15
6.4.6 Providing of watchdog timer function by software .................................................. 6-16
6.5 Memory assignment ........................................................................................................... 6-17
6.6 SFR assignment .................................................................................................................. 6-20
6.7 Control registers ................................................................................................................. 6-30
6.8 Ports ...................................................................................................................................... 6-51
6.9 Machine instruction table .................................................................................................. 6-53
6.10 Instruction code table ...................................................................................................... 6-63
6.11 Mask ROM ordering method........................................................................................... 6-64
6.12 Mark specification form ................................................................................................... 6-80
iv
7220 Group User’s Manual
List of figures
List of figures
CHAPTER 1. OVERVIEW
Fig. 1.2.1 Pin configuration (top view) (1) ................................................................................. 1-5
Fig. 1.2.2 Pin configuration (top view) (2) ................................................................................. 1-6
Fig. 1.4.1 Functional block diagram ............................................................................................ 1-9
CHAPTER 2. FUNCTIONAL DESCRIPTION
Fig. 2.1.1 Registers configuration diagram ................................................................................ 2-2
Fig. 2.1.2 CPU mode register ...................................................................................................... 2-3
Fig. 2.1.3 Sequence of push onto/pop from a stack during interrupts and
subroutine calls ............................................................................................................ 2-5
Fig. 2.1.4 Contents of stack after execution of BRK instruction ............................................. 2-7
Fig. 2.2.1 Access area of M37221M4-XXXSP and M37221M6-XXXSP/FP ........................... 2-8
Fig. 2.2.2 Access area of M37221M8-XXXSP and M37221MA-XXXSP ................................. 2-9
Fig. 2.3.1 Memory assignment of M37221M4-XXXSP and M37221M6-XXXSP/FP ............ 2-11
Fig. 2.3.2 Memory assignment of M37221M8-XXXSP and M37221MA-XXXSP .................. 2-12
Fig. 2.3.3 Memory map of SFR (special function register) (1) ............................................. 2-13
Fig. 2.3.4 Memory map of SFR (special function register) (2) ............................................. 2-14
Fig. 2.3.5 Memory map of 2 page register (only M37221M8-XXXSP and
M37221MA-XXXSP) ................................................................................................... 2-15
Fig. 2.3.6 I/O setting example of port ...................................................................................... 2-16
Fig. 2.3.7 Access to timer registers .......................................................................................... 2-18
Fig. 2.4.1 I/O pin block diagram (1) ......................................................................................... 2-24
Fig. 2.4.2 I/O pin block diagram (2) ......................................................................................... 2-25
Fig. 2.5.1 V SYNC interrupt generation timing .............................................................................. 2-27
Fig. 2.5.2 Interrupt control logic ................................................................................................ 2-29
Fig. 2.5.3 Interrupt request register 1 (address 00FC 16) ........................................................ 2-30
Fig. 2.5.4 Interrupt request register 2 (address 00FD 16) ........................................................ 2-30
Fig. 2.5.5 Interrupt control register 1 (address 00FE 16) ......................................................... 2-31
Fig. 2.5.6 Interrupt control register 2 (address 00FF 16).......................................................... 2-31
Fig. 2.5.7 Interrupt input polatiry register (address 00F916) ................................................... 2-32
Fig. 2.5.8 CRT port control register (address 00EC16) ........................................................... 2-32
Fig. 2.5.9 Interrupt control system ............................................................................................ 2-33
Fig. 2.5.10 Interrupt vector table ............................................................................................... 2-33
Fig. 2.6.1 Timer 1, timer 2, timer 3, and timer 4 block diagram .......................................... 2-34
Fig. 2.6.2 Timer overflow timing ................................................................................................ 2-35
Fig. 2.6.3 Timer 12 mode register (address 00F4 16) .............................................................. 2-36
Fig. 2.6.4 Timer 34 mode register (address 00F5 16) .............................................................. 2-37
Fig. 2.6.5 Example of timer system .......................................................................................... 2-38
Fig. 2.7.1 Serial I/O block diagram ........................................................................................... 2-41
Fig. 2.7.2 Serial I/O mode register (address 00DC16) ............................................................ 2-41
Fig. 2.7.3 Serial input/output common transfer mode block diagram ................................... 2-42
Fig. 2.7.4 Serial I/O register when receiving (when SM5 = “0”) ........................................... 2-43
Fig. 2.7.5 Serial I/O register when transmitting (when SM5 = “0”) ...................................... 2-44
Fig. 2.7.6 Timing diagram of serial I/O .................................................................................... 2-45
Fig. 2.7.7 Connection example for serial I/O transmit/receive .............................................. 2-46
Fig. 2.7.8 Serial data transmit/receive processing sequence ................................................ 2-46
7220 Group User’s Manual
v
List of figures
2.8.1 Block diagram of multi-masteer I2C-BUS interface ................................................ 2-48
2.8.2 I 2C data shift register ................................................................................................ 2-49
2.8.3 I2C address register ................................................................................................... 2-50
2.8.4 I2C clock control register .......................................................................................... 2-52
2.8.5 Connection port control by BSEL0 and BSEL1 ..................................................... 2-53
2.8.6 I2C control register ..................................................................................................... 2-54
2.8.7 Interrupt request signal generating timing .............................................................. 2-57
2.8.8 I2C status register ...................................................................................................... 2-57
2.8.9 START condition generation timing diagram ........................................................ 2-58
2.8.10 STOP condition generation timing diagram ........................................................ 2-58
2.8.11 START condition/STOP condition detect timing diagram ................................... 2-59
2.8.12 Address data communication format ................................................................... 2-60
2.9.1 A-D comparator block diagram ................................................................................ 2-61
2.9.2 A-D control register 1 (address 00EE16) ................................................................. 2-62
2.9.3 A-D control register 2 (address 00EF16) ................................................................. 2-62
2.10.1 14-bit PWM (DA) block diagram ............................................................................ 2-63
2.10.2 8-bit PWM block diagram ....................................................................................... 2-64
2.10.3 14-bit PWM output example (f(X IN) = 8 MHz) ...................................................... 2-66
2.10.4 Pulse waveforms corresponding to weight of each bit of 8-bit PWM register 2-68
2.10.5 Example of 8-bit PWM output ................................................................................ 2-68
2.10.6 PWM output control register 1 (address 00D516) ................................................ 2-69
2.10.7 PWM output control register 2 (address 00D616) ................................................ 2-70
2.11.1 Structure of CRT display character ....................................................................... 2-71
2.11.2 CRT display circuit block diagram ......................................................................... 2-72
2.11.3 CRT control register (address 00EA16) ................................................................. 2-73
2.11.4 Count method of synchronous signal .................................................................... 2-74
2.11.5 Display position ........................................................................................................ 2-75
2.11.6 Vertical position register n (addresses 00E1 16 and 00E2 16) ............................... 2-76
2.11.7 Horizontal position register (address 00E016) ....................................................... 2-76
2.11.8 Character size register (address 00E416) ............................................................. 2-77
2.11.9 Display start position (horizontal direction) for each character size ................. 2-77
2.11.10 Example of display character data storing form................................................ 2-78
2.11.11 Structure of CRT display RAM ............................................................................ 2-81
2.11.12 Color register n (addresses 00E616 to 00E9 16) .................................................. 2-82
2.11.13 Generation timing of CRT interrupt request ....................................................... 2-84
2.11.14 Display state of blocks and occurrence of CRT interrupt request .................. 2-84
2.11.15 Border example ...................................................................................................... 2-85
2.11.16 Border selection register (address 00E5 16) ........................................................ 2-85
2.11.17 CRT port control register (address 00EC 16) ....................................................... 2-86
2.11.18 MUTE signal output example ............................................................................... 2-87
2.11.19 CRT clock selection register ................................................................................ 2-88
2.12.1 ROM correction address registers ......................................................................... 2-89
2.12.2 ROM correction enable register ............................................................................. 2-89
2.13.1 Sequence at detecting software runaway detection ............................................ 2-90
2.14.1 Oscillation stabilizing time at return by reset input............................................. 2-92
2.14.2 Execution sequence example at return by occurrence of INT0 interrupt
request ...................................................................................................................... 2-92
Fig. 2.14.3 Reset input time....................................................................................................... 2-93
Fig. 2.14.4 State transitions of low-power dissipation mode ................................................. 2-94
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
vi
7220 Group User’s Manual
List of figures
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
2.15.1
2.15.2
2.15.3
2.15.4
2.15.5
2.15.6
2.15.7
2.16.1
2.17.1
2.17.2
2.17.3
Timing diagram at reset .......................................................................................... 2-95
Internal state immediately after reset (1) ............................................................. 2-96
Internal state immediately after reset (2) ............................................................. 2-97
Internal state immediately after reset (3) (only M37221M8/MA-XXXSP) ........ 2-98
Voltage at poweron reset ....................................................................................... 2-99
Example of reset circuit (1) .................................................................................... 2-99
Example of reset circuit (2) .................................................................................... 2-99
Clock generating circuit block diagram ............................................................... 2-100
Clock oscillation circuit using a ceramic resonator ........................................... 2-101
External clock input circuit example .................................................................... 2-101
Clock oscillation circuit for CRT display ............................................................. 2-101
CHAPTER 3. ELECTRICAL CHARACTERISTICS
Fig. 3.1.1 Definition diagram of timing on multi-master I 2C-BUS ............................................ 3-5
CHAPTER 4. M37220M3-XXXSP/FP
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
4.2.1 Pin configuration (top view) (1) ................................................................................. 4-4
4.2.2 Pin configuration (top view) (2) ................................................................................. 4-5
4.4.1 Functional block diagram ............................................................................................ 4-8
4.5.1 Access area ................................................................................................................ 4-10
4.5.2 Memory assignment ................................................................................................... 4-11
4.5.3 Memory map of SFR (special function register) (1) ............................................. 4-12
4.5.4 Memory map of SFR (special function register) (2) ............................................. 4-13
4.5.5 Interrupt request register 1 (address 00FC 16) ........................................................ 4-16
4.5.6 Interrupt control register 1 (address 00FE16) ......................................................... 4-16
4.5.7 D-A converter block diagram .................................................................................... 4-17
4.5.8 DA n conversion register (addresses 00DE16 and 00DF 16) .................................. 4-18
4.5.9 Port P3 output mode control register (address 00CD16) ...................................... 4-18
4.5.10 CRT display circuit block diagram ......................................................................... 4-20
4.5.11 Example of display character data storing form .................................................. 4-21
4.5.12 Structure of CRT display RAM .............................................................................. 4-23
4.5.13 Border selection register (addresses 00E5 16) ...................................................... 4-24
4.5.14 Color register n (addresses 00E616 to 00E9 16) .................................................... 4-24
4.5.15 CRT control register (address 00EA16) ................................................................. 4-25
4.5.16 CRT port control register (address 00EC 16) ......................................................... 4-25
4.5.17 Internal state immediately after reset (1) ............................................................. 4-26
4.5.18 Internal state immediately after reset (2) ............................................................. 4-27
CHAPTER 5. APPLICATION
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
5.1.9
Connection example .................................................................................................... 5-2
Display example ........................................................................................................... 5-2
Flowchart of initialization processing routine ........................................................... 5-3
Flowchart of V SYNC interrupt processing routine ....................................................... 5-4
Flowchart of CRT interrupt processing routine ........................................................ 5-5
Set of display character data ..................................................................................... 5-6
Example of setup timing for line counter and display character data .................. 5-7
Timing of interrupt processing when not setting multiple interrupts ..................... 5-9
Timing when all interrupt request bits are “1” at the same sampling point ..... 5-10
7220 Group User’s Manual
vii
List of figures
Fig. 5.1.10 Flowchart of CRT interrupt processing routine
(when setting multiple interrupts) .......................................................................... 5-11
Fig. 5.1.11 Flowchart of VSYNC interrupt processing routine
(when setting multiple interrupts) .......................................................................... 5-12
Fig. 5.2.1 Color register n (M37221ERSS) .............................................................................. 5-13
Fig. 5.2.2 Color register n (M37220M3-XXXSP/FP) ................................................................ 5-14
Fig. 5.2.3 Border selection register (M37220M3-XXXSP/FP) ................................................ 5-14
Fig. 5.3.1 Connection example .................................................................................................. 5-15
Fig. 5.3.2 Correction example (1) ............................................................................................. 5-15
Fig. 5.3.3 Correction example (2) ............................................................................................. 5-16
Fig. 5.3.4 E2PROM map when using ROM correction function (1) ....................................... 5-17
Fig. 5.3.5 E2PROM map when using ROM correction function (2) ....................................... 5-18
Fig. 5.3.6 General flowchart when using ROM correction function ...................................... 5-19
Fig. 5.4.1 Connection example .................................................................................................. 5-21
Fig. 5.4.2 Byte write timing ........................................................................................................ 5-22
Fig. 5.4.3 Random address read timing ................................................................................... 5-22
Fig. 5.4.4 Flowchart of write processing routine ..................................................................... 5-23
Fig. 5.4.5 Flowchart of read processing routine ...................................................................... 5-24
Fig. 5.4.6 Flowchart of data output processing routine .......................................................... 5-25
Fig. 5.5.1 Connection example .................................................................................................. 5-26
Fig. 5.5.2 Staus read timing....................................................................................................... 5-27
Fig. 5.5.3 Byte write timing ........................................................................................................ 5-27
Fig. 5.5.4 Flowchart of write processing routine ..................................................................... 5-28
Fig. 5.5.5 Flowchart of read processing routine ...................................................................... 5-29
Fig. 5.5.6 Flowchart of data output processing routine .......................................................... 5-30
Fig. 5.5.7 Flowchart of START condition processing routine ................................................ 5-31
Fig. 5.5.8 Flowchart of STOP condition processing routine .................................................. 5-31
Fig. 5.5.9 Flowchart of bus H processing routine ................................................................... 5-31
Fig. 5.5.10 Flowchart of data input processing routine .......................................................... 5-32
Fig. 5.5.11 Flowchart of return ACK processing routine ........................................................ 5-33
Fig. 5.5.12 Flowchart of return NACK processing routine ..................................................... 5-33
Fig. 5.5.13 Flowchart of power on processing ........................................................................ 5-36
Fig. 5.5.14 Flowchart of “CH UP/DOWN key” input processing............................................ 5-37
Fig. 5.5.15 Flowchart of “picture memory switching key” input processing ......................... 5-38
Fig. 5.5.16 Status data register ................................................................................................. 5-39
Fig. 5.5.17 Map of write data register ...................................................................................... 5-41
Fig. 5.6.1 Application circuit example 1 (I2C-BUS chassis) ................................................... 5-45
Fig. 5.6.2 Application circuit example 2 (Non-BUS chassis) ................................................. 5-46
CHAPTER 6. APPENDIX
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Initialization of flags in PS ......................................................................................... 6-4
Stack contents after PHP instruction execution ...................................................... 6-4
Note when executing PLP instruction ....................................................................... 6-4
Note in decimal arithmetic operation ........................................................................ 6-5
Execution of BBC or BBS instruction ....................................................................... 6-5
Sequence for switching an external interrupt detection edge ................................ 6-6
Initialization for serial I/O............................................................................................ 6-6
Relation between timer values and their values read
(timer setting value = 2) .............................................................................................. 6-7
Fig. 6.3.9 Relation between timer values and their values read when two timers are
connected in series (timers 1 and 2 are connected, timer 1 setting value = 2,
timer 2 setting value = 1)............................................................................................ 6-7
viii
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
7220 Group User’s Manual
List of figures
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
6.4.1 Wiring for RESET input pin ...................................................................................... 6-11
6.4.2 Wiring for clock I/O pin ............................................................................................. 6-11
6.4.3 Wiring for CNV SS pin ................................................................................................. 6-12
6.4.4 Wiring for V PP pin of One Time PROM and EPROM version .............................. 6-12
6.4.5 Bypass capacitor across V SS line and V CC line ...................................................... 6-13
6.4.6 Analog signal line and resistor and capacitor ....................................................... 6-13
6.4.7 Wiring for large current signal line .......................................................................... 6-14
6.4.8 Wiring for signal line where potential levels charge frequently ........................... 6-14
6.4.9 VSS pattern on underside of an oscillator ............................................................... 6-14
6.4.10 Setup for I/O ports .................................................................................................. 6-15
6.4.11 Watchidog timer by software .................................................................................. 6-16
6.5.1 Memory assignment of M37221M4-XXXSP and M37221M6-XXXSP/FP ............ 6-17
6.5.2 Memory assignment of M37221M8-XXXSP and M37221MA-XXXSP .................. 6-18
6.5.3 Memory assignment of M37220M3-XXXSP/FP ...................................................... 6-19
6.6.1 SFR assignment (including internal state immediately after reset and access
access characteristics) (1) (M37221Mx-XXXSP/FP) .............................................. 6-20
6.6.2 SFR assignment (including internal state immediately after reset and access
access characteristics) (2) (M37221Mx-XXXSP/FP) .............................................. 6-22
6.6.3 Memory map of 2 page register (including internal state immediately after reset and
after reset and access characteristics) (3)
(only M37221M8-XXXSP and M37221MA-XXXSP) ............................................... 6-24
6.6.4 SFR assignment (including internal state immediately after reset and access
after reset and access characteristics) (4) (M37220M3-XXXSP/FP) .................. 6-26
6.6.5 SFR assignment (including internal state immediately after reset and access
after reset and access characteristics) (5) (M37220M3-XXXSP/FP) .................. 6-28
6.7.1 Port Pi direction register ........................................................................................... 6-30
6.7.2 Port P3 direction register .......................................................................................... 6-30
6.7.3 Port P5 direction register .......................................................................................... 6-31
6.7.4 Port P3 output mode control register ...................................................................... 6-31
6.7.5 PWM output control register 1 ................................................................................. 6-32
6.7.6 PWM output control register 2 ................................................................................. 6-32
6.7.7 I 2C data shift register ................................................................................................ 6-33
6.7.8 I2C address register ................................................................................................... 6-33
6.7.9 I2C status register ...................................................................................................... 6-34
6.7.10 I2C control register ................................................................................................... 6-35
6.7.11 I2C clock contorol register ...................................................................................... 6-36
6.7.12 Serial I/O mode register ......................................................................................... 6-37
6.7.13 DA conversion register n (only M37220M3-XXXSP/FP) ..................................... 6-38
6.7.14 Horizontal position register ..................................................................................... 6-38
6.7.15 Vertical position register n ...................................................................................... 6-39
6.7.16 Character size register ............................................................................................ 6-39
6.7.17 Border selection register ......................................................................................... 6-40
6.7.18 Color register n ........................................................................................................ 6-41
6.7.19 CRT control register ................................................................................................ 6-42
6.7.20 CRT port control register ........................................................................................ 6-43
6.7.21 CRT clock selection register .................................................................................. 6-44
6.7.22 CRT A-D control register 1 .................................................................................... 6-45
6.7.23 A-D control register 2 ............................................................................................. 6-45
6.7.24 Timer 12 mode register .......................................................................................... 6-46
6.7.25 Timer 34 mode register .......................................................................................... 6-47
6.7.26 Interrupt input polarity register ............................................................................... 6-47
6.7.27 CPU mode register .................................................................................................. 6-48
7220 Group User’s Manual
ix
List of figures
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
x
6.7.28 Interrupt request register 1 ..................................................................................... 6-48
6.7.29 Interrupt request register 2 ..................................................................................... 6-49
6.7.30 Interrupt control register 1 ...................................................................................... 6-49
6.7.31 Interrupt control register 2 ...................................................................................... 6-50
6.7.32 ROM correction enable register ............................................................................. 6-50
6.8.1 I/O pin block diagram (1) ......................................................................................... 6-51
6.8.2 I/O pin block diagram (2) ......................................................................................... 6-52
7220 Group User’s Manual
List of tables
List of tables
CHAPTER 1. OVERVIEW
Table
Table
Table
Table
1.1.1
1.1.2
1.3.1
1.3.2
Performance overview (1) ........................................................................................ 1-3
Performance overview (2) ........................................................................................ 1-4
Pin description (1) .................................................................................................... 1-7
Pin description (2) .................................................................................................... 1-8
CHAPTER 2. FUNCTIONAL DESCRIPTION
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
2.2.1
2.2.2
2.4.1
2.5.1
2.6.1
2.6.2
2.7.1
2.8.1
2.8.2
2.8.3
2.9.1
Zero page addressing ............................................................................................ 2-10
Special page addressing........................................................................................ 2-10
List of programmable port functions .................................................................... 2-22
Interrupt sources, vector addresses and priority ................................................ 2-26
Memory map of timer-related registers ................................................................ 2-37
Contents of timers 3 and 4 when reset or when executing STP instruction 2-39
Clock source selection ........................................................................................... 2-42
Multi-master I2C-BUS interface functions ............................................................. 2-47
START condition/STOP condition generation timing table ................................ 2-58
START condition/STOP condition detect conditions .......................................... 2-59
Relationship between contents of A-D control register 2 and reference
voltage “Vref” .......................................................................................................... 2-62
2.10.1 PWM function performance (at oscillation frequency = 8 MHz) ..................... 2-63
2.10.2 The relation between D L and t m ( m = “0” to “63”) ............................................. 2-65
2.11.1 Outline of CRT display function.......................................................................... 2-71
2.11.2 Relationship between set value in character size register and character
size ......................................................................................................................... 2-77
2.11.3 Character code table (be omitted partly) .......................................................... 2-79
2.11.4 Contents of CRT display RAM ............................................................................ 2-80
2.11.5 Display example of character background coloring (when green is set for
a character and blue is set for background color) .......................................... 2-83
2.11.6 Relationship between set value of border selection register and character
border function ...................................................................................................... 2-85
2.14.1 State in stop mode ............................................................................................... 2-91
2.14.2 State in wait mode ............................................................................................... 2-93
2.14.3 Invalid interrupts in the wait mode ..................................................................... 2-93
7220 Group User’s Manual
xi
List of tables
CHAPTER 4. M37220M3-XXXSP/FP
Table
Table
Table
Table
Table
Table
4.1.1
4.1.2
4.3.1
4.3.2
4.5.1
4.5.2
Table 4.5.3
Table 4.5.4
Table 4.5.5
Table 4.5.6
Table 4.5.7
Performance overview (1) ........................................................................................ 4-2
Performance overview (2) ........................................................................................ 4-3
Pin description (1) .................................................................................................... 4-6
Pin description (2) .................................................................................................... 4-7
Difference between M37220M3-XXXSP/FP and M37221M6-XXXSP/FP ........... 4-9
Difference of programmable ports between M37221M6-XXXSP/FP and
M37220M3-XXXSP/FP ........................................................................................... 4-14
Interrupt sources, vector addresses and priority ................................................ 4-15
Relationship between contents of D-A conversion register and output voltage “V”
output voltage “V” ................................................................................................... 4-17
Outline of CRT display function ............................................................................ 4-19
Character code table (be omitted partly)............................................................. 4-22
Contents of CRT display RAM .............................................................................. 4-22
CHAPTER 5. APPLICATION
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
5.5.1
5.5.2
5.5.3
5.5.4
Data setting at tuning and searching ................................................................... 5-34
Data setting at “volume UP/DOWN key” input ................................................... 5-34
Data setting at “screen-size-related keys” input ................................................. 5-34
Data setting at “picture data control key” and
“picture memory switching key” input .................................................................. 5-34
5.5.5 Data setting when changing AFT state ............................................................... 5-35
5.5.6 Data setting when changing audio mute state ................................................... 5-35
5.5.7 Data setting when changing video mute state ................................................... 5-35
5.5.8 Data setting when adjusting white balance ......................................................... 5-35
5.5.9 Relationship between DFA and DL TIME ............................................................ 5-42
5.5.10 Setting of color system (at sub-address 0916, write data) .............................. 5-43
CHAPTER 6. APPENDIX
Table 6.2.1 Termination of unused pins ..................................................................................... 6-3
xii
7220 Group User’s Manual
CHAPTER 1
OVERVIEW
1.1
1.2
1.3
1.4
Performance overview
Pin configuration
Pin description
Functional block diagram
OVERVIEW
1.1 Performance overview
1.1 Performance overview
The 8-bit microcomputers:
-M37221M4-XXXSP
-M37221M6-XXXSP/FP
-M37221M8-XXXSP
-M37221MA-XXXSP
-M37220M3-XXXSP/FP
have their simple instruction set; the ROM, RAM, and I/O addresses are placed on the same memory map
to enable easy programming.
Furthermore, they have many additional functions for tuning system for TV:
● PWM output (14-bit and 8-bit)
● CRT display
● A-D comparator (resistance string method)
● Software runaway detection
● Multi-master I 2C-BUS interface function
● ROM correction function
And also, they can allow low power dissipation by the use of CMOS processing.
The M37221M6-XXXSP/FP is used as a general example in describing the functions of the above microcomputers,
unless otherwise noted.
1-2
7220 Group User’s Manual
OVERVIEW
1.1 Performance overview
The performance overview is shown in Table 1.1.1.
M37220M3-XXXSP/FP
Refer to “CHAPTER 4. M37220M3-XXXSP/FP.”
Table 1.1.1 Performance overview (1)
Parameter
Number of basic instructions
Performance
71
0.5 µ s (the minimum instruction execution time, at 8
MHz oscillation frequency)
8 MHz (maximum)
Instruction execution time
Clock frequency
Memory size
ROM
16 K bytes
RAM
320 bytes
ROM
24 K bytes
RAM
384 bytes
M37221M8-XXXSP
ROM
RAM
32 K bytes
512 bytes
M37221MA-XXXSP
ROM
40 K bytes
RAM
640 bytes
M37221M4-XXXSP
M37221M6-XXXSP/FP
8 K bytes
CRT ROM
CRT RAM
Input/Output ports
96 bytes
8-bit ✕ 1 (N-channel open-drain output structure, can be
used as PWM output pins, INT input pins, A-D input pin)
4-bit ✕ 1 (CMOS input/output structure, can be used as
CRT output pin, A-D input pins, INT input pin)
P0 0–P07
I/O
P1 0, P15–P1 7
I/O
P1 1–P14
I/O
4-bit ✕ 1 (CMOS input/output structure, can be used as
multi-master I 2C-BUS interface)
P2 0, P2 1
I/O
2-bit ✕ 1 (CMOS input/output or N-channel open-drain
output structure, can be used as serial I/O pins)
P2 2–P27
I/O
6-bit ✕ 1 (CMOS input/output structure, can be used as
serial input pin, external clock input pins)
P3 0, P3 1
I/O
I/O
2-bit ✕ 1 (CMOS input/output or N-channel open-drain
output structure, can be used as A-D input pins)
1-bit ✕ 1 (N-channel open-drain output structure)
P3 3, P3 4
Input
2-bit ✕ 1 (can be used as CRT display clock I/O pins)
P5 2–P55
Output
4-bit ✕ 1 (CMOS output structure, can be used as CRT
output pins)
P3 2
Serial I/O
Multi-master I 2C-BUS interface
8-bit ✕ 1
A-D comparator
PWM output circuit
6 channels (6-bit resolution)
14-bit ✕ 1, 8-bit ✕ 6
Timers
8-bit timer ✕ 4
ROM correction function (See note)
32 bytes ✕ 2
1 (2 systems)
7220 Group User’s Manual
1-3
OVERVIEW
1.1 Performance overview
Table 1.1.2 Performance overview (2)
Parameter
Subroutine nesting
M37221M4-XXXSP
Performance
96 levels (maximum)
M37221M6-XXXSP/FP
M37221M8-XXXSP
128 levels (maximum)
M37221MA-XXXSP
Interrupt
External interrupt ✕ 3, Internal timer interrupt ✕ 4, Serial
I/O interrupt ✕ 1, CRT interrupt ✕ 1, Multi-master I2CBUS interface interrupt ✕ 1, f(X IN)/4096 interrupt ✕ 1,
V SYNC interrupt ✕ 1, BRK interrupt ✕ 1
Clock generating circuit
2 built-in circuits (externally connected to a ceramic
resonator or a quartz-crystal oscillator)
5 V ± 10 %
Power source voltage
Power dissipation
CRT ON
165 mW typ. (at oscillation frequency f(XIN ) = 8 MHz,
f CRT = 8 MHz)
CRT OFF
110 mW typ. (at oscillation frequency f(XIN) = 8 MHz)
In stop mode
1.65 mW (maximum)
12V withstand ports
6
LED drive ports
4
–10 °C to 70 °C
Operating temperature range
Device structure
M37221M4-XXXSP
Package
CMOS silicon gate process
42-pin shrink plastic molded DIP
M37221M6-XXXSP
M37221M8-XXXSP
M37221MA-XXXSP
M37221M6-XXXFP
CRT display function
42-pin shrink plastic molded SOP
Number of display characters
Dot structure
24 characters ✕ 2 lines (maximum 16 lines by software)
Kinds of characters
256 kinds
Kinds of character sizes
Kinds of character
colors
3 kinds
Maximum 7 kinds (R, G, B); can be specified by the
character
Display position (horizontal, vertical)
64 levels (horizontal) ✕ 128 levels (vertical)
12 ✕ 16 dots
Note: Only M37221M8-XXXSP and M37221MA-XXXSP have the function.
1-4
7220 Group User’s Manual
OVERVIEW
1.2 Pin configuration
1.2 Pin configuration
The pin configurations are shown in Figures 1.2.1 and 1.2.2.
M37220M3-XXXSP/FP
Refer to “CHAPTER 4. M37220M3-XXXSP/FP.”
1
42
P52/R
2
3
41
40
P53/G
P54/B
P01/PWM1
P02/PWM2
4
39
5
6
38
37
P55/OUT1
P20/SCLK
P21/SOUT
P22/SIN
P03/PWM3
P04/PWM4
P05/PWM5
P06/INT2/A-D4
P07/INT1
P23/TIM3
P24/TIM2
P25
P26
P27
D-A
P32
CNVSS
XIN
XOUT
VSS
7
8
9
10
11
12
13
14
15
M37221M4-XXXSP
M37221M6-XXXSP
M37221M8-XXXSP
M37221MA-XXXSP
HSYNC
VSYNC
P00/PWM0
36
35
34
33
32
31
30
29
28
P10/OUT2
P11/SCL1
P12/SCL2
P13/SDA1
P14/SDA2
P15/A-D1/INT3
P16/A-D2
P17/A-D3
16
17
18
19
27
26
25
P30/A-D5
24
20
23
OSC1/P33
OSC2/P34
21
22
VCC
P31/A-D6
RESET
Outline 42P4B
Fig. 1.2.1 Pin configuration (top view) (1)
7220 Group User’s Manual
1-5
OVERVIEW
1.2 Pin configuration
1
42
P52/R
2
3
41
40
P01/PWM1
P02/PWM2
4
39
P53/G
P54/B
P55/OUT1
P03/PWM3
5
6
38
37
P20/SCLK
P21/SOUT
P04/PWM4
P05/PWM5
7
8
36
P22/SIN
P10/OUT2
P06/INT2/A-D4
9
10
P07/INT1
P23/TIM3
P24/TIM2
P25
P26
M37221M6-XXXFP
HSYNC
VSYNC
P00/PWM0
11
12
35
34
33
32
P13/SDA1
P14/SDA2
P27
15
31
30
29
28
D-A
P32
16
17
27
26
P30/A-D5
P31/A-D6
CNVSS
XIN
XOUT
18
19
25
24
RESET
OSC1/P33
20
21
23
22
OSC2/P34
VCC
VSS
13
14
Outline 42P2R-A
Fig. 1.2.2 Pin configuration (top view) (2)
1-6
P11/SCL1
P12/SCL2
7220 Group User’s Manual
P15/A-D1/INT3
P16/A-D2
P17/A-D3
OVERVIEW
1.3 Pin description
1.3 Pin description
The pin description is shown in Table 1.3.1.
M37220M3-XXXSP/FP
Refer to “CHAPTER 4. M37220M3-XXXSP/FP.”
Table 1.3.1 Pin description (1)
Input/
Pin
Name
Functions
Output
Power source
Apply voltage of 5 V ± 10 % (typical) to V CC, and 0 V to V SS.
VCC,
VSS
Connected to V SS.
CNVSS
CNVSS
RESET
Reset input
Input
XIN
Clock input
Input
XOUT
Clock output
P0 0
I/O port P0
______
This chip has an internal clock generating circuit. To control generating
frequency, an external ceramic resonator or a quartz-crystal oscillator
is connected between pins XIN and X OUT. If an external clock is used,
Output the clock source should be connected to the XIN pin and the X OUT pin
should be left open.
I/O
PWM0–
P0 5/
PWM5,
P 0 6 / I N T 2 / PWM output
A-D4,
External
P0 7/INT1
P1 1/SCL1,
P1 2/SCL2, CRT output
P1 3/SDA1,
Input
Input
I/O
Pins P0 6 , P0 7 are also used as external interrupt input pins INT2,
INT1 respectively.
P0 6 pin is also used as analog input pin A-D4.
Port P1 is an 8-bit I/O port and has basically the same functions as
port P0. The output structure is CMOS output.
Output Pins P1 0 is also used as CRT output pin OUT2. The output structure
is CMOS output.
I/O
Pins P11–P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively,
when multi-master I2C-BUS interface is used. The output structure is
N-channel open-drain output.
Analog input
Input
Pins P1 5 –P1 7 are also used as analog input pins A-D1 to A-D3
respectively.
External
Input
P1 5 pin is also used as external interrupt input pin INT3.
P1 4/SDA2, Multi-master
P1 5/A-D1/ I2C-BUS
interface
INT3,
P1 6/A-D2,
P1 7/A-D3
Port P0 is an 8-bit I/O port with direction register allowing each I/O bit
to be individually programmed as input or output. At reset, this port is
set to input mode. The output structure is N-channel open-drain output.
Output Pins P0 0 –P0 5 are also used as PWM output pins PWM0–PWM5
respectively. The output structure is N-channel open-drain output.
interrupt input
Analog input
P1 0/OUT2, I/O port P1
To enter the reset state, the reset input pin must be kept at a “L” for
2 µ s or more (under normal V CC conditions).
If more time is needed for the quartz-crystal oscillator to stabilize, this
“L” condition should be maintained for the required time.
interrupt input
7220 Group User’s Manual
1-7
OVERVIEW
1.3 Pin description
Table 1.3.2 Pin description (2)
Input/
Pin
Name
Functions
Output
I/O port P2
I/O
P2 0/S CLK,
Port P2 is an 8-bit I/O port and has basically the same functions as
port P0. The output structure is CMOS output.
P2 1/S OUT,
P2 3/TIM3,
External clock
input
P2 4/TIM2,
Serial I/O
P2 5–P27
synchronous
P2 2/S IN,
Input
Pins P2 3, P24 are also used as external clock input pins TIM3, TIM2
respectively.
I/O
P20 pin is also used as serial I/O synchronous clock input/output pin
SCLK. The output structure is N-channel open-drain output.
I/O
Pins P2 1, P2 2 are also used as serial I/O data input/output pins SOUT,
SIN respectively. The output structure is N-channel open-drain output.
Ports P30–P32 are 3-bit I/O ports and have basically the same functions
as port P0. Either CMOS output or N-channel open-drain output structure
can be selected as the port P3 0 and P31. The output structure of port
P32 is N-channel open-drain output.
clock input/
output
Serial I/O data
input/output
P3 0 /A-D5/ I/O port P3
DA1,
I/O
P3 1 /A-D6/
DA2, P3 2
Analog input
P3 3/OSC1, Input port P3
P3 4/OSC2 Clock input for
CRT display
Input
Input
Pins P30, P31 are also used as analog input pins A-D5, A-D6 respectively.
Input
P3 3 pin is also used as CRT display clock input pin OSC1.
Ports P3 3, P3 4 are 2-bit input ports.
Clock output for Output P3 4 pin is also used as CRT display clock output pin OSC2. The
output structure is CMOS output.
CRT display
P5 3/G,
Output port P5 Output Ports P5 2–P55 are 4-bit output ports. The output structure is CMOS
output.
P5 4/B,
CRT output
P5 2/R,
P5 5/OUT1
Output Pins P5 2 –P5 5 are also used as CRT output pins R, G, B, OUT1
respectively. The output structure is CMOS output.
H SYNC
H SYNC input
Input
This is a horizontal synchronous signal input for CRT.
VSYNC
D-A
VSYNC input
Input
This is a vertical synchronous signal input for CRT.
1-8
DA output
Output This is a 14-bit PWM output pin. The output structure is CMOS output.
7220 Group User’s Manual
28 29 30 31 32 33 34 35
15 14 13 12 11 36 37 38
14-bit
PWM circuit
16
D-A
17 26 27
P3 (3)
18
CNVSS
Stack
pointer
S (8)
ROM
21
VSS
TIM2
Fig. 1.4.1 Functional block diagram
Timer 4
T4 (8)
Timer 3
T3 (8)
Timer 2
T2 (8)
Timer 1
T1 (8)
Timer count source
selection circuit
Multi-master
I 2 C-BUS
interface
TIM3
I/O port P0
I/O port P1
I/O port P2
I/O ports P3 0–P32
Note : Only M38221M8-XXXSP and M37221MA-XXXSP have the function.
10 9 8 7 6 5 4 3
P2 (8)
22
VCC
Index
register
Y (8)
PCL (8)
PCH (8)
Index
register
X (8)
Program
counter
Program
counter
A-D
comparator
P1 (8)
Accumulator
A (8)
Processor
status
register
PS (8)
P0 (8)
8-bit
arithmetic
and
logical unit
Address bus
RAM
Data bus
INT3
Clock
generating
circuit
25
INT2
INT1
20
8-bit PWM circuit
SI/O(8)
Instruction
register (8)
Instruction
decoder
Control signal
SIN
SCLK
SOUT
19
23
(See note)
ROM
correction
function
P5 (4)
39 40 4142
2 1
Output ports P5 2–P55
CRT circuit
24
OUT2
Input ports P3 3, P34
Clock input for display Clock output for display
OSC1 OSC2
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
7220 Group User’s Manual
OUT1
B
G
R
Reset input
RESET
VSYNC
HSYNC
Clock input Clock output
XIN XOUT
OVERVIEW
1.4 Functional block diagram
1.4 Functional block diagram
The functional block diagram is shown in Figure 1.4.1.
M37220M3-XXXSP/FP
Refer to “CHAPTER 4. M37220M3-XXXSP/FP.”
1-9
CHAPTER 2
FUNCTIONAL
DESCRIPTION
2.1 Central processing unit
2.2 Access area
2.3 Memory assignment
2.4 Input/Output pins
2.5 Interrupts
2.6 Timers
2.7 Serial I/O
2.8 Multi-master I 2C-BUS interface
2.9 A-D comparator
2.10 PWM
2.11 CRT display function
2.12 ROM correction function
2.13 Software runaway detect function
2.14 Low-power dissipation mode
2.15 Reset
2.16 Clock generating circuit
2.17 Oscillation circuit
FUNCTIONAL DESCRIPTION
2.1 Central processing unit
2.1 Central processing unit
The CPU of the M37221M6-XXXSP/FP has six main registers.
The program counter (PC) is a 16-bit register consists of PC H and PCL, both of which are 8-bit registers.
The other five registers: the accumulator (A), index register X (X), index register Y (Y), stack pointer (S) and
processor status register (PS), all have an 8-bit configuration.
Note: The contents of registers above except the following are indeterminate after a hardware reset. Therefore,
initialize these registers by software.
• The Interrupt disable flag I of the processor status register = “1”
• The program counter = the contents of addresses FFFE16 and FFFF 16
Figure 2.1.1 shows the registers configuration diagram of M37221M6-XXXSP/FP.
7
0
A
7
Accumulator (A)
0
X
7
Index Register X (X)
0
Y
7
Index Register Y (Y)
0
S
7
0
7
Stack Pointer (S)
0
PCL
PCH
7
Program Counter (PC)
0
N V T B D I Z C
Processor Status Register (PS)
Carry Flag
Zero Flag
Interrupt Disable Flag
Decimal Operation Mode Flag
Break Flag
X Modified Operation Mode Flag
Overflow Flag
Negative Flag
Fig. 2.1.1 Registers configuration diagram
2.1.1 Accumulator (A)
The accumulator is the central register of the microcomputer and 8-bit register.
This general-purpose register is used with considerable for arithmetic operations, data transfer, temporary
clearing, condition judgments, etc.
2.1.2 Index register X (X), index register Y (Y)
The M37221M6-XXXSP/FP has the index register X and the index register Y, both of which are 8-bit
registers.
In the addressing modes which use these index registers, the register contents are added to the specified
address and this becomes the actual address. These modes are used for referencing subroutine tables and
memory tables.
The index registers, which have increment, decrement, comparison and data transfer functions, are also
used as simple accumulators.
2-2
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.1 Central processing unit
2.1.3 Stack pointer (S)
The stack pointer is an 8-bit register used for interrupts and subroutine calls.
The stack area can be assigned into the internal RAM.
The internal RAM of M37221M6-XXXSP/FP is assigned in the zero page and the page 1. The both area
can use for the stack area. The stack area is specified with the CPU mode register (address 00FB16). At
reset, the stack area is specified to the page 1 automatically.
Note: Storing data in the stack area fills the RAM area with stored data in order, therefore make sure the
depth of interrupt levels and the subroutine nesting.
The stack area and stack pointer (S) should be specified in the initialization of software. When the stack
area is specified to “1,” even if the value of stack pointer is over “0016” (stack address is 010016), the stack
area value never change to “0” automatically. Therefore in this case, change the stack area value by
software.
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1 1 1 1 1
0 0
CPU mode register (CPUM) (CM) [Address 00FB16]
B
Name
0, 1 Fix these bits to “0.”
2
Stack page selection
bit (CM2)
Functions
0: 0 page
1: 1 page
(Note)
3 Fix these bits to “1.”
to
5
After reset
R W
0
R W
1
R W
1
R W
Indeterminate R W
6, 7
Note: This bit is set to “1” after reset release.
Fig. 2.1.2 CPU mode register
With the stack pointer during a interrupt or subroutine call, the processing is performed automatically in the
following sequence (refer to “Figure 2.1.3”).
➀ The contents of high-order 8 bits of the program counter (PCH) are stored at an address indicated as
below:
• The high-order 8 bits are the stack area value (“00 16” or “0116”).
• The low-order 8 bits are the stack pointer contents.
➁ The stack pointer contents are decremented by 1.
➂ The contents of low-order 8 bits of the program counter (PCL) are stored at an address indicated as
below:
• The high-order 8 bits are the stack area value (“00 16” or “0116”).
• The low-order 8 bits are the stack pointer contents.
➃ The stack pointer contents are decremented by 1.
➄ The contents of the processor status register (PS) are stored at an address indicated as below:
• The high-order 8 bits are the stack area value (“00 16” or “0116”).
• The low-order 8 bits are the stack pointer contents.
➅ The stack pointer contents are decremented by 1.
7220 Group User’s Manual
2-3
FUNCTIONAL DESCRIPTION
2.1 Central processing unit
Storing of the processor status register in items ➄ and ➅ above is not performed during a subroutine call.
Execute the PHP instruction in a program to push the processor status register onto a stack.
To prevent data from losing during interrupts and subroutine calls, push the other registers onto a stack
by software as described above.
For example, execute the PHA instruction to push the accumulator contents onto a stack. Executing the
PHA instruction stores the accumulator contents at an address indicated as below:
• The high-order 8 bits are the stack area value (“00 16” or “0116”).
• The low-order 8 bits are the stack pointer contents.
The stack pointer contents are then decremented by 1.
Execute the RTI instruction to return from an interrupt routine.
When the RTI instruction is executed, the processing is performed automatically in the following sequence
(refer to “Figure 2.1.3”).
➀ The stack pointer contents are incremented by 1.
➁ The contents at the address indicated as below are restored to the processor status register.
• The high-order 8 bits are the stack area value (“00 16” or “0116”).
• The low-order 8 bits are the stack pointer contents.
➂ The stack pointer contents are incremented by 1.
➃ The contents at the address indicated as below are restored to low-order 8 bits of the program counter
(PCL).
• The high-order 8 bits are the stack area value (“00 16” or “0116”).
• The low-order 8 bits are the stack pointer contents.
➄ The stack pointer contents are incremented by 1.
➅ The contents at the address indicated as below are restored to high-order 8 bits of the program counter
(PCH).
• The high-order 8 bits are the stack area value (“00 16” or “0116”).
• The low-order 8 bits are the stack pointer contents.
Restoring of the processor status register in items ➀ and ➁ above is not performed in this case. Execute
the RTS instruction to return from a subroutine.
Execute the PLP instruction and PLA instruction to restore the processor status register and the accumulator,
respectively.
Executing the PLP (PLA) instruction increments the stack pointer by 1 and restores the contents at the
address indicated as below to the processor status register.
• The high-order 8 bits are the stack area value (“00 16” or “0116”).
• The low-order 8 bits are the stack pointer.
2-4
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.1 Central processing unit
On-going routine
••••••••
Interrupt request
Execute JSR
M(S)
(PCH)
(S)
(S)–1
M(S)
(PCL)
(S)
(S)–1
M(S)
M(S)
(PCH)
(S)
(S)–1
M(S)
(PCL)
(S)
(S)–1
(PS)
(S)
(S)–1
••••••••
Interrupt routine
•
•
•
Execute RTI
Subroutine
(S)
•
•
•
(PS)
Execute RTS
(S)
(PCL)
(S)+1
(S)
M(S)
(PCL)
(S)
(S)+1
(S)
(PCH)
M(S)
(PCH)
(S)+1
M(S)
(S)+1
M(S)
(S)+1
M(S)
(PCH) : Contents of high-order 8 bits of program counter
(PCL) : Contents of low-order 8 bits of program counter
(PS) : Contents of processor status register
(S)
: Contents of stack pointer
M
: Memory
RTI : Instruction for returning from interrupt routine to main routine
RTS : Instruction for returning from subroutine to main routine
Fig. 2.1.3 Sequence of push onto/pop from a stack during interrupts and subroutine calls
7220 Group User’s Manual
2-5
FUNCTIONAL DESCRIPTION
2.1 Central processing unit
2.1.4 Program counter (PC)
The program counter is a 16-bit counter consists of PC H and PC L, both of which are 8-bit registers.
The program counter indicates the address of the program to be executed next.
The M37221M6-XXXSP/FP uses the stored program system. To start a new operation, transfer the instruction
and the data, from the memory to the CPU. Ordinary, the program counter is controlled to indicate the
memory address to be sent next. After each instruction is executed, the instruction required next is called
out and this cycle is repeated until finished.
Note: The program counter of the M37221M6-XXXSP/FP is controlled automatically; however, make sure
to avoid differences between program flow and the program counter contents when operating the
stack pointer or directly changing the program counter contents.
2.1.5 Processor status register (PS)
The processor status register is an 8-bit register. It consists of 5 flags, which indicate the state after
arithmetic operations related to the internal CPU, and 3 flags which determine operation.
The following explains each of these flags. Refer to “6.9 Machine instruction table” of this USER’S
MANUAL or “SERIES 740 <SOFTWARE> USER’S MANUAL” concerning the change of these flags.
(1) Carry flag (C) ...................................................... Bit 0
This flag stores any carry or borrow from the ALU after an arithmetic operation and is also changed
by the Shift instruction or Rotate instruction.
This flag is set to “1” by using the SEC instruction and is cleared to “0” by using the CLC instruction.
(2) Zero flag (Z) ........................................................ Bit 1
This flag is set to “1” when the result of an arithmetic operation or a data transfer is “0” and is cleared
to “0” by any other result.
This flag has no meaning in the decimal mode.
(3) Interrupt disable flag (I) ................................... Bit 2
This flag disables interrupts. When this flag is “1,” all interrupts except the BRK interrupt and reset
are disabled. This flag immediately becomes “1” when an interrupt is received. This flag is set to “1”
by using the SEI instruction and is cleared to “0” by using the CLI instruction.
(4) Decimal operation mode flag (D) ................... Bit 3
This flag determines whether addition and substruction are performed in binary or decimal notation.
Binary arithmetic is performed when this flag is “0” and decimal arithmetic is performed with treating
each word as a 2-digit decimal when this flag is “1.” Decimal adjust is performed automatically at this
time. This flag is set to “1” by using the SED instruction and is cleared to “0” by using the CLD
instruction. Only the ADC and SBC instructions are used for decimal arithmetic.
Since this flag directly affects calculations, always initialize it after a reset.
(5) Break flag (B) ...................................................... Bit 4
This flag determines whether or not an interrupt occurred by using the BRK instruction. When a BRK
instruction interrupt occurs, the flag B is set to “1”; for all other interrupts the flag is set to “0” and
pushed to the stack.
For the M37221M6-XXXSP/FP, interrupt vectors by using the BRK instruction are independent of
other interrupts, and it is possible to determine the cause of interrupt by jumping to the vector
address inherent to each interrupt. Therefore, it is not specifically necessary to refer to this flag.
Note: The BRK instruction will be used for debugging.
2-6
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.1 Central processing unit
7
S
S+1
S+2
S+3
4
0 Bit
=B Flag
PS (processor status register)
1
PCL (low-order of program counter)
PCH (high-order of program counter)
Fig. 2.1.4 Contents of stack after execution of BRK instruction
(6) X modified operation mode flag (T) .............. Bit 5
This flag determines whether arithmetic operations are performed via the accumulator or directly
between memories. When the flag is set to “0”, arithmetic operations are performed between the
accumulator and memory. When “1,” arithmetic operations are performed directly between memories.
This flag is set to “1” with the SET instruction and is cleared to “0” with the CLT instruction.
Since this flag directly affects calculations, always initialize it after a reset.
■ When the T flag = “0”
A←A ✽ M
✽ : indicates an arithmetic operation
A : accumulator contents
M: contents of the memory specified by the addressing of the arithmetic operation
■ When the T flag = “1”
M1←M1 ✽ M2
✽ : indicates arithmetic operation
M1: contents of memory specified directly with index register X
M2: contents of the memory specified by the addressing of the arithmetic operation
(7) Overflow flag V ................................................... Bit 6
This flag is set to “1” when an overflow occurs in the result of an arithmetic operation involving signs.
An overflow occurs when the result of an addition or subtraction exceeds +127 (7F16) or –128 (8016).
The CLV instruction clears the overflow flag to “0.” There is no instruction for setting this flag to “1.”
When the BIT instruction is executed except the above, bit 6 of the memory executed by the BIT
instruction is set to the overflow flag.
This flag has no meaning in decimal mode.
Note: Overflows do not occur when the result of an addition or subtraction is smaller than the above
numerical values or an addition is performed between different signs.
(8) Negative flag (N) ......................................................... Bit 7
This flag is set to “1” when the result of a data transfer or arithmetic operation is negative (bit 7 is
“1”). When the BIT instruction is executed, bit 7 of the memory executed by the BIT instruction is
set to the negative flag. This flag can be used to determine whether the results of arithmetic operations
are positive or negative, and also to perform a simple bit test. There are no instructions for directly
setting or clearing this flag.
This flag has no meaning in decimal mode.
7220 Group User’s Manual
2-7
FUNCTIONAL DESCRIPTION
2.2 Access area
2.2 Access area
The ROM, RAM and various I/O control registers are assigned within the same memory area. Therefore, the
same instructions are used for data transfers and arithmetic operations without making any distinction
between memory and I/O.
Since the program counter is a 16-bit register, 64 K-byte memory area can be accessed: from addresses
as 0000 16 to FFFF16.
The first 256 bytes of the 64 K-byte memory area are called the “zero page” and the last 256 bytes are
called the “special page.” These areas can be accessed with only 2 bytes by using each special addressing
mode.
M37220M3-XXXSP/FP
Refer to “CHAPTER 4. M37220M3-XXXSP/FP.”
000016
Internal RAM
RAM
(384 bytes)
for
M37221M6
RAM
(320 bytes)
for
M37221M4
00C0 16
SFR area
00FF16
(Refer to Figures 2. 3. 3 and 2. 3. 4)
CRT display ROM
(8 K bytes)
10000 16
ROM
for display
Zero page
Special function register
11FFF 16
Internal RAM
017F16
01BF 16
Not used
CRT display RAM
(96 bytes)
(See note)
060016
06B716
RAM
for display
Not used
Not used
A00016
C000 16
: Internal ROM area for
program counter
ROM
(24 K bytes)
for
M37221M6
Internal ROM
ROM
(16 K bytes)
for
M37221M4
FF0016
FFDE16
FFFF16
Interrupt vector area
Special page
1FFFF 16
Note: Refer to Table 2.11.4 Contents of CRT display RAM.
Fig. 2.2.1 Access area of M37221M4-XXXSP and M37221M6-XXXSP/FP
2-8
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.2 Access area
10000 16
000016
Internal RAM
Zero page
RAM
(640 bytes)
for
M37221MA
RAM
(512 bytes)
for
M37221M8
00C016
SFR area
00FF16
(Refer to Figures 2. 3. 3 to 2. 3. 5)
Special function register
01FF16
ROM
for display
CRT display ROM
(8 K bytes)
Internal RAM
11FFF16
Not used
021716
021B16
2 page register
Not used
02C016
02FF16
030016
033F16
ROM correction
memory (RAM)
ROM correction memory
Block 1: addresses 02C0 16 to 02DF 16
Block 2: addresses 02E0 16 to 02FF 16
Internal RAM
03BF16
CRT display RAM
(96 bytes)
(See note)
060016
06B716
Not used
Not used
600016
800016
ROM
(40 K bytes)
for
M37221MA
ROM
(32 K bytes)
for
M37221M8
Not used
RAM
for display
: Internal ROM area for
program counter
Internal ROM
FF0016
FFDE16
Interrupt vector area
FFFF16
Special page
1FFFF 16
Note: Refer to Table 2.11.4 Contents of CRT display RAM.
Fig. 2.2.2 Access area of M37221M8-XXXSP and M37221MA-XXXSP
7220 Group User’s Manual
2-9
FUNCTIONAL DESCRIPTION
2.2 Access area
2.2.1 Zero page (addresses 0000 16 to 00FF16)
The 256 bytes from address 000016 to address 00FF16
are called “zero page”.
The internal RAM, I/O ports, timer, serial I/O, A-D
comparison, PWM output, CRT display and interrupt
related registers all present within this area.
These registers were called “special function registers”
in distinction from the accumulator, index registers
and so on in the CPU.
The addressing modes as shown in Table 2.2.1 are
used to specify memory (RAM) and special function
registers in the zero page area.
Those modes dedicated to the zero page area are
marked with a symbol (✽).
This area can be accessed with shorter instructions
by using these modes.
Table 2.2.1 Zero page addressing
Bytes required
Addressing mode
✽ Zero page
2
✽ Zero page Indirect
2
✽ Zero page X
✽ Zero page Y
2
✽ Zero page Bit
2
✽ Zero page Bit Relative
Absolute
3
3
Absolute X
3
Absolute Y
Relative
3
Indirect
3
Indirect X
2
2
Indirect Y
2.2.2 Special page (addresses FF0016 to FFFF16)
The 256 bytes from address FF0016 to address FFFF16
within the internal ROM are called “special page
area”.
The addressing modes as shown in Table 2.2.2 are
used to specify memory in the special page area.
Those modes dedicated to the special page area
are marked with a symbol (✽).
This area can be accessed with shorter instructions
by using these modes.
Subroutines used with considerable frequency are
ordinary assigned in this area.
2-10
2
2
Table 2.2.2 Special page addressing
Bytes required
Addressing mode
✽ Special page
2
Absolute
3
Absolute X
Absolute Y
3
Relative
Indirect
2
3
Indirect X
2
Indirect Y
2
7220 Group User’s Manual
3
FUNCTIONAL DESCRIPTION
2.3 Memory assignment
2.3 Memory assignment
Figures 2.3.1 and 2.3.2 show the memory assignment. The ROM, RAM and I/O assigned in this memory
area are described below.
M37220M3-XXXSP/FP
Refer to “CHAPTER 4. M37220M3-XXXSP/FP.”
Hexadecimal notation
0000 16
Decimal notation
0
Internal RAM
RAM
(384 bytes)
for
M37221M6
RAM
(320 bytes)
for
M37221M4
00C0 16
00FF16
0100 16
SFR area
CRT display ROM
(8 K bytes)
Special function register
(Refer to Figures 2. 3. 3 and 2. 3. 4)
ROM
for display
Zero page
192
65536
10000 16
73727
11FFF16
255
Internal RAM
383
447
017F16
01BF 16
Not used
CRT display RAM
(96 bytes)
(See note)
0600 16
06B716
RAM
for display
1536
1719
Not used
Not used
A00016
40960
C000 16
49152
Internal ROM
ROM
(24 K bytes)
for
M37221M6
ROM
(16 K bytes)
for
M37221M4
65280
65502
FF0016
Interrupt vector area
FFFF 16
Special page
65535
1FFFF 16
131071
Note: Refer to Table 2.11.4 Contents of CRT display RAM.
Fig. 2.3.1 Memory assignment of M37221M4-XXXSP and M37221M6-XXXSP/FP
7220 Group User’s Manual
2-11
FUNCTIONAL DESCRIPTION
2.3 Memory assignment
Decimal notation
Hexadecimal notation
0
000016
Internal RAM
1000016
65536
Zero page
RAM
(640 bytes)
for
M37221MA
RAM
(512 bytes)
for
M37221M8
00C0 16
Special function register
00FF16
010016
01FF16
021716
021B16
02C0 16
02FF16
030016
CRT display RAM
(96 bytes)
(See note)
192
SFR area
(Refer to Figures 2. 3. 3 to 2. 3. 5)
Internal RAM
255
511
2 page register
73727
535
540
Not used
ROM correction
memory (RAM)
Internal RAM
704
767
768
831
03BF 16
959
06B716
11FFF16
Not used
033F16
060016
ROM
for display
CRT display ROM
(8 K bytes)
Not used
RAM
for display
ROM correction memory
Block 1: addresses 02C0 16 to 02DF 16
Block 2: addresses 02E0 16 to 02FF 16
Not used
1536
1719
Not used
24576
32768
600016
800016
ROM
(40 K bytes)
for
M37221MA
ROM
(32 K bytes)
for
M37221M8
Internal ROM
FF0016
FFDE16 Interrupt vector area
FFFF16
65280
65502
Special page
1FFFF 16
65535
Note: Refer to Table 2.11.4 Contents of CRT display RAM.
Fig. 2.3.2 Memory assignment of M37221M8-XXXSP and M37221MA-XXXSP
2-12
7220 Group User’s Manual
131071
FUNCTIONAL DESCRIPTION
2.3 Memory assignment
■SFR Area (addresses C016 to DF16)
< Bit allocation >
0 : “0” immediately after reset
:
Name
< State immediately after reset >
Function bit
:
1 : “1” immediately after reset
: No function bit
? : Indeterminate immediately
after reset
0 : Fix this bit to “0”
(do not write “1”)
Address
Register
1 : Fix this bit to “1”
(do not write “0”)
Bit allocation
State immediately after reset
b0 b7
b7
C016
C116
C216
C316
C416
C516
C616
C716
C816
C916
CA16
CB16
CC16
CD16
CE16
CF16
D016
D116
D216
D316
D416
D516
D616
D716
D816
D916
DA16
DB16
DC16
DD16
DE16
DF16
b0
Port P0 (P0)
Port P0 direction register (D0)
Port P1 (P1)
Port P1 direction register (D1)
Port P2 (P2)
Port P2 direction register (D2)
Port P3 (P3)
0
0
0
0
0
?
0
0
?
0
0
0
Port P3 direction register (D3)
Port P5 (P5)
Port P5 direction register (D5)
Port P3 output mode control register (P3S)
0
0
P31S P30S
DA-H register (DA-H)
DA-L register (DA-L)
PWM0 register (PWM0)
PWM1 register (PWM1)
PWM2 register (PWM2)
PWM3 register (PWM3)
PWM4 register (PWM4)
PWM output control register 1 (PW)
PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0
PWM output control register 2 (PN)
I2 C data shift register (S0)
I2 C address register (S0D)
PN4 PN3 PN2
D7
D6
D5
D4
D3
D2
D1
D0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
I2 C status register (S1)
MST TRX BB
I2 C
BSEL1 BSEL0 10 BIT ALS ES0 BC2 BC1 BC0
SAD
ACK FAST
ACK BIT
CCR4 CCR3 CCR2 CCR1 CCR0
MODE
control register (S1D)
I2 C clock control register (S2)
Serial I/O mode register (SM)
Serial I/O register (SIO)
SM6 SM5
PIN
0
AL AAS AD0 LRB
SM3 SM2 SM1 SM0
0016
0016
?
0016
?
0016
?
0016
? ?
0016
?
?
? ?
0016
?
0016
?
? ?
?
?
?
?
?
0016
0016
?
0016
1 0
0016
0016
0016
?
0016
0016
?
?
?
?
?
?
?
?
?
0
0
?
Fig. 2.3.3 Memory map of SFR (special function register) (1)
7220 Group User’s Manual
2-13
FUNCTIONAL DESCRIPTION
2.3 Memory assignment
■SFR Area (addresses E016 to FF16)
< Bit allocation >
0 : “0” immediately after reset
:
Name
< State immediately after reset >
Function bit
:
1 : “1” immediately after reset
: No function bit
? : Indeterminate immediately
after reset
0 : Fix this bit to “0”
(do not write “1”)
1 : Fix this bit to “1”
(do not write “0”)
Address
E016
E116
E216
E316
E416
E516
E616
E716
E816
E916
EA16
EB16
EC16
ED16
EE16
EF16
F016
F116
F216
F316
F416
F516
F616
F716
F816
F916
FA16
FB16
FC16
FD16
FE16
FF16
Register
Bit allocation
State immediately after reset
b0 b7
b7
Horizontal position register (HR)
Vertical position register 1 (CV1)
CV16 CV15 CV14 CV13 CV12 CV11 CV10
Vertical position register 2 (CV2)
CV26 CV25 CV24 CV23 CV22 CV21 CV20
Character size register (CS)
Border selection register (MD)
Color register 0 (CO0)
CO07 CO06 CO05 CO04
CO03 CO02 CO01
Color register 1 (CO1)
CO17 CO16 CO15 CO14
CO13 CO12 CO11
Color register 2 (CO2)
CO27 CO26 CO25 CO24
CO23 CO22 CO21
Color register 3 (CO3)
CRT control register (CC)
CO37 CO36 CO35 CO34
CO33 CO32 CO31
CC7
CRT port control register (CRTP)
OP7 OP6 OP5 OUT1 OUT2 R/G/B VSYC HSYC
CRT clock selection register (CK)
CS21 CS20 CS11 CS10
MD20
0
MD10
0
0
?
?
?
?
0
0
0
0
0
0
0
0
0
0
0
0
?
?
1
CC2 CC1 CC0
0
A-D control register 1 (AD1)
A-D control register 2 (AD2)
Timer 1 (TM1)
0
0
0
ADM4
0
CK1 CK0
ADM2 ADM1 ADM0
ADC5 ADC4 ADC3 ADC2 ADC1 ADC0
Timer 2 (TM2)
Timer 3 (TM3)
Timer 4 (TM4)
Timer 12 mode register (T12M)
0
Timer 34 mode register (T34M)
T12M4 T12M3 T12M2 T12M1 T12M0
T34M5 T34M4 T34M3 T34M2 T34M1 T34M0
PWM5 register (PWM5)
Interrupt input polarity register (RE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
0
1
IT3R
RE5 RE4
CK0 RE3
1
1
0
0
0
CM2
0
0
IICR VSCR CRTR TM4R TM3R TM2R TM1R
0
IT3E
0016
1 1
S1R 1T2R 1T1R
MSR
CK0
IICE VSCE CRTE TM4E TM3E TM2E TM1E
0
0
MSE
0
S1E 1T2E 1T1E
Fig. 2.3.4 Memory map of SFR (special function register) (2)
2-14
b0
HR5 HR4 HR3 HR2 HR1 HR0
7220 Group User’s Manual
0016
? ?
? ?
?
0 ?
0 0
0016
0016
0016
0016
0016
?
0016
0016
? 0
0016
FF16
0716
FF16
0716
0016
0016
?
?
?
0 0
0016
1 1
0016
0016
0016
0016
?
?
?
?
?
?
?
?
?
0
?
?
0
0
0
0
0
?
1
0
0
FUNCTIONAL DESCRIPTION
2.3 Memory assignment
■2 Page Register Area (addresses 21716 to 21B16)
< Bit allocation >
< State immediately after reset >
0 : “0” immediately after reset
:
Function bit
Name
:
1 : “1” immediately after reset
: No function bit
? : Indeterminate immediately
after reset
0 : Fix this bit to “0”
(do not write “1”)
Address
21716
21816
21916
21A16
21B16
Register
1 : Fix this bit to “1”
(do not write “0”)
Bit allocation
State immediately after reset
b0 b7
b7
ROM correction address 1 (high-order)
ADH17 ADH16 ADH15 ADH14 ADH13 ADH12 ADH11 ADH10
ROM correction address 1 (low-order)
ADL17 ADL16 ADL15 ADL14 ADL13 ADL12 ADL11 ADL10
ROM correction address 2 (high-order)
ADH27 ADH26 ADH25 ADH24 ADH23 ADH22 ADH21 ADH20
ROM correction address 2 (low-order)
ROM correction enable register (RCR)
ADL27 ADL26 ADL25 ADL24 ADL23 ADL22 ADL21 ADL20
0
0
RCR1 RCR0
b0
?
?
?
?
0016
Note: Only M37221M8-XXXSP and M37221MA-XXXSP have this area.
Fig. 2.3.5 Memory map of 2 page register (only M37221M8-XXXSP and M37221MA-XXXSP)
7220 Group User’s Manual
2-15
FUNCTIONAL DESCRIPTION
2.3 Memory assignment
2.3.1 Internal RAM
The static RAM is assigned.
The internal RAM is used as a stack area for subroutine calls and interrupts as well as for storing data.
Both zero page and page 1 are used as a stack area. At reset, the page 1 is specified automatically.
Ordinary, the stack pointer is set to the highest address in the internal RAM of the page 1 during initialization
immediately after power on.
This stack pointer moves to lower addresses as the nesting depth increases; therefore, make sure the
subroutine nesting and interrupt levels to prevent the stored data destroying necessary data in the RAM.
When the stack page is specified “1,” if the value of stack pointer exceeds address 0100 16, the value of
stack page never change to “0” automatically. In this case, set the stack page value to “0” and set the stack
pointer value to the highest address by software.
2.3.2 I/O ports (addresses 00C0 16 to 00CD 16)
Addresses 00C016 to 00CD16 are assigned to the ports, port direction registers and the port P3 output mode
control register. There are 5 ports: P0, P1, P2, P3 and P5. Ports P0, P1 and P2 are the 8-bit programmable
I/O ports. Port P3 consists of 5 bits. The low-order 3 bits (P30–P3 2) are the programmable I/O ports, and
the high-order 2 bits (P33 and P3 4) are the input ports.
For I/O ports P0, P1, P2 and P3 0–P32, input or output can be specified in bit units by setting the relevant
values to each port direction register.
To specify port bits as output pins, write “1” to the corresponding bit of the port direction register.
Conversely, write “0” to the corresponding bit to specify as an input pin.
For example, to use the even numbered bits of port P2 as output ports and the odd numbered bits as input
ports, write “55 16 (01010101 2)” to address 00C5 16 (the port P2 direction register) at initialization.
Although Port P5 is an output port, it can be specified as the CRT output pins (R, G, B, OUT1) or as
general-purpose port (P52–P5 5) by setting each bit in the port P5 direction register.
When setting “0,” it is used for the CRT output pins (R, G, B, OUT1), and when setting “1,” it is used as
general-purpose output ports (P52–P55).
Note: Each port direction register default is “input” (port P5 is “CRT output”) immediately after reset
release.
Write “5516” to port P2 direction register
00C416
Port P2
00C516
Port P2 direction register
Port P2 direction register
0 1 0 1 0 1 0 1
7
6
5
4
3
2
1
0 Bit
Input
Output
Input
Output
Input
Output
Input
Output
Port P2
7
6
5
4
3
2
1
0 Bit
Fig. 2.3.6 I/O setting example of port
2-16
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.3 Memory assignment
2.3.3 DA registers (addresses 00CE 16 and 00CF 16)
The DA-H register is assigned to address 00CE16 , and the DA-L register is assigned to address 00CF 16.
Both registers consist of 8 bits.
The DA-H register is used to set the high-order 8 bits of 14-bit PWM output data. The DA-L register is used
to set the low-order 6 bits of 14-bit PWM output data (set to bits 0 to 5). Bits 7 is not used.
2.3.4 PWM registers (addresses 00D0 16 to 00D4 16 and 00F6 16)
The PWM0 to PWM4 registers are assigned to addresses 00D0 16 to 00D4 16 and PWM5 register is
address 00F6 16. All registers consist of 8 bits.
These registers are used to set the output data corresponding to six 8-bit PWM (PWM0–PWM5).
2.3.5 PWM output control registers (addresses 00D5 16 and 00D616)
The PWM output control register 1 is assigned to address 00D516 and the PWM output control register 2
is assigned to address 00D616.
Both registers consist of 8 bits, and used to select the PWM count source etc. The high-order 3 bits and
the low-order 2 bits of the PWM output control register 2 are not used.
2.3.6 Multi-master I 2C-BUS related registers (addresses 00D7 16 to 00DB 16)
The I 2C data shift register, the I 2C address register, the I 2C status register, I 2C control register and the I 2C
clock control register are assigned to addresses 00D716, 00D8 16, 00D916, 00DA16 and 00DB16 respectively.
All registers consist of 8 bits.
The I 2C data shift register is a 8-bit shift register to store receive data and write transmit data.
The I 2C address register consists of a 7-bit slave address and a read/write bit.
The I 2C status register controls the I 2C-BUS interface status. The low-order 4 bits are read-only bits and
the high-order 4 bits can be read out and written to.
The I2C control register controls data communication format.
The I 2C clock control register is used to set ACK control, SCL mode and SCL frequency.
2.3.7 Serial I/O related registers (addresses 00DC 16 and 00DD 16)
The serial I/O mode register is assigned to address 00DC 16 and the serial I/O register is assigned to
address 00DD 16. Both registers consist of 8 bits.
The serial I/O mode register is used to select the synchronous clock and the serial I/O port function by its
low-order 4 bits. Bit 5 selects the transfer direction, and bit 6 selects the serial data input pin. Bit 4 is set
to “0.” Bit 7 is not used.
The serial I/O register is used to write transfer data.
2.3.8 CRT display related registers (addresses 00E0 16 to 00EC16)
(1) Horizontal position register (address 00E0 16)
The horizontal position register is assigned to address 00E016. This register consists of 8 bits, and
is used to specify the horizontal position of CRT display. Bits 7 and 6 are not used.
(2) Vertical display position registers (addresses 00E1 16 and 00E216)
The vertical display position register 1 is assigned to address 00E116 and the vertical display position
register 2 is assigned to address 00E2 16. These registers are corresponded to blocks 1 and 2, and
used to set the vertical position to start display. Bit 7 of each register is not used.
(3) Character size register (address 00E416)
The character size register is assigned to address 00E416. This register consists of 8 bits, and is used
to specify one of the three sizes of display characters. Bits 4 to 7 are not used.
7220 Group User’s Manual
2-17
FUNCTIONAL DESCRIPTION
2.3 Memory assignment
(4) Border selection register (address 00E516)
The border selection register is assigned to address 00E5 16. This register consists of 8 bits, and is
used to set the border for blocks 1 and 2 by using one bit each. Bits 1 and 3 to 7 are not used.
(5) Color registers (addresses 00E616 to 00E9 16)
Color registers 0 to 3 are assigned to addresses 00E616 to 00E916. All color registers consist of 8 bits,
and are used to set character output, blank output and character background color by CRT output
(R, G, B, OUT1). Bit 0 is not used.
(6) CRT control register (address 00EA16)
The CRT control register is assigned to address 00EA16. This register consists of 8 bits, and is used
to set display on/off for each block. Bits 3 to 6 are not used.
(7) CRT port control register (address 00EC16)
The CRT port control register is assigned to address 00EC 16. This register consists of 8 bits, and is
used to set the input polarity (HSYNC and VSYNC) and the output polarity (R, G, B, OUT1 and OUT2).
2.3.9 A-D control registers (addresses 00EE 16 and 00EF 16)
The A-D control register 1 is assigned to address 00EE16, the A-D control register 2 is assigned to address
00EF16. Both registers consist of 8 bits
The A-D control register 1 is used to select analog input pins and hold the results of comparator operation.
Bits 3 and 5 to 7 are not used.
The A-D control register 2 is used to set the internal analog voltage. Bits 6 and 7 are not used.
2.3.10 Timer registers (addresses 00F016 to 00F3 16)
The timer registers are assigned to addresses 00F0 16 to 00F316. Both the timer and timer latch are written
in this area when writing, but only the timer is read when reading.
To write data to address 00F116, for example, the data are stored to the timer 2 latch and timer 2. After
that, the timer 2 contents are decremented by synchronizing with the clock pulse but the timer 2 latch
contents are not changed. Accordingly, when reading data at address 00F1 16, the contents of timer 2 is
read out at the time.
Timer 2 latch
Addresses
00F016
00F116
00F216
Timer 1
00F316
Timer 4
Timer 2
Data setting
Data loading at timer 2
overflow
Timer 3
Timer 2
Counting
(down count)
At read access
Reading the contents of timer 2
Fig. 2.3.7 Access to timer registers
2-18
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.3 Memory assignment
2.3.11 Timer mode registers (address 00F4 16 and 00F5 16)
The timer 12 mode register is assigned to address 00F4 16 and the timer 34 mode register is assigned to
address 00F516. Both registers consist of 8 bits. They select the count source of timer and control the count
stop bit. Bits 5 to 7 of the timer 12 mode register and bits 6, 7 of the timer 34 mode register are not used.
2.3.12 CPU mode register (address 00FB 16)
The CPU mode register is assigned to address 00FB16. This register consists of 8 bits, and specifies the
stack page. Set bits 0 and 1 are set to “0,” and set bits 3 to 7 to “0.”
2.3.13 Interrupt request registers (addresses 00FC 16 and 00FD16)
The interrupt request register 1 is assigned to address 00FC16 and the interrupt request register 2 is
assigned to address 00FD16. Both registers consist of 8 bits, and hold content of each interrupt request bit.
Bits 3 and 5 to 7 of the interrupt request register 2 are not used.
2.3.14 Interrupt control registers (addresses 00FE 16 and 00FF16)
The interrupt control register 1 is assigned to address 00FE16 and the interrupt control register 2 is assigned
to address 00FF 16. Both registers consist of 8 bits, and sets enable/disable of interrupts.
Bits 7 to 5 and 3 of the interrupt control register 2 are not used.
2.3.15 2 page register (addresses 0217 16 to 021B16) (only M37221M8-XXXSP and M37221MA-XXXSP)
(1) ROM correction addresses (address 021716 to 021A 16)
Addresses 0217 16 to 021A 16 are assigned to ROM correction address. The ROM data addresses to
be corrected are set to the ROM correction addresses.
(2) ROM correction enable register (address 021B16)
The ROM correction enable register is assigned to address 021B 16. This register consist of 8 bits,
and controls the ROM correction function. Bits 2 to 7 are not used.
2.3.16 CRT display RAM (addresses 0600 16 to 06B7 16)
The display RAM is used to specify the character to be displayed on the CRT and its color. Two addresses
are used for one character: one address (8 bits) to specify each character code and the other (8 bits) to
specify the color of the character.
2.3.17 ROM (addresses A00016 to FFFF 16)
The mask ROM is assigned.
In this internal ROM, addresses FFDE 16, FFDF 16, FFE4 16, FFF5 16, and FFF8 16 to FFFF 16 are assigned to
vector area for reset and for interrupts. A vector jump destination storage address (16 bits) are stored in
2 addresses by the 1 interrupt source.
2.3.18 CRT display ROM (addresses 1000016 to 11FFF 16)
The display ROM stores (masks) character patterns of each character to be displayed on the CRT. Although
one character consists of 16 (vertical) × 12 (horizontal) dots, it is divided into a 16 × 8 dot and a 16 × 4
dot pattern, with each pattern stored in one address. In other words, two addresses (16 bits) are used for
one character. The ROM can store up to 256 kinds of characters.
7220 Group User’s Manual
2-19
FUNCTIONAL DESCRIPTION
2.4 Input/Output pins
2.4 Input/Output pins
The M37221M6-XXXSP/FP has 33 programable ports (I/O ports, input ports, output ports). The doublefunction ports function as ports and as pins for internal peripheral devices.
M37220M3-XXXSP/FP
Refer to “CHAPTER 4. M37220M3-XXXSP/FP.”
●Double-function ports .................... <I/O ports>
P00–P07, P10–P17, P2 0–P24, P30, P31
<Input ports>
P33, P3 4
<Output ports>
P52–P5 5
●I/O port-only ports ......................... <I/O ports>
P2 5–P2 7, P3 2
And also, the M37221M6-XXXSP/FP has 9 pins
with only the dedicated function.
________
●Dediated pins ................................. VCC, V SS, RESET, X IN, CNV SS, X OUT , D-A, H SYNC, V SYNC
2.4.1 Programmable ports
(1) Port P0
Port P0 is an 8-bit input/output port. This is an N-channel open drain output. Port P0 is assigned to
memory at address 00C016 on zero page.
Port P0 has the direction register (at address 00C116 on zero page), so that it is possible to program
each bit whether the port is used for input or output. The pins of which the direction register is
programmed to “0” are set for input; when programmed to “1”, the pins are set for output.
When pins are programmed as output pins, the output data are written into the port latch and then
output. When reading data from the output pins, the output pin level is not read but the port latch
data is read. This allows a previously-output value to be read correctly even if the output LOW
voltage has risen, for example, because a light emitting diode was directly driven.
The input pins float, so the values of the pins can be read. When writing data into the input pin, it
is written only into the port latch, while the pin remains floating.
Ports P0 0–P05 are also used as PWM output pins PWM0–PWM5 respectively. Port P0 6 is also used
as external interrupt pin INT2 and analog input pin A-D4. The P07 pin is also used as external
interrupt input pin INT1. When external interrupts INT1 and INT2 are enabled, an interrupt is processed
according to transition in the level on these pins.
Ports P06 and P07 have the schmit characteristics when they are used as INT input pins. In this case,
set these pins for input by the port P0 direction register.
2-20
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.4 Input/Output pins
(2) Port P1
Port P1 is an 8-bit I/O port. The output structure is CMOS output, however, only when ports P1 1–
P14 are used as multi-master I2C-BUS interface, the output structure is N-channel open-drain output.
Port P1 has basically the same function as port P0.
Port P1 0 is also used as CRT output pin OUT2. Pin OUT2 is a CRT output pin. When setting “1” to
bit 7 of the CRT control register, the pin functions as CRT output pin, when setting “0,” the pin
functions as a general-purpose I/O port.
Ports P1 1–P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively.
Port P1 5 is also used as external interrupt input pin INT3 and analog input pin A-D1.
Ports P1 6 and P1 7 are also used as analog input pins A-D2 and A-D3 respectively.
(3) Port P2
Port P2 is an 8-bit I/O port. The output structure is CMOS output, however, only when ports P2 0 and
P2 1 are used as serial I/O pins, the output structure is N-channel open-drain output. Port P2 has
basically the same function as port P0.
Port P20 is also used as serial I/O synchronous clock input/output pin SCLK. Port P21 is also used as
serial I/O data output pin S OUT. Port P22 is also used as serial I/O data input pin SIN.
Port P2 3 is also used as external clock input pin TIM3. When the timer 3 count source is supplied
form an external device (as set by the timer 34 mode register), the input signal to this pin is the timer
3 count source.
The port P2 4 is also used as external clock input pin TIM2. When the count source for timer 2 is
supplied form an external device (as set by the timer 12 mode register), the input signal to this pin
is the timer 2 count source.
Ports P2 5–P2 7 has only I/O port function.
(4) Port P3
Ports P3 0–P32 are 3-bit I/O ports, ports P33 and P3 4 are a 2-bit input port. For the output structure
of ports P30 and P31, either CMOS output or N-channel open-drain output structure can be selected
by bit 0 or 1 of the port P3 output mode control register (address 00CD16). When “1,” N-channel opendrain output structure is selected; when “0,” CMOS output structure is selected.
Port P32 has only I/O port function. The output structure is N-channel open-drain output. Port P3 2 has
basically the same function as port P0.
Ports P3 0 and P3 1 are also used as analog input pins A-D5 and A-D6 respectively.
Ports P3 3 and P34 are also used as CRT display clock input pins OSC1 and OSC2 respectively. Pin
OSC1 is a clock input for CRT display, pin OSC2 is a clock output for CRT display. The output
structure of pin OSC2 is CMOS output.
(5) Port P5
Ports P5 2–P5 5 are 4-bit output ports. The output structure is CMOS output. Ports P5 2–P5 5 are also
used as CRT output pins R, G, B, OUT1 respectively.
Pins R, G, B, and OUT1 are CRT output pins. When setting each bit of the port P5 direction register
to “0,” the pins function as CRT output pins; when setting to “1,” the pins function as general-purpose
output ports. The output structure of CRT output pin is CMOS output structure.
7220 Group User’s Manual
2-21
FUNCTIONAL DESCRIPTION
2.4 Input/Output pins
Table 2.4.1 List of programmable port functions
Ports
Functions except port
Name
P0 0–P05
PWM0–PWM5
PWM output pin
P0 6
INT2/A-D4
External interrupt input pin/Analog input pin
P0 7
INT1
External interrupt input pin
P1 0
P1 1
OUT2
SCL1
CRT output pin
Multi-master I 2C-BUS interface pin
P1 2
SCL2
Multi-master I 2C-BUS interface pin
P1 3
SDA1
Multi-master I 2C-BUS interface pin
P1 4
SDA2
Multi-master I 2C-BUS interface pin
P1 5
A-D1/INT3
Analog input pin/External interrupt pin
P1 6
P1 7
A-D2
A-D3
Analog input pin
Analog input pin
P2 0
SCLK
Serial I/O synchronous clock input/output pin
P2 1
SOUT
Serial I/O data input /output pin
P2 2
SIN
Serial I/O data input pin
P2 3
TIM3
External clock input pin
P2 4
P2 5–P27
TIM2
—
External clock input pin
Function as only programmable I/O ports
P3 0
A-D5
Analog input pin
P3 1
A-D6
Analog input pin
P3 2
—
Functions as only programmable I/O port.
P3 3
P3 4
OSC1
OSC2
CRT display clock input pin
CRT display clock output pin
P5 2
R
CRT output pin
P5 3
G
CRT output pin
P5 4
B
CRT output pin
P5 5
OUT1
CRT output pin
2-22
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.4 Input/Output pins
2.4.2 Dedicated pins
(1) 14-bit PWM output (D-A) pin
This is a 14-bit PWM signal output pin. This pin also can be used for 1-bit general-purpose output
port. The output structure is CMOS output.
(2) Vertical and horizontal synchronous signal input pins (VSYNC, HSYNC)
These pins input the vertical and horizontal synchronous signals for CRT display.
(3) Test input pin (CNV SS)
Connect this pin to V SS.
(4) Reset input pin (RESET)
This pin inputs reset signal. To reset the microcomputer, hold the RESET pin at a LOW level for
2 µs or more. Reset is released when HIGH level is applied to the RESET pin. For details, refer to
“2.15 Reset.”
(5) Clock I/O pins (X IN, X OUT)
These pins are I/O pins of main clock f(X IN). Since a microcomputer has on-chip clock oscillation
circuit, set the oscillation frequency by connecting an external ceramic resonator or a quartz-crystal
oscillator between pins X IN and X OUT.
When inputting an external clock, connect the external clock to the X IN pin and leave the XOUT pin
open.
The output structure of X OUT pin is CMOS output.
(6) Power source input pin (V CC, V SS)
These pins supply the power source to a microcomputer. Apply voltage of 5 V ± 10 % to pin VCC and
0 V to pin V SS.
7220 Group User’s Manual
2-23
FUNCTIONAL DESCRIPTION
2.4 Input/Output pins
P00/PWM0–P0 5/PWM5, P3 2
N-channel open-drain output
Direction register
Data bus
Port latch
P10/OUT2, P1 1/SCL1, P1 2/SCL2, P1 3/SDA1, P1 4/SDA2, P1 5/A-D1/INT3, P1 6/A-D2, P1 7/A-D3,
P20/SCLK, P21/SOUT, P22/SIN, P23/TIM3, P2 4/TIM2, P2 5–P27, P30/A-D5, P3 1/A-D6
Direction register
CMOS output
Data bus
Port latch
Notes 1 : When ports P1 1–P14 are used as multi-master I 2 C-BUS interface pin and when ports P2 0, P21 are used as
serial I/O output pins, their output structure is N-channel open-drain output.
2 : For the output structure of ports P3 0, P31, either CMOS output or N-channel open-drain output is selected
(In the case of N-channel open-drain output, the block diagram is the same as below).
P06/INT2/A-D4, P0 7/INT1
N-channel open-drain output
Direction register
Data bus
Port latch
indicates a pin.
Fig. 2.4.1 I/O pin block diagram (1)
2-24
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.4 Input/Output pins
P33/OSC1, P3 4
Input
Internal circuit
D-A, P5 2/R, P5 3/G, P5 4/B, P5 5/OUT1
CMOS output
Internal circuit
HSYNC , VSYNC
Schmidt input
H SYNC or
VSYNC
indicates a pin.
Fig. 2.4.2 I/O pin block diagram (2)
7220 Group User’s Manual
2-25
FUNCTIONAL DESCRIPTION
2.5 Interrupts
2.5 Interrupts
Interrupts are used in the following cases.
● When there is a request to execute a higher priority routine than current processing routine.
● When it is necessary to process according to a certain timing.
The M37221M6-XXXSP/FP has 14 interrupt sources (including reset).
These are vector interrupts with a fixed priority sequence. Table 2.5.1 shows the interrupt sources, vector
addresses and the interrupt priority sequence.
M37220M3-XXXSP/FP
Refer to “CHAPTER 4. M37220M3-XXXSP/FP.”
Table 2.5.1 Interrupt sources, vector addresses and priority
Priority
Interrupt sources
Vector addresses
High-order byte Low-order byte
1
Reset (Note)
FFFF16
FFFE16
2
FFFD 16
FFFC16
3
CRT interrupt
INT2 interrupt
4
INT1 interrupt
FFFB16
FFF9 16
FFFA16
FFF816
5
6
Timer 4 interrupt
FFF5 16
FFF416
f(XIN)/4096 interrupt
FFF3 16
FFF216
7
VSYNC interrupt
FFF1 16
FFF016
8
Timer 3 interrupt
Timer 2 interrupt
FFEF16
FFEE16
Timer 1 interrupt
FFED16
FFEB 16
FFEC16
FFEA16
Serial I/O interrupt
FFE916
FFE816
9
10
11
12
Multi-master I C-BUS interface interrupt
FFE716
FFE616
13
INT3 interrupt
BRK instruction interrupt
FFE516
FFE416
FFDF 16
FFDE16
14
2
Remarks
Non-maskable
Active edge selectable
Active edge selectable
Active edge selectable
Active edge selectable
Non-maskable (software interrupt)
Note: Reset are included in the table because it operates in the same way as interrupts.
These 14-source, 14-vector interrupts have the priority sequence as shown in Table 2.5.1 (reset has a
higher priority than interrupts).
When two or more interrupt requests occur at the same sampling point, the interrupt with the higher priority
(in order of 1 to 14) is received. This priority sequence is determined by hardware, but priority processing
is possible to be varied by software, by using the interrupt enable bit and the interrupt disable flag.
2-26
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.5 Interrupts
2.5.1 Interrupt sources
The following explains interrupt sources, in order of priority (except reset).
(1) CRT interrupt
When displaying a character block with the CRT display function, the CRT interrupt request occurs
at the completion of the display.
(2) INT2 interrupt
An INT2 interrupt request is generated by detecting a level transition on pin INT2 (external interrupt
input).
Detecting either positive polarity (LOW to HIGH transition) or negative polarity (HIGH to LOW transition)
is set with RE4 (the interrupt input polarity register: bit 4 at address 00F9 16). When RE4 is set to “0,”
a positive polarity is detected; when RE4 is set to “1,” a negative polarity is detected.
The INT2 pin is also used for port P0 6 and pin A-D4. An INT2 interrupt by a level transition on the
pin may cause software runaway. Therefore, when this pin is used as port P0 6, disable an INT2
interrupt by using an interrupt enable bit and the interrupt disable flag (I).
(3) INT1 interrupt
An INT1 interrupt request is generated by detecting a level transition on pin INT1 (external interrupt
input).
Detecting either positive polarity (LOW to HIGH transition) or negative polarity (HIGH to LOW transition)
to be detected is set with RE3 (the interrupt input polarity register: bit 3 at address 00F9 16). When
RE3 is set to “0,” a positive polarity is detected; when RE3 is set to “1,” a negative polarity is
detected.
Pin INT1 is also used for port P0 7. An INT1 interrupt by a level transition on the pin may cause
software runaway. Therefore, when this pin is used as port P07, disable the INT1 interrupt by using
an interrupt enable bit and interrupt disable flag (I).
(4) Timer 4 interrupt
Timer 4 value is counted down. Timer 4 interrupt request occurs when the count source next to “0016”
is input.
(5) f(XIN)/4096 interrupt
A f(X IN)/4096 interrupt request occurs for a f(X IN)/4096 period.
This interrupt is valid when the PWM count source is supplied (when bit 0 of PWM output control
register 1 is “0”).
(6) VSYNC interrupt
A VSYNC interrupt request occurs synchronized
with the vertical synchronous signal which
is input to pin V SYNC.
When the VSYNC input polarity is positive (the
CRT port control register: bit 1 at address
00EC 16 is “0”), an interrupt request is
generated by a rising edge (LOW to HIGH
transition) of the V SYNC input; conversely,
when the polarity is negative, an interrupt
request is generated by a falling edge.
Positive polarity
input
VSYNC
input pin
Negative polarity
input
: Interrupt request is generated
Fig. 2.5.1 VSYNC interrupt generation timing
7220 Group User’s Manual
2-27
FUNCTIONAL DESCRIPTION
2.5 Interrupts
(7) Timer 3 interrupt
Timer 3 value is counted down. Timer 3 interrupt request occurs when the count source next to “00 16”
is input.
(8) Timer 2 interrupt
Timer 2 value is counted down. Timer 2 interrupt request occurs when a count source next to “00 16”
is input
(9) Timer 1 interrupt
Timer 1 value is counted down. Timer 1 interrupt request occurs when a count source next to “00 16”
is input.
(10) Serial I/O interrupt
The serial I/O interrupt request is generated by detecting a rising edge of the eighth serial transfer
clock after writing to the serial I/O register.
(11) Multi-master I2C-BUS interface interrupt
A multi-master interrupt request occurs synchronized with a falling edge serial clock (SCL) every
completion of 1-byte data communication.
(12) INT3 interrupt
An INT3 interrupt request is generated by detecting a transition in the level on pin INT3 (external
interrupt input).
Detecting either positive polarity (LOW to HIGH transition) or negative polarity (HIGH to LOW transition)
to be detected is set with RE5 (the interrupt input polarity register: bit 5 at address 00F9 16). When
RE5 is set to “0,” a positive polarity is detected, when RE5 is set to “1,” a negative polarity is
detected.
Pin INT3 is also used for port P1 5 and pin A-D1. An INT3 interrupt by a level transition on the pin
may cause software runaway. Therefore, when this pin is used as port P15, disable an INT3 interrupt
by using an interrupt enable bit and interrupt disable flag (1).
(13) BRK instruction interrupt
This software interrupt has the least significant priority and generates an interrupt request is generated
by executing when the BRK instruction. There is no corresponding interrupt enable bit and no
influence by the interrupt disable flag (I).
2-28
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.5 Interrupts
2.5.2 Interrupt control
Each interrupt can be controlled with the interrupt request bit, the interrupt control bit, and the interrupt
disable flag.
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
Reset
BRK instruction
Start of
interrupt
process
Fig. 2.5.2 Interrupt control logic
(1) Interrupt request bit
When an interrupt request occurs, the corresponding bit of the interrupt request register is set to “1.”
The interrupt request is held active until an interrupt is accepted or “0” is written to the relevant bit
by software. The bit is automatically cleared to “0” simultaneously when the interrupt is accepted.
Interrupt request bits are cleared to “0” (to clear the interrupt request) by software but are not set
to “1” (to generate the interrupt request) by software.
Each interrupt request bit is assigned to interrupt request registers 1 and 2 (addresses 00FC 16 and
00FD16).
(2) Interrupt enable bit
Interrupt enable bits control the acceptance of each interrupt.
When the interrupt enable bit is cleared to “0” (to disable an interrupt), the interrupt cannot be
accepted. Conversely, when the interrupt enable bit is set to “1” (to enable an interrupt), the interrupt
is accepted. However, if the interrupt disable flag is set to “1,” the interrupt cannot be accepted even
when the interrupt enable bit is set to “1.”
Each interrupt enable bit is assigned to interrupt control registers 1 and 2 (addresses 00FE16 and
00FF16).
(3) Interrupt disable flag (I)
The interrupt disable flag (I) is assigned to bit 2 of the processor status register. When the interrupt
disable flag is set to “1,” all interrupts except the BRK instruction interrupt are disabled; when the
flag is cleared to “0,” interrupts are enabled. However, if the interrupt disable flag is cleared to “0,”
the interrupt cannot be accepted even when the interrupt enable bit is “0.”
7220 Group User’s Manual
2-29
FUNCTIONAL DESCRIPTION
2.5 Interrupts
Interrupt Request Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address 00FC16]
B
0
Name
Functions
After reset R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
Multi-master I 2C-BUS interface 0 : No interrupt request issued
interrupt request bit (IICR) 1 : Interrupt request issued
INT3 interrupt
0 : No interrupt request issued
request bit (IT3R)
1 : Interrupt request issued
Timer 1 interrupt
request bit (TM1R)
Timer 2 interrupt
request bit (TM2R)
Timer 3 interrupt
request bit (TM3R)
Timer 4 interrupt
request bit (TM4R)
CRT interrupt
request bit (CRTR)
V SYNC interrupt
request bit (VSCR)
1
2
3
4
5
6
7
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R ✽
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.5.3 Interrupt request register 1 (address 00FC 16)
Interrupt Request Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt request register 2 (IREQ2) [Address 00FD16]
B
Name
Functions
INT1 interrupt
0 : No interrupt request issued
request bit (ITIR)
1 : Interrupt request issued
1 INT2 interrupt
0 : No interrupt request issued
request bit (IT2R)
1 : Interrupt request issued
0 : No interrupt request issued
2 Serial I/O interrupt
request bit (S1R)
1 : Interrupt request issued
3 Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
4 f(XIN)/4096 interrupt 0 : No interrupt request issued
request bit (MSR)
1 : Interrupt request issued
5, 6 Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
7 Fix this bit to “0.”
0
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.5.4 Interrupt request register 2 (address 00FD 16)
2-30
7220 Group User’s Manual
After reset R W
0
R ✽
0
R ✽
0
R ✽
0
R —
0
R ✽
0
R —
0
R W
FUNCTIONAL DESCRIPTION
2.5 Interrupts
Interrupt Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address 00FE16]
B
Name
0
Timer 1 interrupt
enable bit (TM1E)
1
Timer 2 interrupt
enable bit (TM2E)
Timer 3 interrupt
enable bit (TM3E)
Timer 4 interrupt
enable bit (TM4E)
2
3
4
CRT interrupt enable
bit (CRTE)
VSYNC interrupt
enable bit (VSCE)
Multi-master I 2C-BUS interface
interrupt enable bit (IICE)
INT3 interrupt
enable bit (IT3E)
5
6
7
Functions
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
After reset R W
0
R W
0
R W
0
R W
0
R W
0
R W
0
R W
0
R W
0
R W
Fig. 2.5.5 Interrupt control register 1 (address 00FE 16)
Interrupt Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
0
Interrupt control register 2 (ICON2) [Address 00FF16]
B
Name
0
INT1 interrupt
enable bit (IT1E)
INT2 interrupt enable
bit (IT2E)
Serial I/O interrupt
enable bit (S1E)
Fix this bit to “0.”
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
f(XIN)/4096 interrupt
enable bit (MSE)
Fix these bits to “0.”
0 : Interrupt disabled
1 : Interrupt enabled
1
2
3
4
5
to
Functions
After reset R W
0
R W
0
R W
0
R W
0
R W
0
R W
0
R W
7
Fig. 2.5.6 Interrupt control register 2 (address 00FF 16)
7220 Group User’s Manual
2-31
FUNCTIONAL DESCRIPTION
2.5 Interrupts
Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
Interrupt input polarity register(RE) [Address 00F9 16 ]
b
0
Name
Functions
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
1, 2 Fix these bits to “0.”
After reset
R W
Indeterminate
R —
0
R W
3
INT1 polarity switch bit
(RE3)
0 : Positive polarity
1 : Negative polarity
0
R W
4
INT2 polarity switch bit
(RE4)
0 : Positive polarity
1 : Negative polarity
0
R W
5
INT3 polarity switch bit
(RE5)
0 : Positive polarity
1 : Negative polarity
0
R W
6
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
0
R —
7
Fix this bit to “0.”
0
R W
Fig. 2.5.7 Interrupt input polatiry register (address 00F916)
CRT port control register
b7 b6 b5 b4 b3 b2 b1 b0
CRT port control register(CRTP) [Address 00EC 16 ]
b
Name
Functions
HSYNC input polarity
switch bit (HSYC)
0 : Positive polarity
1 : Negative polarity
0
R W
1
VSYNC input polarity
switch bit (VSYC)
0 : Positive polarity
1 : Negative polarity
0
R W
2
R, G, B output polarity
switch bit (R, G, B)
0 : Positive polarity
1 : Negative polarity
0
R W
3
OUT2 output polarity
switch bit (OUT2)
0 : Positive polarity
1 : Negative polarity
0
R W
4
OUT1 output polarity
switch bit (OUT1)
0 : Positive polarity
1 : Negative polarity
0
R W
5
R signal output switch bit
(OP5)
0 : R signal output
1 : MUTE signal output
0
R W
6
G signal output switch bit
(OP6)
0 : G signal output
1 : MUTE signal output
0
R W
7
B signal output switch bit
(OP7)
0 : B signal output
1 : MUTE signal output
0
R W
Fig. 2.5.8 CRT port control register (address 00EC16)
2-32
After reset R W
0
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.5 Interrupts
Interrupt request bits are set to “1” by occurrence of an interrupt request, even if the interrupt is disabled.
Therefore, to disable interrupt processing, clear the interrupt request bit to “0” immediately before the
interrupt disable state is cancelled (interrupt enable state, i.e., the interrupt enable bit = “1” and the interrupt
disable flag = “0”).
Reset
RESET
CRT interrupt
CRTR
INT2 interrupt
IT2R
INT1 interrupt
Timer 4 interrupt
f(XIN)/4096 interrupt
VSYNC interrupt
Timer 3 interrupt
Timer 2 interrupt
Timer 1 interrupt
Serial I/O interrupt
Multi-master I2C-BUS interface interrupt
VSCR
TM3R
TM2R
TM1R
Note:
FFF516, FFF416
FFF316, FFF216
VSCE
FFF116, FFF016
TM3E
FFEF16, FFEE16
TM2E
FFED16, FFEC16
TM1E
FFEB16, FFEA16
S1E
S1R
IICR
BRK
FFF916, FFF816
TM4E
MSE
MSR
BRK instruction interrupt
FFFB16, FFFA16
IT1E
TM4R
IT3R
FFFD16, FFFC16
IT2E
IT1R
INT3 interrupt
FFFF16, FFFE16
CRTE
FFE916, FFE816
IICE
FFE716, FFE616
IT3E
FFE516, FFE416
FFDF16, FFDE16
Interrupt
Interrupt
request bit enable bit
indicates to operate together.
Interrupt
disable flag (I)
Interrupt
vector
Fig. 2.5.9 Interrupt control system
Internal ROM area
FFDE16
FFDF16
BRK instruction interrupt L
H
FFE016
Internal ROM area
FFE416
FFE516
FFE616
FFE716
INT3 interrupt
I2 C-BUS
Multi-master
interface interrupt
FFE816
FFE916
Serial I/O interrupt
FFEA16
FFEB16
Timer 1 interrupt
FFEC16
FFED16
Timer 2 interrupt
L
H
L
H
L
H
L
H
L
H
FFEE16
FFEF16
Timer 3 interrupt
FFF016
FFF116
VSYNC interrupt
FFF216
FFF316
f(XIN)/4096 interrupt
FFF416
FFF516
Timer 4 interrupt
FFF616
FFF716
Internal ROM area
FFF816
FFF916
INT1 interrupt
FFFA16
FFFB16
INT2 interrupt
FFFC16
FFFD16
CRT interrupt
FFFE16
FFFF16
Reset
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Interrupt Vector Table
The low-order 8 bits and the high-order 8 bits of jump destination address
when an interrupt occurs, are stored to addresses “L” and “H” respectively.
Fig. 2.5.10 Interrupt vector table
7220 Group User’s Manual
2-33
FUNCTIONAL DESCRIPTION
2.6 Timers
2.6 Timers
M37221M6-XXXSP/FP has four 8-bit timers with reload latch. Figure 2.6.1 shows the timer block diagram.
Data bus
8
Timer 1 latch (8)
1/4096
8
XIN
1/2
1/8
Timer 1
interrupt request
Timer 1 (8)
T12M0
T12M2
8
T12M4
8
Timer 2 latch (8)
8
P24/TIM2
(Note 3)
Timer 2
interrupt request
Timer 2 (8)
T12M1
T12M3
8
HSYNC
8
FF16
P23/TIM3
T34M5
Timer 3 latch (8)
(Note 3)
8
Timer 3
interrupt request
Timer 3 (8)
T34M0
T34M2
8
8
Selection gate :
Connected to black
side at reset
0716
T34M1
Timer 4 latch (8)
T12M : Timer 12 mode register
T34M : Timer 34 mode register
8
Timer 4
interrupt request
Timer 4 (8)
T34M4
T34M3
8
Notes 1: HIGH pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more.
2: When the external clock source is selected, timers 2 and 3 are counted at a rising edge of input signal.
3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.
Fig. 2.6.1 Timer 1, timer 2, timer 3, and timer 4 block diagram
2-34
Reset
STP
instruction
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.6 Timers
2.6.1 Timer functions
There are four timers; Timer 1, Timer 2, Timer 3, Timer 4 and each timer has an 8-bit reload latch. All
timers are the count-down type, and when the timer latch value is “n”, the divide ratio is 1/(n+1)(“n” = 0
to 255). When the valve “n” is written to reload latch, is also set “n” to its timer, simultaneously.
Timer value is counted down each rising edge of count source. The timer overflows at the count next pulse,
after the count value reaches “0016,” and the interrupt request occurs. At the same time of timer overflow,
the reload latch value “n” is set (reload) to timer, and timer continues to count down. The divide ratio is
1/(n+1). Make sure that set “n” in the range “00 16” to “FF 16.”
Count source
Timer
nn16 nn16-1
0116
0016
nn16
nn16-1
Writing Value
Overflow signal
Interrupt request
Fig. 2.6.2 Timer overflow timing
(1) Timer 1
Timer 1 can select one of the following count sources:
● f(X IN)/16
● f(X IN)/4096
(This is a clock by f(X IN)/4096 interrupt and is valid only when PWM count source is supplied.)
The count source of timer 1 is selected by setting bit 0 of the timer 12 mode register (address
00F416).
Timer 1 interrupt request occurs at timer 1 overflow.
(2) Timer 2
Timer 2 can select one of the following count sources:
● f(X IN)/16
● Timer 1 overflow signal
● External clock from pin P2 4/TIM2
The count source of timer 2 is selected by setting bits 4 and 1 of the timer 12 mode register (address
00F4 16). When timer 1 overflow signal is a count source for timer 2, timer 1 functions as an 8-bit
prescaler.
Timer 2 interrupt request occurs at timer 2 overflow.
7220 Group User’s Manual
2-35
FUNCTIONAL DESCRIPTION
2.6 Timers
Timer 12 Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Timer 12 mode register (T12M) [Address 00F416]
After reset R W
0
R W
B
Name
0 Timer 1 count source
selection bit (T12M0)
Functions
0: f(XIN)/16
1: f(XIN)/4096
1
Timer 2 count source
selection bit
(T12M1)
0: Internal clock
1: External clock from
P24/TIM2 pin
0
R W
2
Timer 1 count
stop bit (T12M2)
Timer 2 count stop
bit (T12M3)
0: Count start
1: Count stop
0: Count start
1: Count stop
0: f(XIN)/16
1: Timer 1 overflow
0
R W
0
R W
0
R W
0
R W
0
R —
3
4
Timer 2 internal count
source selection bit
(T12M4)
5
Fix this bit to “0.”
6,7 Nothing is assigned. These bits are write disable
bits. When these bits are read out, the values are
“0.”
Fig. 2.6.3 Timer 12 mode register (address 00F4 16)
(3) Timer 3
Timer 3 can select one of the following count sources:
● f(X IN)/16
● External clock from pin H SYNC
● External clock from pin P2 3/TIM3
The count source of timer 3 is selected by setting bits 5 and 0 of the timer 34 mode register (address
00F5 16)
Timer 3 interrupt request occurs at timer 3 overflow.
(4) Timer 4
Timer 4 can select one of the following count sources:
● f(X IN)/16
● f(XIN)/2
● Timer 3 overflow signal
The count source of timer 3 is selected by setting bits 4 and 1 of the timer 34 mode register (address
00F5 16). When timer 3 overflow signal is a count source for timer 4, timer 3 functions as an 8-bit
prescaler.
Timer 4 interrupt request occurs at timer 4 overflow.
2-36
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.6 Timers
Timer 34 Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 34 mode register (T34M) [Address 00F516]
B
Name
0 Timer 3 count source
selection bit (T34M0)
Functions
0: f(XIN)/16
1: External clock
1
Timer 4 internal count
source selection bit
(T34M1)
0: Timer 3 overflow
1: f(X IN)/16
0
R W
2
Timer 3 count
stop bit (T34M2)
0: Count start
1: Count stop
0
R W
3
Timer 4 count stop
bit (T34M3)
0: Count start
1: Count stop
0
R W
4
Timer 4 count source
selection bit (T34M4)
0: Internal clock
1: f(XIN)/2
0
R W
5
Timer 3 external count
0: External clock from P2 3/TIM3 pin
source selection bit (T34M5) 1: External clock from H SYNC pin
0
R W
0
R —
6,7 Nothing is assigned. These bits are write disable
bits. When these bits are read out, the values are
“0.”
After reset R W
0
R W
Fig. 2.6.4 Timer 34 mode register (address 00F5 16)
Table 2.6.1 Memory map of timer-related registers
Addresses
00F016
Contents
Timer 1 (TM1)
00F116
Timer 2 (TM2)
00F216
Timer 3 (TM3)
00F316
Timer 4 (TM4)
00F416
Timer 12 mode register (T12M)
00F516
Timer 34 mode register (T34M)
7220 Group User’s Manual
2-37
FUNCTIONAL DESCRIPTION
2.6 Timers
T12M4 T12M1 T12M0
0
0
0
“1”
f(XIN)
Timer 1
1/16
“0”
“1”
Timer 1
interrupt
request
“0”
T12M2
Timer 2
Timer 2
interrupt
request
Timer 2
Timer 2
interrupt
request
Timer 2
Timer 2
interrupt
request
Timer 2
Timer 2
interrupt
request
T12M3
T12M4 T12M1 T12M0
0
0
1
“1”
f(XIN)
f(XIN)
1/4096
Timer 1
“0”
P24/TIM2
Timer 1
1/16
Timer 1
interrupt
request
T12M2
T12M4 T12M1 T12M0
1
0
0
“1”
Timer 1
interrupt
request
“1”
“0”
T12M3
“1”
Timer 1
1/16
“0”
“0”
T12M2
Fig. 2.6.5 Example of timer system
2-38
T12M3
1/16
“0”
f(XIN)
“0”
T12M2
T12M4 T12M1 T12M0
0
1
0
“1”
f(XIN)
“1”
Timer 1
interrupt
request
7220 Group User’s Manual
T12M3
FUNCTIONAL DESCRIPTION
2.6 Timers
2.6.2 Timer 3 and timer 4 when reset and when executing the STP instruction
Timers 3 and 4 start counting down immediately after reset status is released or stop mode is released,
and CPU starts operating by supplying the internal clock φ at overflow of these timers. Therefore, the
program can start under a stable clock.
(1) When reset
When reset, Timers 3 and 4 are automatically set by hardware as shown in Table 2.6.2, and immediately
start counting down. The counting is continued, then, Timer 4 overflows and the internal clock φ is
supplied (the internal reset is released). The program can start again.
(2) When executing the STP instruction
Immediately after the STP instruction is executed, Timers 3 and 4 are automatically set as shown
in Table 2.6.2 as in the case of reset and placed in the stop mode. When the stop mode is entered,
the processor stops supplying the internal clock φ , and contents of Timers 3 and 4 are retained.
When the stop mode is released by reset input or external interrupt input, the processor simultaneously
supplies f(X IN), and Timers 3 and 4 start counting down.
The counting is continued, then, when timer 4 overflows and the internal clock φ is supplied. The
program can start again.
Table 2.6.2 Contents of timers 3 and 4 when reset or when executing STP instruction
Timer 4
Contents
Timer 3
07 16
Value
FF 16
Count source
f(X IN)/16
(except when executing the STP instructions)
Timer 3 overflow signal
Note: When executing the STP instruction, f(X IN )/16 is not automatically selected as the timer 3 count
source. Accordingly, set bit 0 of the timer 34 mode register (address 00F5 16) to “0” before executing
the STP instruction select (f(X IN)/16 is selected as the timer 3 count source).
7220 Group User’s Manual
2-39
FUNCTIONAL DESCRIPTION
2.7 Serial I/O
2.7 Serial I/O
The M37221M6-XXXSP/FP has on-chip clock synchronous serial I/O which can receive and transmit 8-bit
data serially.
Because pin SOUT also can be used as the serial I/O data input pin, it can transmit and receive with only
one signal line.
2.7.1 Structure of serial I/O
Serial I/O consists of
● Serial I/O register
● Serial I/O mode register
● Serial I/O counter
● Clock source generating counter
The serial I/O register is the register which 8-bit transfer data is written into. Each function of serial I/O
can be controlled by setting appropriate values to the serial I/O mode register.
Serial I/O transfers data to and from the internal CPU via the data bus, and it transfers data to and from
external devices via ports P2 2–P20. When using the serial I/O, ports P2 2–P20 have the following functions:
● P20 : Serial I/O synchronous clock input/output pin (SCLK)
● P21 : Serial I/O data input/output pin (S OUT )
● P22: Serial I/O data input pin (S IN)
The functions of these ports can be selected by the serial I/O mode register.
The transfer clock that determines the serial data transfer rate can selected 4 kinds of clock sources with
the serial I/O mode register.
Figure 2.7.1 shows the serial I/O block diagram, Figure 2.7.2 shows the serial I/O mode register.
2-40
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.7 Serial I/O
Data bus
XIN
1/2
Frequency
divider
1/2
1/4 1/8
1/16
SM1
SM0
SM2
S
Synchronous circuit
Clock source
generating circuit
P20 latch
P20/SCLK
SM3
P21 latch
SM5 : LSB
SM : Serial I/O mode register
Serial I/O interrupt
request
Serial I/O counter (8)
P21/SOUT
Selection gate :
Connected to black
side at reset.
MSB
SM3
P22/SIN
Serial I/O shift register (8)
(Address 00DD 16)
8
SM6
Note: When the data is set in the serial I/O register (address 00DD16),
the register functions as the serial I/O shift register.
Fig. 2.7.1 Serial I/O block diagram
Serial I/O Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Serial I/O mode register (SM) [Address 00DC 16]
B
Name
0, 1 Internal synchronous
clock selection bits
(SM0, SM1)
Functions
b1
0
0
1
1
b0
0: f(X IN)/4
1: f(X IN)/16
0: f(X IN)/32
1: f(X IN)/64
After reset R W
R W
0
2
Synchronous clock
selection bit (SM2)
0: External clock
1: Internal clock
0
R W
3
Serial I/O port
selection bit (SM3)
0: P2 0, P21 functions
as port
1: S CLK, SOUT
0
R W
4
Fix this bit to “0.”
0
R W
5
Transfer direction
selection bit (SM5)
0: LSB first
1: MSB first
0
R W
6
Serial input pin
selection bit (SM6)
0: Input signal from S IN pin
1: Input signal from S OUT pin
0
R W
7
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
0
R —
Fig. 2.7.2 Serial I/O mode register (address 00DC16 )
7220 Group User’s Manual
2-41
FUNCTIONAL DESCRIPTION
2.7 Serial I/O
2.7.2 Serial I/O register (address 00DD 16)
The serial I/O register is serial-parallel conversion register used for data transfer. This register consists of
8-bit and can be used as both transmit and receive register.
Serial I/O register is assigned to address 00DD 16.
Although data transfer is performed bit by bit, it is possible to specify whether the data is transferred
beginning with most-significant-bit (MSB) or least-significant-bit (LSB) by using bit 5 of the serial I/O mode
register.
(1) When bit 5 of the serial I/O mode register is “0”
● Receive: Data is received bit by bit beginning with the MSB (bit 7) of the serial I/O register.
● Transmit: Data is transmitted bit by bit beginning with the LSB (bit 0) of the serial I/O register.
(2) When bit 5 of the serial I/O mode register is “1”
● Receive: Data is received bit by bit beginning with the LSB (bit 0) of the serial I/O register.
● Transmit: Data is transmitted bit by bit beginning with the MSB (bit 7) of the serial I/O register.
2.7.3 Clock source generating circuit
The clock source generating circuit can select oscillation frequency divided by 4, 16, 32, and 64 as the
internal clock. Also, it can select an external clock (the external clock is selected immediately after reset).
Bit 2 of the serial I/O mode register specifies internal clock or external clock. When bit 2 of the serial
I/O mode register is set to “0,” an external clock is
selected, when “1,” an internal clock is selected.
Table 2.7.1 Clock source selection
When selecting an internal clock, set the division
Serial I/O mode register
of oscillation frequency by bits 0 and 1 of the serial
Serial I/O clock
Bit 1
Bit 2
Bit 0
I/O mode register.
● Oscillation frequency divided by 4:
0 or 1 (Invalid)
External clock
0
set both bits 1 and 0 to “0.”
0
0
f(XIN)/4
● Oscillation frequency divided by 16:
0
Internal
f(XIN)/16
1
1
set bit 1 = “0” and bit 0 = “1.”
0
1
clock
f(XIN)/32
● Oscillation frequency divided by 32:
1
1
f(XIN)/64
set bit 1 = “1” and bit 0 = “0.”
● Oscillation frequency divided by 64:
set both bit 1 and 0 to “1.”
The contents of bits 0 and 1 of the serial I/O mode register are invalid, when selecting an external clock.
2.7.4 Serial input/output common transmission/reception mode
Pin P21/SOUT can also be used as the serial I/O data input pin when the serial input pin selection bit (bit
6 of the serial I/O mode register; address 00DC 16) is set to “1.” (It is not necessary to set the corresponding
bit of port P2 direction register to input mode.)
With this function, pin P2 2/SIN can also be used as general-purpose input port P2 2.
P20/S CLK
Clock
Input or output
Transmit mode
P21/SOUT
“1”
SM6
P22/SIN
Serial I/O register (8)
“0”
Receive mode
Port P2 2 data
Note: To start receiving, set “FF16” to the serial I/O register
Fig. 2.7.3 Serial input/output common transfer mode block diagram
2-42
7220 Group User’s Manual
SM: Serial I/O register
FUNCTIONAL DESCRIPTION
2.7 Serial I/O
2.7.5 Serial I/O data receive method (when an internal clock is selected)
(1) Initialization
First, set the serial I/O mode register (address 00DC 16 ) as follows.
➀ Select the synchronous clock (SM2 = “1,” SM1, SM0).
➁ Set P20 as pin SCLK (SM3 = “1”). Pin P21/S OUT is not used when receiving serial data. However,
since the serial I/O port selection bit (SM3) is also used for setting pin SOUT, port P21 is automatically
set as pin S OUT and loses its general-purpose I/O port function.
➂ Select the serial input pin by the serial input pin selection bit (SM6). When SM6 = “0,” signal is
input from pin P22 /SIN; when SM6 = “1,” signal is input from pin P21/S OUT. When pin P22 /SIN is a
input pin, set the port P2 direction register to input mode (“0”). For pins P2 0/S CLK and P21/S OUT, the
corresponding bits of the port P2 direction register are automatically set by setting the serial I/O
mode register.
(2) Receive enable state
After the above setting have been made, write “FF16” to the serial I/O register (address 00DD 16). The
serial I/O counter is then set to “0716” during the write cycle and receive is enabled.
(3) Receive operation
The data from the serial I/O data input pins (S OUT or SIN) is received one bit at a time into the serial
I/O register in synchronization with rising edges of the transfer clock.
Receive operation is performed according to bit 5 (SM5) of the serial I/O mode register:
➀ When SM5 is set to “0,” data is received from MSB (bit 7) of the register and shifted to the right
(to low-order bit) every time new data is received.
➁ When SM5 is set to “1,” data is received from LSB (bit 0) of the register and shifted to the left (to
high-order bit) every time new data is received.
When all 8-bit data have been received, the serial I/O interrupt request bit (bit 2) of the interrupt
request register 2 (address 00FD16) is set to “1.”
MSB
When receiving
LSB
D0
D1 D0
D2 D1 D0
•
•
•
D7 D6 D5 D4 D3 D2 D1 D0
Transfer clock
Serial I/O register
Note: To start receiving, set “FF16” to the serial I/O register.
Fig. 2.7.4 Serial I/O register when receiving (when SM5 = “0”)
7220 Group User’s Manual
2-43
FUNCTIONAL DESCRIPTION
2.7 Serial I/O
2.7.6 Serial I/O data transmit method (when an external clock is selected)
(1) Initialization
First, set the serial I/O mode register (address 00DC 16 ) as follows.
➀ Select the synchronous clock (SM2 = “0”).
➁ Set P20 as pin SCLK (SM3 = “1”). Since the serial I/O port selection bit (SM3) is also used for the
setting pin SOUT , port P21 is automatically becomes the S OUT pin.
Note: It is not necessary to set pin P22/SIN as pin SIN when transmitting. It can be used as generalpurpose input pin.
(2) Transmit enable state
When transmit data are written to the serial I/O register, the serial I/O counter is set to “0716” and
transmit is enabled.
(3) Transmit operation
When transmit is enabled (the serial I/O counter value = “0716”), simultaneously, the data of the serial
I/O register is transmitted from pin P21/S OUT in synchronization with a falling edge of the transfer
clock.
Transmission is performed according to bit 5 (SM5) of the serial I/O mode register:
➀ When SM5 is set to “0,” data is transmitted from LSB (bit 0) of the register and shifted to the right
(to low-order bit) every time new data is transmitted.
➁ When SM5 is set to “1,” data is transmitted from MSB (bit 7) of the register and shifted to the left
(to high-order bit) every time new data is transmitted.
When all 8-bit data have been transmitted, the serial I/O interrupt request bit (bit 2) of the interrupt
request register 2 (address 00FD 16) is set to “1.”
Pin P21 /SOUT will be in after transmit operation has been completed.
Note: On programming, note that the serial I/O counter is set even by writing to the serial I/O register
with bit management instructions, such as SEB and CLB.
When transmitting
MSB
LSB
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1
D0
D7 D6 D5 D4 D3 D2
D1
D7 D6 D5 D4 D3
•
•
•
D2
D7
Transfer clock
Serial I/O register
Fig. 2.7.5 Serial I/O register when transmitting (when SM5 = “0”)
2-44
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.7 Serial I/O
2.7.7 Note when selecting a synchronous clock
Regardless of either an internal or external clock is selected as the serial I/O synchronous clock source,
the interrupt request bit is set to “1” after 8 transfer clocks.
However, the serial I/O register contents will continue to be shifted as long as the transfer clock is being
input to the serial I/O circuit, so it is necessary to stop after 8 transfer clocks.
When an internal clock is selected, the transfer clock stops automatically after 8 clocks.
When an external clock is selected, control the transfer clock externally. Moreover, use an external clock
of 1 MHz or less with a duty cycle of 50 %.
When selecting an external clock as the synchronizing clock, write transmit data to the serial I/O register
transfer clock input level is HIGH
Figure 2.7.6 shows the serial I/O timing.
Synchronous clock
Transfer clock
Serial I/O register
writing signal
Serial I/O output
SOUT
D0
D1
D2
D3
D4
D5
D6
D7
Serial I/O input
SIN
Interrupt request bit is set to “1”
Note: When an internal clock is selected, pin SOUT is at high-impedance after transfer is completed.
Fig. 2.7.6 Timing diagram of serial I/O
7220 Group User’s Manual
2-45
FUNCTIONAL DESCRIPTION
2.7 Serial I/O
The transmit side in Figure 2.7.7, P21 is set as the serial I/O data output pin and P2 0 is set as the serial
I/O synchronous clock output pin by the initialization program.
The receive side, P21 is set as the serial I/O data input pin and P2 0 is used for the serial I/O synchronous
clock (external clock) input pin by the initialization program.
Figure 2.7.8 shows the serial data transmit/receive processing sequence using the above structure.
Receive Side
Transmit Side
Serial I/O Mode Register
Serial I/O Mode Register
b7
b7
b0
b0
1
0 1 1
0 1 0
Internal synchronous clock selection bits
Internal synchronious clock selection bits
Synchronous clock selection bit
1: Internal clock
Synchronous clock selection bit
0: External clock
Serial I/O port selection bit
1: SCLK, SOUT
Serial I/O port selection bit
1: SCLK, SOUT
Fix this bit to “0.”
Transfer direction selection bit
Fix this bit to “0.”
Transfer direction selection bit
Serial input pin selection bit
Serial input pin selection bit
1: Input signal from SOUT pin
Nothig is assigned.
Nothig is assigned.
Synchronous clock
P20/SCLK
P21/SOUT
SCLK/P20
Serial data
SOUT/P21
M37221M6-XXXSP/FP
M37221M6-XXXSP/FP
Fig. 2.7.7 Connection example for serial I/O transmit/receive
Receive side
Transmit side
LDM
CLB
#$0C, $DC
2, $FD
SEB
2, $FF
LDM
; Set serial I/O mode register.
; Reset serial I/O interrupt
request bit.
; Set the serial I/O interrupt
enable bit to “1.”
LDM
#$48, $DC
CLB
2, $FD
SEB
2, $FF
#DATA, $DD ; Write transfer data to serial ▼LDM
I/O register.
#$FF, $DD
; Set serial I/O mode
register.
; Reset serial I/O interrupt
request bit.
; Set serial I/O interrupt
enable bit to “1.”
; Write dummy data to
serial I/O register.
As a result of the above processing 1-byte data is transferred from the transmit side to the receive side.
When the transmit operation is completed, interrupts occur on both sides, so that completion of the data
transfer can be reported.
After that, repeating the processing after the symbol (▼) can transmit/receive more data.
Fig. 2.7.8 Serial data transmit/receive processing sequence
2-46
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.8 Multi-master I2C-BUS interface
2.8 Multi-master I 2C-BUS interface
The multi-master I 2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS
data transfer format. This interface, offering both an arbitration lost detection and a synchronous functions,
is useful for the multi-master serial communications.
Figure 2.8.1 shows a block diagram of the multi-master I 2C-BUS interface and Table 2.8.1 shows multimaster I2C-BUS interface functions.
The M37220M3-XXSP/FP does not have this function.
Table 2.8.1 Multi-master I2C-BUS interface functions
Function
Item
2
In conformity with Philips I C-BUS standard:
Format
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I2C-BUS standard:
Master transmission
Communication mode
Master reception
Slave transmission
Slave reception
SCL clock frequency
16.1 kHz to 400 kHz (at f = 4 MHz)
f : System clock = f(XIN)/2
Note: We are not responsible for any third party’s infringement of patent rights or other rights attributable
to the use of the control function (bits 6 and 7 of the I 2 C control register at address 00DA 16 ) for
connections between the I 2C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2).
7220 Group User’s Manual
2-47
FUNCTIONAL DESCRIPTION
2.8 Multi-master I2C-BUS interface
I 2 C address register
b7
b0
Interrupt
generating
circuit
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
S0D
Interrupt
request signal
(IICIRQ)
Address comparator
Serial
data
(SDA)
Noise
elimination
circuit
Data
control
circuit
b7
b0
I 2 C data shift register
b7
S0
b0
AL AAS AD0 LRB
MST TRX BB PIN
S1
AL
circuit
I 2 C status
register
Internal data bus
BB
circuit
Serial
clock
(SCL)
Noise
elimination
circuit
Clock
control
circuit
b7
ACK
b0
ACK
BIT
b7
FAST
MODE CCR4 CCR3 CCR2 CCR1 CCR0
BSEL1 BSEL0
S2
I 2 C clock control register
Clock division
b0
10BIT
SAD
ALS
ESO BC2 BC1 BC0
S1D I 2 C control register
System clock (φ)
Bit counter
Fig. 2.8.1 Block diagram of multi-masteer I2C-BUS interface
2.8.1 Construction of multi-master I2C-BUS interface
The multi-master I 2C-BUS interface consists of the following :
● I 2C address register
● I 2C data shift register
● I 2C clock control register
● I 2C control register
● I 2C status register
● Other control circuits
The data transfer with the internal CPU is performed via data bus, the data transfer with an external device
is performed via ports P1 1–P1 4. When using multi-master I 2C-BUS interface, these ports P1 1–P1 4 are
assigned to the following functions.
●
●
●
●
P1 1:
P1 2:
P1 3:
P1 4:
Multi-master
Multi-master
Multi-master
Multi-master
I2C-BUS
I2C-BUS
I 2C-BUS
I 2C-BUS
interface
interface
interface
interface
Synchronous clock input/output pin 1 (SCL1)
Synchronous clock input/output pin 2 (SCL2)
data input/output pin 1 (SDA1)
data input/output pin 2 (SDA2)
The shift clock to determine the transfer speed of serial data is selected by the I 2C clock control register
(refer to “Figure 2.8.4”).
A serial data and a serial clock is referred as “SDA,” “SCL” respectively, hereafter.
2-48
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.8 Multi-master I2C-BUS interface
2.8.2 Multi-master I2C-BUS interface-related registers
(1) I2C data shift register (S0: address 00D716)
The I 2C data shift register (S0 : address 00D7 16) is an 8-bit shift register to store receive data and
write transmit data.
When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization
with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit
to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL
clock, and each time one-bit data is input, the data of this register are shifted one bit to the left.
The I2C data shift register is in a write enable status only when the ESO bit of the I2C control register
(address 00DA 16) is “1.” The bit counter is reset by a write instruction to the I2C data shift register.
When both the ESO bit and the MST bit of the I2C status register (address 00F916) are “1,” the SCL
is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift
register is always enabled regardless of the ESO bit value.
Figure 2.8.2 shows the I 2C data shift register.
2
I C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
2
I C data shift register (S0) [Address 00D716]
B
0
to
7
Name
Functions
D0 to D7
This is an 8-bit shift register to store
receive data and write transmit data.
After reset
R W
Indeterminate R W
Note: To write data into the I2C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
Fig. 2.8.2 I 2C data shift register
7220 Group User’s Manual
2-49
FUNCTIONAL DESCRIPTION
2.8 Multi-master I2C-BUS interface
(2) I2C address register (S0D: address 00D816)
The I 2C address register (address 00D816) consists of a 7-bit slave address and a read/write bit. In
the addressing mode, the slave address written in this register is compared with the address data
to be received immediately after the START condition are detected.
■ Bit 0: Read/write bit (RBW)
Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode,
the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the
I2C address register.
The RBW bit is cleared to “0” automatically when the stop condition is detected.
■ Bits 1 to 7: Slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing
mode, the address data transmitted from the master is compared with the contents of these bits.
Figure 2.8.3 shows the I 2C address register.
I2C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C address register (S0D) [Address 00D816]
B
Name
Functions
0
Read/write bit
(RBW)
0: Read
1: Write
0
R W
1
to
7
Slave address
(SAD0 to SAD6)
The address data transmitted from
the master is compared with the
contents of these bits.
0
R W
Fig. 2.8.3 I2C address register
2-50
After reset R W
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.8 Multi-master I2C-BUS interface
(3) I2C clock control register (S2: address 00DB 16)
The I 2C clock control register (address 00DB16) is used to set ACK control, SCL mode and SCL
frequency.
■ Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency. Refer to “Table 2.8.4.”
■ Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the standard clock mode is set. When
the bit is set to “1,” the high-speed clock mode is set.
■ Bit 6: ACK bit (ACK BIT)
This bit sets the SDA status when an ACK clock ✽ is generated. When this bit is set to “0,” the ACK
return mode is set and SDA goes to LOW at the occurrence of an ACK clock. When the bit is set
to “1,” the ACK non-return mode is set. The SDA is held in the HIGH status at the occurrence of
an ACK clock.
However, when the slave address matches the address data in the reception of address data at
ACK BIT = “0,” the SDA is automatically made LOW (ACK is returned). If there is a mismatch
between the slave address and the address data, the SDA is automatically made HIGH (ACK is
not returned).
✽ACK clock: Clock for acknowledgment
■ Bit 7: ACK clock bit (ACK)
This bit specifies a mode of acknowledgment which is an acknowledgment response of data
transmission. When this bit is set to “0,” the no ACK clock mode is set. In this case, no ACK clock
occurs after data transmission. When the bit is set to “1,” the ACK clock mode is set and the
master generates an ACK clock upon completion of each 1-byte data transmission. The device for
transmitting address data and control data releases the SDA at the occurrence of an ACK clock
(make SDA HIGH) and receives the ACK bit generated by the data receiving device.
Figure 2.8.4 shows the I 2C clock control register.
Note: Do not write data into the I2C clock control register during transmission. If data is written during
transmission, the I 2C clock generator is reset, so that data cannot be transmitted normally.
7220 Group User’s Manual
2-51
FUNCTIONAL DESCRIPTION
2.8 Multi-master I2C-BUS interface
I2C Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0
I2 C clock control register (S2 : address 00DB 16)
B
0
to
4
Name
Functions
SCL frequency control bits Setup value of Standard clock
(CCR0 to CCR4)
CCR4–CCR0
mode
00 to 02
After reset R W
High speed
clock mode
0
R W
Setup disabled Setup disabled
03
Setup disabled
04
Setup disabled
333
250
05
100
400 (See note)
06
83.3
166
...
500/CCR value
1000/CCR value
1D
17.2
34.5
1E
16.6
33.3
1F
16.1
32.3
(at φ = 4 MHz, unit : kHz)
5
SCL mode
specification bit
(FAST MODE)
0 : Standard clock mode
1 : High-speed clock mode
0
R W
6
ACK bit
(ACK BIT)
0 : ACK is returned.
1 : ACK is not returned.
0
R W
7
ACK clock bit
(ACK)
0 : No ACK clock
1 : ACK clock
0
R W
Note: At 4000kHz in the high-speed clock mode, the duty is as below .
“0” period : “1” period = 3 : 2
In the other cases, the duty is as below.
“0” period : “1” period = 1 : 1
Fig. 2.8.4 I 2C clock control register
2-52
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.8 Multi-master I2C-BUS interface
(4) I2C Control Register (S1D: address 00DA16)
The I2C control register (address 00DA16) controls the data communication format.
■ Bits 0 to 2: Bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt
request signal occurs immediately after the number of bits specified with these bits are transmitted.
When a START condition is received, these bits become “0002” and the address data is always
transmitted and received in 8 bits.
■ Bit 3: I2C-BUS interface use enable bit (ESO)
This bit enables usage of the multi-master I2C-BUS interface. When this bit is set to “0,” the use
disable status is provided, so the SDA and the SCL become high-impedance. When the bit is set
to “1,” use of the interface is enabled.
When ESO = “0,” the following is performed.
• PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I2C status register at address
00F816).
• Writing data to the I2C data shift register (address 00D716 ) is disabled.
■ Bit 4: Data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses. When this bit is set to “0,” the
addressing format is selected, so that address data is recognized. When a match is found between
a slave address and address data as a result of comparison or when a general call (refer to “(5)
I2C Status Register,” bit 1) is received, transmission processing can be performed. When this bit
is set to “1,” the free data format is selected, so that slave addresses are not recognized.
■ Bit 5: Addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit is set to “0,” the 7-bit addressing
format is selected. In this case, only the high-order 7 bits (slave address) of the I2 C address
register (address 00D8 16) are compared with address data. When this bit is set to “1,” the 10-bit
addressing format is selected, all the bits of the I2C address register are compared with address
data.
■ Bit 6 and 7: Connection control bits between I 2C-BUS interface and ports (BSEL0, BSEL1)
This bits controls the connection between SCL and ports or SDA and ports. When using the ports
as multi-master I 2C-BUS interface, set the corresponding bits of port P1 direction register to “1”
(output mode).
Figure 2.8.5 shows the connection port control by BSEL0 and BSEL1, Figure 2.8.6 shows the I2C
control register.
“0”
“1” BSEL0
SCL1/P11
SCL
Multi-master
I2C-BUS
interface
SDA
“0”
“1” BSEL1
SCL2/P12
“0”
“1” BSEL0
SDA1/P1 3
“0”
“1” BSEL1
SDA2/P1 4
Fig. 2.8.5 Connection port control by BSEL0 and BSEL1
7220 Group User’s Manual
2-53
FUNCTIONAL DESCRIPTION
2.8 Multi-master I2C-BUS interface
I2C Control Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C control register (S1D : address 00DA 16)
B
Name
Functions
0
to
2
Bit counter
(Number of transmit/recieve
bits)
(BC0 to BC2)
b2
0
0
0
0
1
1
1
1
3
I2 C-BUS interface use
enable bit (ESO)
4
5
0
R W
0 : Disabled
1 : Enabled
0
R W
Data format selection bit
(ALS)
0 : Addressing mode
1 : Free data format
0
R W
Addressing format selection
bit (10BIT SAD)
0 : 7-bit addressing format
1 : 10-bit addressing format
0
R W
b7 b6 Connection port
0 0 : None
0 1 : SCL1, SDA1
1 0 : SCL2, SDA2
1 1 : SCL1, SDA1
SCL2, SDA2
0
R W
6, 7 Connection control bits
between I2C-BUS interface
and ports
(BSEL0, BSEL1)
b1
0
0
1
1
0
0
1
1
b0
0:
1:
0:
1:
0:
1:
0:
1:
After reset R W
8
7
6
5
4
3
2
1
Note: When using ports P1 1 -P14 as I 2 C-BUS interface, the output structure changes
automatically from CMOS output to N-channel open-drain output. However, set
the port direction register to “1” (output mode).
Fig. 2.8.6 I 2C control register
2-54
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.8 Multi-master I2C-BUS interface
(5) I 2C status register (S1: address 00D9 16)
The I2C status register (address 00D916) controls the I 2C-BUS interface status. The low-order 4 bits
are read-only bits and the high-order 4 bits can be read out and written to.
■ Bit 0: Last receive bit (LRB)
This bit stores the last bit value of received data and can also be used for ACK receive confirmation.
If ACK is returned when an ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned,
this bit is set to “1.” Except in the ACK mode, the last bit value of received data is input. The state
of this bit is changed from “1” to “0” by executing a write instruction to the I 2C data shift register
(address 00D7 16).
■ Bit 1: General call detecting flag (AD0)
This bit is set to “1” when a general call ✽ whose address data is all “0” is received in the slave
mode. By a general call of the master device, every slave device receives control data after the
general call. The AD0 bit is set to “0” by detecting the STOP condition or START condition.
■ Bit 2: Slave address comparison flag (AAS)
This flag indicates a comparison result of address data.
➀In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in
one of the following conditions.
• The address data immediately after occurrence of a START condition matches the slave address
stored in the high-order 7 bits of the I2C address register (address 00D816).
• A general call is received.
➁In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1”
with the following condition.
• When the address data is compared with the I2C address register (8 bits consists of slave
address and RBW), the first bytes match.
➂The state of this bit is changed from “1” to “0” by executing a write instruction to the I2C data
shift register (address 00D716).
■ Bit 3: Arbitration lost ✽ detecting flag (AL)
In the master transmission mode, when a device other than the microcomputer sets the SDA to
LOW by any other device, arbitration is judged to have been lost, so that this bit is set to “1.” At
the same time, the TRX bit is set to “0,” so that immediately after transmission of the byte, whose
arbitration was lost is completed, the MST bit is set to “0.” When arbitration is lost during slave
address transmission, the TRX bit is set to “0” and the reception mode is set. Consequently, it
becomes possible to receive and recognize its own slave address transmitted by another master
device.
✽Arbitration lost: The status in which communication as a master is disabled.
7220 Group User’s Manual
2-55
FUNCTIONAL DESCRIPTION
2.8 Multi-master I2C-BUS interface
■ Bit 4: I 2C-BUS interface interrupt request bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of
the PIN bit changes from “1” to “0.” At the same time, an interrupt request signal is sent to the
CPU. The PIN bit is set to “0” in synchronization with a falling edge of the last clock (including the
ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a
falling edge of the PIN bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock
generation is disabled. Figure 2.8.7 shows an interrupt request signal generating timing chart.
The PIN bit is set to “1” in any one of the following conditions.
• Executing a write instruction to the I 2C data shift register (address 00D7 16).
• When the ESO bit is “0”
• At reset
The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (including when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately after completion of slave address
or general call address reception
• In the slave reception mode, with ALS = “1” and immediately after completion of address data
reception
■ Bit 5: Bus busy flag (BB)
This bit indicates the status of use of the bus system. When this bit is set to “0,” this bus system
is not busy and a START condition can be generated. When this bit is set to “1,” this bus system
is busy and the occurrence of a START condition is disabled by the START condition duplication
prevention function (Note).
This flag can be written by software only in the master transmission mode. In the other modes, this
bit is set to “1” by detecting a START condition and set to “0” by detecting a STOP condition. When
the ESO bit of the I 2C control register (address 00DA16) is “0” and at reset, the BB flag is kept in
the “0” state.
■ Bit 6: Communication mode specification bit (transfer direction specification bit: TRX)
This bit decides the direction of transfer for data communication. When this bit is “0,” the reception
mode is selected and the data of a transmitting device is received. When the bit is “1,” the
transmission mode is selected and address data and control data are output into the SDA in
synchronization with the clock generated on the SCL.
When the ALS bit of the I2C control register (address 00F916) is “0” in the slave reception mode
is selected, the TRX bit is set to “1” (transmit) if the least significant bit (R/W bit) of the address
data transmitted by the master is “1.” When the ALS bit is “0” and the R/W bit is “0,” the TRX bit
is cleared to “0” (receive).
The TRX bit is cleared to “0” in one of the following conditions.
• When arbitration lost is detected.
• When a STOP condition is detected.
• When occurrence of a START condition is disabled by the START condition duplication prevention
function (Note).
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset
2-56
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.8 Multi-master I2C-BUS interface
■ Bit 7: Communication mode specification bit (master/slave specification bit: MST)
This bit is used for master/slave specification for data communication. When this bit is “0,” the
slave is specified, so that a START condition and a STOP condition generated by the master are
received, and data communication is performed in synchronization with the clock generated by the
master. When this bit is “1,” the master is specified and a START condition and a STOP condition
are generated, and also the clocks required for data communication are generated on the SCL.
The MST bit is cleared to “0” in one of the following conditions.
• Immediately after completion of 1-byte data transmission when arbitration lost is detected
• When a STOP condition is detected.
• When occurrence of a START condition is disabled by the START condition duplication preventing
function (Note).
• At reset
Figure 2.8.7 shows the interrupt request signal generating timing, Figure 2.8.8 shows the I 2C status
register.
Note: The START condition duplication prevention function disables the START condition generation,
reset of bit counter reset, and SCL output when the following condition is satisfied:
a START condition is set by another master device.
SCL
PIN
IICIRQ
Fig. 2.8.7 Interrupt request signal generating timing
I2C Status Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address 00D916]
B
Name
Functions
0
Last receive bit (LRB)
(See note)
0 : Last bit = “0 ”
1 : Last bit = “1 ”
1
General call detecting flag
(AD0) (See note)
2
After reset R W
Indeterminate
R —
0 : No general call detected
1 : General call detected
0
R —
Slave address comparison
flag (AAS) (See note)
0 : Address mismatch
1 : Address match
0
R —
3
Arbitration lost detecting flag
(AL) (See note)
0 : Not detected
1 : Detected
0
R —
4
I2C-BUS interface interrupt
request bit (PIN)
0 : Interrupt request issued
1 : No interrupt request issued
1
R W
5
Bus busy flag (BB)
0 : Bus free
1 : Bus busy
0
R W
b7
0
0
1
1
0
R W
6, 7 Communication mode
specification bits
(TRX, MST)
b6
0 : Slave recieve mode
1 : Slave transmit mode
0 : Master recieve mode
1 : Master transmit mode
Note : These bits and flags can be read out, but cannnot be written.
Fig. 2.8.8 I2C status register
7220 Group User’s Manual
2-57
FUNCTIONAL DESCRIPTION
2.8 Multi-master I2C-BUS interface
2.8.3 START condition, STOP condition generation method
(1) START condition generation method
When the ESO bit of the I 2C control register (address 00DA16) is “1,” execute a write instruction to
the I2C status register (address 00D916) to set the MST, TRX and BB bits to “1.” A START condition
will then be generated. After that, the bit counter becomes “0002” and an SCL for 1 byte is output.
The START condition generating timing and BB bit set timing are different in the standard clock mode
and the high-speed clock mode. Refer to “Figure 2.8.9” for the START condition generation timing
diagram, and “Table 2.8.2” for the START condition/STOP condition generation timing table.
(2) STOP condition generation method
When the ESO bit of the I 2C control register (address 00DA16) is “1,” execute a write instruction to
the I 2C status register (address 00D916) for setting the MST bit and the TRX bit to “1” and the BB
bit to “0”. A STOP condition will then be generated. The STOP condition generation timing and the
BB flag reset timing are different in the standard clock mode and the high-speed clock mode. Refer
to “Figure 2.8.10” for the STOP condition generating timing diagram, and “Table 2.8.2” for the
START condition/STOP condition generation timing table.
I2C status register
write signal
SCL
SDA
Setup
time
Hold time
Set time for
BB flag
BB flag
Setup
time
Fig. 2.8.9 START condition generation timing diagram
I2C status register
write signal
SCL
SDA
BB flag
Setup
time
Hold time
Reset time for
BB flag
Fig. 2.8.10 STOP condition generation timing diagram
Table 2.8.2 START condition/STOP condition generation timing table
Standard clock mode
Item
High-speed clock mode
5.0 µ s (20 cycles)
Setup time
2.5 µ s (10 cycles)
5.0 µ s (20 cycles)
Hold time
2.5 µ s (10 cycles)
3.0 µ s (12 cycles)
Set/reset time for BB flag
1.5 µ s (6 cycles)
Note: Absolute time at f = 4 MHz. The value in parentheses denotes the number of f cycles.
2-58
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.8 Multi-master I2C-BUS interface
(3) START/STOP condition detect conditions
The START/STOP condition detect conditions are shown in Figure 2.8.11 and Table 2.8.3. Only when
the 3 conditions of Table 10 are satisfied, a START/STOP condition can be detected.
Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal
“IICIRQ” is generated to the CPU.
SCL release time
SCL
SDA
(START condition)
Setup
time
Hold time
Setup
time
Hold time
SDA
(STOP condition)
Fig. 2.8.11 START condition/STOP condition detect timing diagram
Table 2.8.3 START condition/STOP condition detect conditions
Standard clock mode
6.5 µ s (26 cycles) < SCL release time
3.25 µ s (13 cycles) < Setup time
High-speed clock mode
1.0 µ s (4 cycles) < SCL release time
0.5 µ s (2 cycles) < Setup time
3.25 µ s (13 cycles) < Hold time
0.5 µ s (2 cycles) < Hold time
Note: Absolute time at f = 4 MHz. The value in parentheses denotes the number of f cycles.
7220 Group User’s Manual
2-59
FUNCTIONAL DESCRIPTION
2.8 Multi-master I2C-BUS interface
(4) Address Data Communication
There are two address data communication formats, namely, 7-bit addressing format and 10-bit
addressing format. The respective address communication formats is described below.
➀ 7-bit addressing format
To meet the 7-bit addressing format, set the 10BIT SAD bit of the I 2C control register (address
00DA16) to “0.” The first 7-bit address data transmitted from the master is compared with the highorder 7-bit slave address stored in the I 2C address register (address 00D816). At the time of this
comparison, address comparison of the RBW bit of the I 2C address register (address 00D8 16) is not
made. For the data transmission format when the 7-bit addressing format is selected, refer to
“Figure 2.8.12, (1) and (2).”
➁ 10-bit addressing format
To meet the 10-bit addressing format, set the 10BIT SAD bit of the I2C control register (address
00DA 16 ) to “1.” An address comparison is made between the first-byte address data transmitted
from the master and the 7-bit slave address stored in the I2C address register (address 00D816).
At the time of this comparison, an address
comparison between the RBW bit of the I2C address
__
register (address 00D8 16) and the R/W bit which is the last__
bit of the address data transmitted from
the master is made. In the 10-bit addressing mode, the R/W bit which is the last bit of the address
data not only specifies the direction of communication for control data but also is processed as an
address data bit.
When the first-byte address data matches the slave address, the AAS bit of the I 2C status register
(address 00D9 16) is set to “1.” After the second-byte address data is stored into the I 2C data shift
register (address 00D7 16), make an address comparison between the second-byte data and the
slave address by software. When the address data of the 2nd byte matches the slave address, set
the RBW bit of the I 2C address register
(address 00D816) to “1” by software. This processing can
__
match the 7-bit slave address and R/W data, which are received after a RESTART condition is
detected, with the value of the I 2C address register (address 00D8 16). For the data transmission
format when the 10-bit addressing format is selected, refer to “Figure 2.8.12, (3) and (4).”
S
Slave address R/W
A
Data
A
Data
A/A
P
A
P
Data
A
7 bits
“0”
1 to 8 bits
1 to 8 bits
(1) A master-transmitter transmits data to a slave-receiver
S
Slave address R/W
A
Data
A
Data
7 bits
“1”
1 to 8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
S
Slave address
R/W
1st 7 bits
A
Slave address
2nd byte
A
Data
A/A
P
1 to 8 bits
7 bits
“0”
8 bits
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
Slave address
R/W
1st 7 bits
A
Slave address
2nd byte
A
Sr
Slave address
R/W
1st 7 bits
Data
7 bits
“0”
8 bits
7 bits
“1” 1 to 8 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W: Read/Write bit
From master to slave
From slave to master
Fig. 2.8.12 Address data communication format
2-60
7220 Group User’s Manual
A
Data
1 to 8 bits
A
P
FUNCTIONAL DESCRIPTION
2.9 A-D comparator
2.9 A-D comparator
The M37221M6-XXXSP/FP has A-D comparator consists of the 6-bit D-A converter by resistance string
method and a comparator. Figure 2.9.1 shows the A-D comparator block diagram.
Data bus
A-D control register 1
Bits 0 to 2
P15/A-D1/INT3
P16/A-D2
P17/A-D3
P06/INT2/A-D4
P30/A-D5
P31/A-D6
Comparator control
A-D control
register 1
Analog
signal
switch
Comparator
Bit 4
Bit 5
A-D control
register 2
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Switch tree
Resistor ladder
Fig. 2.9.1 A-D comparator block diagram
The following explains A-D comparison method.
➀ Set “0” to corresponding bits of the direction register to use ports as analog input pins.
➁ Select the analog input pin with bits 0 to 2 of A-D control register 1 (address 00EE 16).
➂ Set the comparison voltage “Vref” for D-A conversion by bits 0 to 5 of A-D control register 2 (address
00EF 16). Table 2.9.1 shows the V ref values corresponding to the set values above.
A-D comparison starts by writing to A-D control register 2.
➃ This voltage comparison needs for 16 machine cycles (NOP instruction ✕ 8).
➄ The comparison result is stored in bit 4 of the A-D control register 1 (address 00EE16).
When the input voltage value is lower than the comparison voltage value, bit 4 is cleared to “0”; when the
input voltage value is higher than the comparison voltage value, bit 4 is set to “1” (refer to “Figure 2.9.2”).
7220 Group User’s Manual
2-61
FUNCTIONAL DESCRIPTION
2.9 A-D comparator
Table 2.9.1 Relationship between contents of A-D control register 2 and reference voltage “Vref”
A-D control register 2
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Internal analog voltage
(comparison voltage Vref)
0
0
0
0
0
0
1/128VCC
0
0
0
0
0
1
3/128VCC
0
:
0
:
0
:
0
:
1
:
0
:
5/128VCC
1
1
1
1
0
1
1
1
1
1
1
0
123/128VCC
125/128VCC
1
1
1
1
1
1
127/128VCC
:
A-D Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 1 (AD1) [Address 00EE16]
B
Name
Functions
0
to
2
Analog input pin selection
bits
(ADM0, ADM1, ADM2)
b2
0
0
0
0
1
1
1
1
b1
0
0
1
1
0
0
1
1
b0
0 : A-D1
1 : A-D2
0 : A-D3
1 : A-D4
0 : A-D5
1 : A-D6
0 : Do not set.
1:
3
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
4
Storage bit of comparison
result (ADM4)
5
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
0: Input voltage < reference voltage
1: Input voltage > reference voltage
After reset R W
0
R W
0
R —
Indeterminate
R W
0
R —
Fig. 2.9.2 A-D control register 1 (address 00EE 16)
A-D Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 2(AD2) [Address 00EF16]
B
0
to
5
Name
D-A converter set bits
(ADC0, ADC1, ADC2,
ADC3, ADC4, ADC5)
Functions
b5
0
0
0
b4
0
0
0
b3
0
0
0
b2
0
0
0
b1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
b0
0 : 1/128Vcc
1 : 3/128Vcc
0 : 5/128Vcc
2-62
7220 Group User’s Manual
R W
0
R W
0
R —
1 : 123/128Vcc
0 : 125/128Vcc
1 : 127/128Vcc
6, 7 Nothing is assigned. These bits are write disable bits.
When these bits are reed out, the values are “ 0.”
Fig. 2.9.3 A-D control register 2 (address 00EF 16)
After reset
FUNCTIONAL DESCRIPTION
2.10 PWM
2.10 PWM
The M37221M6-XXXSP/FP has one 14-bit PWM (pulse width modulator) [DA], and six 8-bit PWM [PWM0–
PWM5].
Table 2.10.1 shows the PWM function performance.
Table 2.10.1 PWM function performance (at oscillation frequency = 8 MHz)
Performance
14-bit PWM [DA]
Resolution (bits)
14
Minimum resolution bit width (µ s)
8-bit PWM
8
0.25
4096
Repeat cycle (µ s)
4
1024
Figure 2.10.1 shows the 14-bit PWM block diagram and Figure 2.10.2 shows the 8-bit PWM block diagram.
Data bus
DA-H register
(Address : 00CE16 )
b7
b0
DA-L register (Note)
(Address : 00CF16 )
DA latch
(14 bits)
MSB
LSB
6
8
14
6
PN2
PN4
14-bit PWM circuit
DA
D-A
PW1
XIN
PWM timing
generating
circuit
1/2
PW0
Selection gate :
Connected to
black side when
reset.
Pass gate
Inside of
with the others.
PW: PWM output control register 1
PN: PWM output control register 2
Note: The DA-L register also functions as the low-order 6 bits of the DA latch.
Fig. 2.10.1 14-bit PWM (DA) block diagram
7220 Group User’s Manual
2-63
FUNCTIONAL DESCRIPTION
2.10 PWM
Data bus
XIN
PWM timing
generating
circuit
1/2
PW0
PWM register
16))
(Address : 00D016
b7
b0
8
PN3
P00
D00
PWM0
PW2
P01
D01
PWM1
D02
PWM2
D03
PWM3
D04
PWM4
D05
PWM5
8-bit PWM circuit
PWM1 register (Address : 00D116)
PW3
P02
Selection gate :
Connected to
black side when
reset.
PWM2 register (Address : 00D2 16)
P03
PWM3 register (Address : 00D3 16)
Inside of
with the others.
PW5
P04
is as same contents
PWM4 register (Address : 00D4 16)
PW6
P05
PW: PWM output control register 1
PN: PWM output control register 2
D0: Port P0 direction register
PW4
PWM5 register (Address : 00F616 )
PW7
Fig. 2.10.2 8-bit PWM block diagram
2.10.1 8-bit PWM registers (addresses 00D016 to 00D416 and 00F616)
/DA registers (addresses 00CE 16 and 00CF16)
Data transfer from the 8-bit PWM registers (addresses 00D0 16 to 00D4 16 and 00F6 16) to the 8-bit PWM
circuit is executed when writing data to the registers. The output signal from the 8-bit PWM output pin
corresponds to the contents of this register.
Also, data transfer from the DA registers (addresses 00CE 16 and 00CF 16) to the 14-bit PWM circuit is
executed when writing data to the DA-L register (address 00CF 16). The output signal from the D–A output
pin corresponds to the contents of the DA latch.
Reading from the DA register (address 00CE16) means the DA latch contents. Therefore, it is possible to
confirm the data being output from the D-A output pin by reading the DA register.
The contents of the 8-bit PWM register and DA register are indeterminate after reset.
2-64
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.10 PWM
2.10.2 14-bit PWM (DA output)
The 14-bit PWM automatically outputs a PWM rectangular waveform from the D-A pin by writing high-order
8 bits of the output data to the DA-H register and the low-order 6 bits to the DA-L register. Data of the
DA-H register are transferred to the 14-bit PWM circuit when writing to the DA-L register.
The following explains the output operation of 14-bit PWM rectangular waveform (when f(X IN) = 8 MHz).
➀The repeat cycle “T” (4,096 µ s) of output waveform is divided into 2 6 = 64 smaller interval “t” (t =
64 µ s). The “t” is further divided into the minimum resolution bit “τ” of 2 8 = 256 (τ = 0.25 µ s).
➁The HIGH duration of the fundamental waveform is determined by the high-order 8 bits “DH” of the DA
latch.
HIGH duration (time) = τ ✕ D H (when f(X IN) = 8 MHz, 0.25DH µ s)
Because the D H values are “0” to “255,” the HIGH duration can be selected a total of 256.
➂The smaller interval “t m” with a longer HIGH level area by “τ” is specified by the low-order 6 bits “DL” of
the DA latch. The t m is specified from among 64 smaller intervals (t 0 to t 63).
Therefore, a rectangular waveform consisted of 2-kind waveforms with different HIGH duration are output
from pin D–A (a length of entirely HIGH output cannot be output).
Figure 2.10.3 shows the 14-bit PWM output example, Table 2.10.2 shows the relation between DL and tm
(m = “0” to “63”).
Table 2.10.2 The relation between DL and t m ( m = “0” to “63”)
Low-order 6-bit data of DA register (D L)
MSB
0 0 0 0 0 0
LSB
Smaller intervals that HIGH duration is longer by τ
t m ( m = “0” to “63”)
Number
Nothing
0
0 0 0 0 0 1
m = 32
1
0 0 0 0 1 0
m = 16, 48
0 0 0 0 1 1
m = 16, 32, 48
2
3
0 0 0 1 0 0
0 0 0 1 0 1
m = 8, 24, 40, 56
4
m = 8, 24, 32, 40, 56
m = 8, 16, 24, 40, 48, 56
5
0 0 0 1 1 0
6
:
:
:
0 0 1 0 0 0
m = 4, 12, 20, 28, 36, 44, 52, 60
8
:
:
:
0 1 0 0 0 0
:
m = 2, 6, 10, 14, 18, ... 46, 50, 54, 58, 62
1 0 0 0 0 0
m = 1, 3, 5, 7, 9 ... 55, 57, 59, 61, 63
:
1 0 1 0 0 0
:
1 1 1 1 1 1
:
:
m = 1, 3, 5, 7, 9 ... 52, 55, 57, 59, 60, 61, 63
:
m = 1 to 63 (“0” is not included)
7220 Group User’s Manual
16
:
32
:
40
:
63
2-65
FUNCTIONAL DESCRIPTION
2.10 PWM
Set “2816” to DA-L register.
Set “2C 16” to DA-H register.
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
[DA-H
0 0 1 0 1 1 0 0 DH
register]
1
[DA-L register]
0
1
0
0
0
DL
Undefined
At writing of DA-L
At writing of DA-L
b13
[DA latch]
0
b6 b5
0
1
0
1
1
0
0
These bits decide HIGH level area
of fundamental waveform.
HIGH level area of
fundamental waveform
=
Minimum
resolution bit
width 0.25 µs
✕
1
b0
0
1
0
0
0
These bits decide smaller interval “tm” in which HIGH level
area is [HIGH level area of fundamental waveform + τ ].
High-order 8-bit
value of DA latch
Fundamental
waveform
Waveform of smaller interval “tm” specified by low-order 6 bits
0.25 µs ✕ 44
0.25 µs ✕ 45
0.25 µs
14-bit
PWM output 2C 2B 2A … 03 02 01 00
14-bit
PWM output 2C 2B 2A … 03 02 01 00
8-bit
counter
8-bit
counter
FF FE FD … D6 D5 D4 D3 … 02 01 00
FF FE FD … D6 D5 D4 D3 … 02 01 00
Fundamental waveform of smaller interval
“tm” which is not specified by low-order 6
bits is not changed.
τ = 0.25 µs
0.25 µs ✕ 44
14-bit PWM output
t0
t1
t2
t3
t4
t5
t59
Low-order 6-bit output
of DA latch
Repeat period
T = 4096 µs
Fig. 2.10.3 14-bit PWM output example (f(X IN) = 8 MHz)
2-66
7220 Group User’s Manual
t60
t61
t62
t63
FUNCTIONAL DESCRIPTION
2.10 PWM
2.10.3 8-bit PWM (PWM0 to PWM5: address 00D0 16 to 00D416 and 00F6 16 )
The 8-bit PWM outputs waveform which is the logical sum (OR) of pulses corresponding to bits 0 to 7 of
the 8-bit PWM register.
That is to say, 8 kinds of pulses corresponding to the weight of each bit of the 8-bit PWM register are
output inside the circuit during 1 cycle. Among these pulses, OR of pulses that correspond to bits, which
is set to “1,” in the 8-bit PWM register to external devices as PWM output.
Figure 2.10.4 shows the pulse waveforms corresponding to the weight of each bit of the 8-bit PWM register.
Figure 2.10.5 shows the example of 8-bit PWM output.
As shown in the Figures, 256 kinds of output (HIGH duration: 0/256 to 255/256) are selected by changing
the contents of the PWM register (a length of entirely HIGH cannot be output).
7220 Group User’s Manual
2-67
2-68
Fig. 2.10.4 Pulse waveforms corresponding to weight
of each bit of 8-bit PWM register
7220 Group User’s Manual
FF16(255)
1816(24)
0116(1)
0016(0)
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
t
2
4
6
8
60
80
110
120
130
140
150
160
170
180
190
200
210
220
230
240
5
250 255
100
104
108
128
132
136
T = 256 t
120
124
140
144
t = 4 µs T = 1024 µs
f(XIN) = 8 MHz
112
116
148
152
156
160
164
168
172
176
180
184
188
192
196
200
204
208
212
216
224
220
228
232
236
240
244
248
252
98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254
96
94
100
PWM output
92
90
90
88
86
84
82
80
78
76
74
72
70
70
68
66
64
62
60
58
56
54
52
50
50
48
46
44
42
40
40
38
36
34
32
30
30
28
26
24
22
20
20
18
16
14
12
10
13579
FUNCTIONAL DESCRIPTION
2.10 PWM
Fig. 2.10.5 Example of 8-bit PWM output
FUNCTIONAL DESCRIPTION
2.10 PWM
2.10.4 14-bit PWM output control
How to control the 14-bit PWM output is described below.
➀ Set “0” to bit 0 of PWM output control register 1 (address 00D5 16) to supply the PWM count source (this
bit is cleared to “0” when reset).
➁ Set the high-order 8 bits of the output data to the DA-H register.
➂ Set the low-order 6 bits of the output data to the DA-L register.
➃ Data is written to the 14-bit PWM circuit by writing data to the DA-L register.
For this reason, even when changing only the high-order 8 bits of the output data, be sure to write the
low-order 6 bits data to the DA-L register again.
Conversely, when changing low-order 6 bits only, it needs to only write data to the DA-L register, and
needs not write the high-order 8-bit data again.
➄ Select the output polarity by bit 2 of PWM output control register 2 (address 00D616). When setting to
“0,” a positive polarity is selected; when “1,” a negative polarity is selected.
➅ 14-bit PWM is output from the D-A pin by clearing bit 1 of PWM output control register 1 to “0.” When
setting to “1,” pin D-A functions as a 1-bit general-purpose output port. In this case, it is possible to
specify either HIGH output (= “1”) or LOW output(= “0”) output by bit 4 of PWM output control register
2.
PWM Output Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
PWM output control register 1 (PW) [Address 00D516]
B
Name
Functions
0 DA, PWM count source 0 : Count source supply
1 : Count source stop
selection bit (PW0)
After reset R W
R W
0
1
DA/PN4 output
selection bit (PW1)
0 : DA output
1 : PN4 output
0
R W
2
P00/PWM0 output
selection bit (PW2)
0: P00 output
1: PWM0 output
0
R W
3
P01/PWM1 output
selection bit (PW3)
0: P01 output
1: PWM1 output
0
R W
4
P02/PWM2 output
selection bit (PW4)
0: P02 output
1: PWM2 output
0
R W
5
P03/PWM3 output
selection bit (PW5)
0: P03 output
1: PWM3 output
0
R W
6
P04/PWM4 output
selection bit (PW6)
0: P04 output
1: PWM4 output
0
R W
7
P05/PWM5 output
selection bit (PW7)
0: P05 output
1: PWM5 output
0
R W
Fig. 2.10.6 PWM output control register 1 (address 00D516)
7220 Group User’s Manual
2-69
FUNCTIONAL DESCRIPTION
2.10 PWM
2.10.5 8-bit PWM output control
How to control the 8-bit PWM output is described below.
The PWM0–PWM7 output pins are also used for port P00–P0 3 and P6 0–P6 3.
➀ Set “0” to bit 0 of the PWM output control register 1 (address 00D516) to supply the PWM count source
(this bit is cleared to “0” after reset).
➁ Write output data to the corresponding 8-bit PWM registers (addresses 00D016 to 00D4 16 and 00F6 16).
➂ Set the corresponding bit of the port P0 direction register to “1” to specify the output mode.
➃ Select the output polarity by bit 3 of the PWM output control register 2 (address 00D6 16). When this bit
is cleared to “0,” a positive polarity is selected; when set to “1,” a negative polarity is selected.
➄ By setting “1” to the corresponding bits among bits 2 to 7 of the PWM output control register 1, the pins
are given the PWM output function to output the PWM. When clearing to “0,” the pins become generalpurpose ports (ports P00–P0 5).
PWM Output Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
PWM output control register 2 (PN) [Address 00D6 16]
B
Name
Functions
After reset R W
0, 1 Nothing is assigned. These bits are write disable bits.
0
R —
When these bits are read out, the values are “0.”
2
DA output polarity
selection bit (PN3)
0 : Positive polarity
1 : Negative polarity
0
R W
3
PWM output polarity
selection bit (PN4)
0 : Positive polarity
1 : Negative polarity
0
R W
4
DA general-purpose
output bit (PN5)
0 : Output LOW
1 : Output HIGH
0
R W
0
R —
5 Nothing is assigned. These bits are write disable bits.
to When these bits are read out, the values are “0.”
7
Fig. 2.10.7 PWM output control register 2 (address 00D616)
2-70
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.11 CRT display function
2.11 CRT display function
Table 2.11.1 shows the outline the CRT display function of the M37221M6-XXXSP/FP.
M37220M3-XXXSP/FP
Refer to “CHAPTER 4. M37220M3-XXXSP/FP.”
The M37221M6-XXXSP/FP has the 24 characters ✕ 2 lines CRT display circuit. CRT display is controlled
by the CRT control register.
Up to 256 kinds of characters can be displayed, and colors can be specified for each character. Up to 4
kinds of colors can be displayed on 1 screen. A combination of up to 7 colors can be obtained by using each
output signal (R, G, and B). Characters are displayed in a 12 ✕ 16 dot structure to display smooth character
patterns (refer to “Figure 2.11.1”).
How to display characters on the CRT screen is described below.
➀ Write the display character code in the display RAM.
➁ Specify the display color by the color register.
➂ Write the color register in which the display color is set in the display RAM.
➃ Specify the vertical position by the vertical position register.
➄ Specify the character size by the character size register.
➅ Specify the horizontal position by the horizontal position register.
➆ Write the display control bit to the designated block display flag of the CRT control register. When this
is done, the CRT starts according to the input of the VSYNC signal.
The CRT display circuit has an extended display mode. This mode allows multi-line (more than 3 lines) to
be displayed on the screen by interrupting each time 1 line is displayed and rewriting data in the block which
display is terminated by software.
Figure 2.11.2 shows the CRT display circuit block diagram. Figure 2.11.3 shows the CRT control register.
Table 2.11.1 Outline of CRT display function
Parameter
Performance
Number of display
24 characters ✕ 2 lines
character
12 dots
Dot structure
12 dots ✕ 16 dots
(Refer to “Figure 2.11.1”)
Kinds of character
16 dots
256 kinds
Kinds of character sizes 3 kinds
Kind of colors 1 screen; 4 kinds, maximum 7 kinds
Color
Coloring unit A character
Display extension
Possible (multi-line display)
Raster coloring
Possible (maximum 7 kinds)
Character background
Possible (a character unit, 1
screen; 4 kinds, maximum 7 kinds)
coloring
Fig. 2.11.1 Structure of CRT display character
7220 Group User’s Manual
2-71
FUNCTIONAL DESCRIPTION
2.11 CRT display function
OSC1
OSC2
HSYNC VSYNC
(Address 00EA 16)
CRT control register
Display oscillation
circuit
(Addresses 00E1 16, 00E216)
Vertical position registers
(Address 00E4 16)
Character size register
Display position control circuit
(Address 00E0 16)
Horizontal position register
(Address 00E5 16)
Border selection register
Display control
circuit
RAM for display
10 bits ✕ 24 characters ✕
2 lines
ROM for display
12 bits ✕ 16 dots ✕
256 characters
(Addresses 00E6 16
to 00E9 16)
Shift register
12 bits
Color registers
Shift register
12 bits
(Address 00EC 16)
Output circuit
CRT port control register
Data bus
R
Fig. 2.11.2 CRT display circuit block diagram
2-72
7220 Group User’s Manual
G
B
OUT1 OUT2
FUNCTIONAL DESCRIPTION
2.11 CRT display function
CRT Control Register
b7 b6 b5 b4 b3 b2 b1 b0
CRT control register (CC) [Address 00EA16]
B
Functions
Name
After reset R W
0
All-blocks display control
bit (Note) (CC0)
0 : All-blocks display off
1 : All-blocks display on
0
R W
1
Block 1 display control bit
(CC1)
0 : Block 1 display off
1 : Block 1 display on
0
R W
2
Block 2 display control bit
(CC2)
0 : Block 2 display off
1 : Block 2 display on
0
R W
3
to
6
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
0
R —
7
P10 /OUT2 pin switch bit
(CC7)
0
R W
0 : P10
1 : OUT2
Note: Display is controlled by logical product (AND) between the all-blocks display
control bit and each block control bit.
Fig. 2.11.3 CRT control register (address 00EA 16)
7220 Group User’s Manual
2-73
FUNCTIONAL DESCRIPTION
2.11 CRT display function
2.11.1 Display position
The display positions of characters are specified in units called a “block”. There are 2 blocks, block 1 and
block 2. Up to 24 characters can be displayed in 1 block (refer to “2.11.3 Memory for display”).
The display position of each block in both horizontal and vertical directions can be set by software.
The horizontal direction is common to all blocks, and is selected from 64-step display positions in units of
4 TC (T C = oscillation cycle for display).
The display position in the vertical direction is selected from 128-step display positions for each block in
units of 4 scanning lines. The display position in the vertical direction is determined by counting the
horizontal sync signal (HSYNC).
At this time, it starts to count the rising edge (falling edge ✽) of HSYNC signal from after about 1 machine cycle
of rising edge (falling edge✽) of V SYNC signal. So interval from rising edge (falling edge✽ ) of HSYNC signal
needs enough time (2 machine cycles or more) for avoiding jitter.
✽:The polarity of H SYNC and V SYNC signals can select by the CRT port control register (address 00EC16).
When clearing corresponding bits to “0,” positive polarity is selected, when setting to “1,” negative
polarity is selected. Refer to “2.11.7 CRT output pin control” for detail.
VSYNC signal input
8 machine cycles or more (See note 4)
VSYNC control signal
in microcomputer
0.125 µs to 0.25 µs (See note 2)
Period of counting
HSYNC signal
(See note 3)
HSYNC signal input
8 machine cycles or more
(See note 4)
↑
↑
↑
↑
↑
↑
Not count
1
2
3
4
5
When bits 0 and 1 of the CRT port control register (address 00EC16)
are set to “1” (negative polarity)
Note 1: The vertical position is determined by counting falling
edge of HSYNC signal after rising edge of VSYNC control
signal in the microcomputer.
2: At f(XIN) = 8 MHz
3: Do not generate falling edge of HSYNC signal near rising edge
of VSYNC control signal in microcomputer to avoid jitter.
4: Pulse width of VSYNC and of HSYNC signals needs 8 machine
cycles or more.
Fig. 2.11.4 Count method of synchronous signal
2-74
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.11 CRT display function
The block 2 is displayed after the display of block 1 is completed (refer to “Figure 2.11.5 (a)”). Therefore,
set vertical display start position of block 2 to be lower than the display end position of block 1. The block
2 cannot display when the display position of block 2 is overlapped with the display position of block 1
(refer to “Figure 2.11.5 (b)”) or is higher than the display position of block 1 (refer to “Figure 2.11.5 (c)”).
Same as above, at the multiline display, the next block 1 cannot be displayed until the display of block 2
is completed. Therefore, set the display start position of the second and later block 1 to be lower than the
display position of the last block 2 (refer to “Figure 2.11.5 (d)”).
(HR)
(HR)
CV1
Block 1
Because the block 2 is
higher than the block 1, the
block 2 cannot be displayed.
CV2
CV2
Block 2
Block 2
CV1
Block 1
(c) Example when the block 2 is higher than the block 1.
(a) Example when each block is separated.
(HR)
(HR)
CV1
CV2
CV2
(last displayed) CV1
Block 1
Block 2
Block 1 (last display)
Block 2 (last display)
Block 1
Because the block 1 overlaps
with the last display of block 2,
the block 1 cannot be displayed.
Because the block 2 overlaps with
the block 1, the block 2 cannot be
displayed.
(b) Example when block 2 overlaps with block 1.
(d) Example when the block 1 overlaps with the last
display of block 2 at the multiline display.
Fig. 2.11.5 Display position
7220 Group User’s Manual
2-75
FUNCTIONAL DESCRIPTION
2.11 CRT display function
The vertical position can specify 128-step positions (4 scanning lines per step) for each block by setting
values “0016” to “7F16” to bits 0 to 6 of the vertical position registers (the blocks 1 and 2 are assigned to
addresses to 00E1 16, 00E2 16 respectively). Figure 2.11.6 shows the vertical position registers.
Vertical Position Register n
b7 b6 b5 b4 b3 b2 b1 b0
Vertical position register n (CV1,CV2) (n = 1 and 2) [Addresses 00E116, 00E216 ]
B
Name
Functions
0
to
6
Vertical display start positions
(CV1 : CV10 to CV16)
(CV2 : CV20 to CV26)
7
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
128 steps (00 16 to 7F16 )
After reset
R W
Indeterminate R W
0
R —
Fig. 2.11.6 Vertical position register n (addresses 00E1 16 and 00E2 16)
The horizontal direction is common to both blocks, and can specify 64-step display positions (4 TC per step,
TC: oscillation cycle for display) by setting values “00 16” to “3F 16” to bits 0 to 5 of the horizontal position
register (address 00E016).
Figure 2.11.7 shows the horizontal position register.
Horizontal Position Register
b7 b6 b5 b4 b3 b2 b1 b0
Horizontal position register (HR) [Address 00E016]
B
0
to
5
Name
Horizontal display start
positions (HR0 to HR5)
Functions
64 steps (0016 to 3F 16)
6, 7 Nothing is assigned. These bits are write disable bits.
When thses bits are read out, the values are “0.”
Fig. 2.11.7 Horizontal position register (address 00E0 16)
2-76
7220 Group User’s Manual
After reset
R W
0
R W
0
R —
FUNCTIONAL DESCRIPTION
2.11 CRT display function
2.11.2 Character size
The size of characters to be displayed can select from 3 sizes for each block. Set a character size by the
character size register (address 00E416).
The character size in block 1 can be specified by bits 0 and 1 of the character size register; the character
size in block 2 can be specified by bits 2 and 3. Figure 2.11.8 shows the character size register.
Character Size Register
b7 b6 b5 b4 b3 b2 b1 b0
Character size register (CS) [Address 00E4 16 ]
B
Name
Functions
After reset
R W
0, 1 Character size of block 1
selection bits
(CS10, CS11)
00 : Minimum size
01 : Medium size
10 : Large size
11 : Do not set.
Indeterminate R W
2,3 Character size of block 2
selection bits
(CS20,CS21)
00 : Minimum size
01 : Medium size
10 : Large size
11 : Do not set.
Indeterminate R W
4
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
0
R —
Fig. 2.11.8 Character size register (address 00E416)
The character size can select three sizes: minimum
size, medium size, and large size. Each character
size is determined with the number of scanning lines
in the height (vertical) direction and the oscillation
cycle for display (= T C ) in the width (horizontal)
direction.
The minimum size consists of [1 scanning line] ✕ [1
TC]; the medium size consists of [2 scanning lines]
✕ [2 TC]; and the large size consists of [3 scanning
lines] ✕ [3 TC]. Table 2.11.2 shows the relationship
between the set values in the character size register
and the character sizes.
Minimum size
Medium size
Display start
position
Large size
Fig. 2.11.9 Display start position (horizontal
direction) for each character size
Table 2.11.2 Relationship between set value in character size register and character sizes
Width (horizontal) direction
Height (vertical) direction
Set values in character size register
Character size
CSn0
CSn1
TC: oscillation cycle for display
scanning lines
0
0
Minimum
1 TC
1 line
0
1
1
0
Medium
2 TC
2 lines
3 lines
Large
3 TC
This is not available.
1
1
Note: The display start position in the horizontal direction is not affected by the character size. In other
words, the horizontal display start position is common to all blocks even when the character size
varies with each block (refer to “Figure 2.11.9”).
7220 Group User’s Manual
2-77
FUNCTIONAL DESCRIPTION
2.11 CRT display function
2.11.3 Memory for display
There are 2 types of display memory: CRT display ROM (addresses 10000 16 to 11FFF 16) used to store
(masked) character dot data and CRT display RAM (addresses 060016 to 06B716) used to specify the colors
and characters to be displayed. Each type of display memory is described below.
(1) CRT display ROM (addresses 1000016 to 11FFF 16)
CRT display ROM stores dot pattern data for characters to be displayed. When actually displaying
characters stored in this ROM, it is necessary to specify them by writing the character code inherent
to each character (code determined based on the addresses in CRT display ROM) into CRT display
RAM.
CRT display ROM has a capacity of 8 K bytes. Since 32 bytes are required for 1 character data, the
ROM can stores up to 256 kinds of characters.
CRT display ROM is broadly divided into 2 areas. The [vertical 16 dots] ✕ [horizontal (left side) 8
dots] data of display characters are stored in addresses 1000016 to 107FF 16 and 11000 16 to 117FF16;
the [vertical 16 dots] ✕ [horizontal (right side) 4 dots] data of display characters are stored in
addresses 1080016 to 10FFF16, 1180016 to 11FFF16 (refer to “Figure 2.11.10”). Note however that the
high-order 4 bits of the data to be written to addresses 10800 16 to 10FFF 16 and 11800 16 to 11FFF 16
must be set to “1” (by writing data FX16 ).
10XX016
or
11XX016
10XXF 16
or
11XXF 16
b7
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 0
0 0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
b0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
10XX016
+80016
or
11XX016
+80016
10XXF 16
+80016
or
11XXF 16
+80016
b7
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
Fig. 2.11.10 Example of display character data storing form
2-78
7220 Group User’s Manual
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b3
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FUNCTIONAL DESCRIPTION
2.11 CRT display function
The character code used to specify a display character is determined based on the address in the
CRT display ROM in which that character data is stored.
Assume that 1 character data is stored in addresses 10XX016 to 10XXF16 (XX denotes “0016” to “7F16”)
and 10YY0 16 to 10YYF 16 (YY denotes “XX + 800 16”), then the character code is “XX 16.”
In other words, a character code is constructed with the low-order second and third digits (hexadecimal
notation) of the 5-digit address (10000 16 to 107FF16) where that character data is stored.
A character code is “YY16” in addresses 1100016 to 11FFF16.
Table 2.11.3 shows the character code table.
Table 2.11.3 Character code table (be omitted partly)
0016
Character data stored address
Left side 8 dots
Right 4 side 8 dots
10000 16 to 1000F16
10800 16 to 1080F 16
0116
10010 16 to 1001F16
10810 16 to 1081F 16
0216
10020 16 to 1002F16
10820 16 to 1082F 16
0316
10030 16 to 1003F16
10830 16 to 1083F 16
:
:
:
7E 16
107E016 to 107EF16
107F016 to 107EF 16
10FE0 16 to 10FEF 16
10FF0 16 to 10FFF 16
Character code
7F16
8016
11000 16 to 1100F16
11800 16 to 1180F 16
8116
11010 16 to 1101F16
11810 16 to 1181F 16
:
:
:
FD16
117D0 16 to 117DF16
11FD0 16 to 11FDF 16
FE16
117E016 to 117EF16
117F016 to 117EF 16
11FE0 16 to 11FEF 16
11FF0 16 to 11FFF 16
FF 16
7220 Group User’s Manual
2-79
FUNCTIONAL DESCRIPTION
2.11 CRT display function
(2) CRT display RAM (addresses 060016 to 06B716)
CRT display RAM is assigned to addresses 060016 to 06B716, and is divided into a display character
code specification part and display color specification part for each block. Table 2.11.4 shows the
contents of CRT display RAM.
For example, to display a character at the first character position (leftmost) in block 1, it is necessary
to write the character code in address 060016 and the color register No. to the low-order 2 bits (bits
0 and 1) at address 068016. The color register No. to be written here is one of the 4 color registers
in which display color is set in advance. For details on color registers, refer to “2.11.4 Color registers.”
Table 2.11.4 Contents of CRT display RAM
Block number
Block 1
Display position (from left side)
Character code specifying
0600 16
Color specifying
1st character
2nd character
0601 16
3rd character
0602 16
068116
068216
:
:
:
22nd character
23rd character
0615 16
069516
0616 16
069616
24th character
0617 16
0618 16
069716
to
069816
:
061F16
069F 16
1st character
2nd character
0620 16
06A016
0621 16
06A116
3rd character
0622 16
:
06A216
:
22nd character
0635 16
:
06B516
23rd character
0636 16
06B616
24th character
0637 16
06B716
Not used
Block 2
2-80
068016
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.11 CRT display function
Figure 2.11.11 shows the structure of CRT display RAM.
Block 1
[Character specification]
7
0
1st character : 0600 16
to
24th character : 0617 16
Character code
Specify 256 characters (“00 16” to “FF16”)
[Color specification]
1st character : 0680 16
1
0
to
24th character : 0697 16
Color register specification
0 0 : Specifying color register 0
0 1 : Specifying color register 1
1 0 : Specifying color register 2
1 1 : Specifying color register 3
Block 2
[Character specification]
1st character : 0620 16
7
0
to
24th character : 0637 16
Character code
Specify 256 characters (“00 16” to “FF16”)
[Color specification]
1st character : 06A0 16
1
0
to
24th character : 06B7 16
Color register specification
0 0 : Specifying color register 0
0 1 : Specifying color register 1
1 0 : Specifying color register 2
1 1 : Specifying color register 3
Fig. 2.11.11 Structure of CRT display RAM
7220 Group User’s Manual
2-81
FUNCTIONAL DESCRIPTION
2.11 CRT display function
2.11.4 Color registers
A display character color can be specified by setting a color to one of 4 color registers (CO0 to CO3:
addresses 00E616 to 00E9 16) and then by specifying the color register with the CRT display RAM.
There are 3 color outputs: R, G, and B. By a combination of these outputs, it is possible to set 23 – 1 (no
output) = 7 colors. However, since color registers are only 4, up to 4 colors can be displayed at one time.
R, G, and B outputs are set by bits 1 to 3 of the color register. Bit 5 is used to specify either a character
output or blank output. Figure 2.11.12 shows the color register.
Either character output or blank output is selected as the OUT1 pin output. Whether blank output or not
is selected as the OUT2 pin output.
Color Register n
b7 b6 b5 b4 b3 b2 b1 b0
Color register n (CO0 to CO3) (n = 0 to 3) [Addresses 00E6 16 to 00E916 ]
B
Name
Functions
After reset R W
0
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
0
R —
1
B signal output
selection bit (COn1)
0 : No character is output
1 : Character is output
0
R W
2
G signal output
selection bit (COn2)
0 : No character is output
1 : Character is output
0
R W
3
R signal output
selection bit (COn3)
0 : No character is output
1 : Character is output
0
R W
4
B signal output (background) 0 : No background color is output
1 : Background color is output (See note 1)
selection bit (COn4)
0
R W
5
OUT1 signal output
control bit (COn5)
0
R W
0 : Character is output
1 : Blank is output
(See notes 1, 2)
6
G signal output (background) 0 : No background color is output
selection bit (COn6)
1 : Background color is output
0
R W
7
R signal output (background) 0 : No background color is output
1 : Background color is output (See note 2)
selection bit (COn7)
0
R W
Notes 1: When bit 5 = “0” and bit 4 = “1,” there is output same as a character or border output
from the OUT1 pin.
Do not set bit 5 = “0” and bit 4 = “0.”
2: When only bit 7 = “1” and bit 5 = “0,” there is output from the OUT2 pin.
Fig. 2.11.12 Color register n (addresses 00E616 to 00E9 16)
2-82
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.11 CRT display function
Table 2.11.5 Display example of character background coloring (when green is set for a character
and blue is set for background color)
Border selection register
Color register
G output
B output
OUT1 output
Character output
OUT2 output
MD0 COn7 COn6 COn 5 COn4 COn3 COn2 COn1
Green
0
0
✕
0
1
0
(Note 1)
1
0
No output
(Note 2)
No output
Same output as
character A
Video signal and character
color (green) are not mixed.
Green
0
1
✕
0
1
0
1
0
No output
Same output as Video signal and character
color (green) are not mixed.
character A
Blank output
Green
0
0
0
1
0
0
1
0
No output
(Note 2)
No output
Blank output
TV image of character
background is not displayed.
Green
0
0
0
1
1
0
1
Background
color
1
✕
✕
0
1
0
1
0
No output
(Note 2)
Blue
0
Blank output
TV image of character
background is not displayed.
Border
output
(Black)
No output
Border output
(Black)
Green
No output
(Note 2)
Video signal and character
color (green) are not mixed.
Green
1
0
0
1
0
0
1
0
Blank output
1
0
0
1
1
0
1
No output
(Note 2)
Black
No output
TV image of character
background is not displayed.
Border
output
(Black)
0
Green
Blue
Background
color – border
Blank output
No output
(Note 2)
TV image of character
background is not displayed.
Notes 1 : When COn5 = “0” and COn 4 = “1,” there is output same as a character or border output from the OUT1 pin.
Do not set COn 5 = “0” and COn 4 = “0.”
2 : When only COn 7 = “1” and COn 5 = “0,” there is output from the OUT2 pin.
3 : The portion “A” in which character dots are displayed is not mixed with any TV video signal.
4 : The wavy-lined arrows in the Table denote video signals.
5 : n : 0 to 3, ✕ : 0 or 1
7220 Group User’s Manual
2-83
FUNCTIONAL DESCRIPTION
2.11 CRT display function
2.11.5 Multi-line display
The M37221M6-XXXSP/FP can ordinarily display 2 lines on the CRT screen by displaying 2 blocks at
different vertical positions. In addition, it can display up to 16 lines by using a CRT interrupt.
A CRT interrupt request occurs at which display of each block has been completed. In other words,
character display of a certain block starts when a scanning line reaches the display position (specified by
vertical position registers) for that block, and an interrupt occurs when the scanning line exceeds the block.
For multi-line display, it is necessary to enable the CRT interrupt (by clearing the interrupt disable flag to
“0” and setting the CRT interrupt enable bit = bit 4 at address 00FE16 to “1”).
In a CRT interrupt processing routine, the character data and vertical position of the block of which display
has been completed (the display as CRT interrupt cause is completed) is then replaced with the character
data (contents of CRT display RAM) and display position (contents of vertical position register) for next
display.
Notes 1: Set the second and later block 1 display start positions of block 1 to be lower than display position
of the last block 2.
2: The CRT interrupt request does not occur at the end of display when the block is not displayed.
In other words, if a block is set to off display with the display control bit of the CRT control
register (at address 00EA16), a CRT interrupt request does not occurs (refer to “Figure 2.11.14”).
Block 1
Block 1 (on display)
Block 2
Block 2 (on display)
Block 1
Block 2
,
On display (CRT interrupt request
occurs at the end of block display)
,
CRT interrupt request
Block 1 (off display)
Fig. 2.11.13 Generation timing of CRT interrupt
request
Block 2 (off display)
Off display (CRT interrupt request does
not occur at the end of block display)
CRT interrupt request
Fig. 2.11.14 Display state of blocks and occurrence
of CRT interrupt request
2-84
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.11 CRT display function
2.11.6 Character border function
An border of 1 clock (1 dot) equivalent size can be
added to a display character in both horizontal and
vertical directions. The border is output from pin
OUT 1. In this case, set bit 5 of a color register to
“0” (character is output).
Border can be specified each block by the border
selection register (address 00E516). Table 2.11.6
shows the relationship between the set values of
the border selection register and the character border
function. Figure 2.11.16 shows the border selection
register.
Character
data dots
Border dots
Fig. 2.11.15 Border example
Table 2.11.6 Relationship between set value of border selection register and character border function
Border selection register
Functions
Example of output
MDn0
R, G, B output
Ordinary
0
OUT1 output
Border including
R, G, B output
character
1
OUT1 output
Border Selection Register
b7 b6 b5 b4 b3 b2 b1 b0
Border selection register (MD) [Address 00E516]
B
Name
Functions
0
Block 1 OUT1 output
0 : Same output as character output
border selection bit (MD10) 1 : Border output
1
Nothing is assigned. This bit is a write disable bits.
When this bit is read out, the value is “0.”
2
Block 1 OUT1 output
0 : Same output as character output
border selection bit (MD20) 1 : Border output
3
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
After reset
R W
Indeterminate R W
0
R —
Indeterminate R W
0
R —
Fig. 2.11.16 Border selection register (address 00E5 16)
7220 Group User’s Manual
2-85
FUNCTIONAL DESCRIPTION
2.11 CRT display function
2.11.7 CRT output pin control
CRT display output pins R, G, B, and OUT1 are also used for ports P5 2–P55 respectively. When clearing
the corresponding bits of the port P5 direction register (address 00CB16) to “0,” the pins are set for CRT
output pins, when setting to “1,” the pins are set for general-purpose port P5. Pin PUT2 is also used for
port P10. When clearing bit 7 of the CRT control register (address 00EA16) to “0,” the pin is set for port P10,
when setting to “1,” the pin is set for pin OUT2.
Immediately after reset release, because the port P5 direction register is reset, they become CRT output
pins R, G, B, and OUT.
Bits 0 to 4 of the CRT port control register (address 00EC16) can determine HSYNC and VSYNC input polarity
and R, G, B, OUT1, and OUT2 output polarity. When clearing corresponding bits to “0,” positive polarity
is selected, when setting to “1,” negative polarity is selected.
Figure 2.11.17 shows the CRT port control.
CRT Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0
CRT port control register (CRTP) [Address 00EC16]
B
Name
Functions
HSYNC input polarity
switch bit (HSYC)
0 : Positive polarity
1 : Negative polarity
0
R W
1
VSYNC input polarity
switch bit (VSYC)
0 : Positive polarity
1 : Negative polarity
0
R W
2
R, G, B output polarity
switch bit (R/G/B)
0 : Positive polarity
1 : Negative polarity
0
R W
3
OUT2 output polarity
switch bit (OUT2)
0 : Positive polarity
1 : Negative polarity
0
R W
4
OUT1 output polarity
switch bit (OUT1)
0 : Positive polarity
1 : Negative polarity
0
R W
5
R signal output switch bit
(OP5)
0 : R signal output
1 : MUTE signal output
0
R W
6
G signal output switch bit
(OP6)
0 : G signal output
1 : MUTE signal output
0
R W
7
B signal output switch bit
(OP7)
0 : B signal output
1 : MUTE signal output
0
R W
Fig. 2.11.17 CRT port control register (address 00EC 16)
2-86
After reset R W
0
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.11 CRT display function
2.11.8 Raster coloring function
R, G, B, and OUT1 output can be switched to MUTE output. MUTE output can color all displaying area
(raster) of screen.
For example, the case that pin B is specified for MUTE signal output is shown in Figure 2.11.18.
When the MUTE signal is output from pin B, the background of the entire screen is colored “BLUE.” Then,
a character data is output from pin R, for example. When B and R signal outputs are set to “character is
output” by the color register at the character “I” output, the output character is colored “YELLOW” (“RED”
mixed “BLUE”) regardless of the OUT1 signal output.
When outputting the character “O,” the output character is colored only “RED” that is not mixed “BLUE”
by setting only R signal output to “character is output.” However, in this case, set pin OUT1 to “blank is
output.”
The TV image can be also erase by setting the all R, G, and B pins to MUTE output. The MUTE signal
is output from pin OUT1 output, regardless of setting CRT display RAM for pin OUT1.
Whether ordinary video signal outputs or MUTE signal outputs from pins R, G, and B is controlled by bits
5 to 7 of the CRT port control register (refer to “Figure 2.11.17”).
“RED”
“BLUE”
A'
A
HSYNC
R
Signals across
A-A'
B
OUT 1
Fig. 2.11.18 MUTE signal output example
7220 Group User’s Manual
2-87
FUNCTIONAL DESCRIPTION
2.11 CRT display function
2.11.9 Clock for display
As a clock for display to be used for CRT display, it is possible to select one of the following 4 types.
● Main clock supplied from the X IN pin
● Main clock supplied from the XIN pin divided by 1.5
● Clock from the LC or RC supplied from the pins OSC1 and OSC2.
● Clock from the ceramic resonator or quartz-crystal oscillator supplied from the pins OSC1 and OSC2.
This clock for display can be selected by the CRT clock selection register (address 00ED 16). When selecting
the main clock, set the oscillation frequency to 8 MHz.
CRT Clock Selection Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
0
0
CRT clock selection register (CK) [Address 00ED16 ]
B
Name
0, 1 CRT clock
selection bits
(CK0,CK1)
Functions
b1 b0
1
0 The clock for display is supplied by connecting RC
or LC across the pins OSC1 and OSC2.
0
1 Since the main clock is used as the clock for CRT oscillation
display, the oscillation frequency is limited.
frequency
Because of this, the character size in width = f(X IN)
(horizontal) direction is also limited. In this
CRT oscillation
0 case, pins OSC1 and OSC2 are also used
frequency
as input ports P3 3 and P34 respectively.
= f(XIN )/1.5
1
1
2
to
7
Functions
After reset R W
0
R W
0
R W
1 The clock for display is supplied by connecting the
following across the pins OSC1 and OSC2.
• a ceramic resonator only for CRT display and a feedback resistor
• a quartz-crystal oscillator only for CRT display and a feedback
resistor (Note)
Fix these bits to “0.”
Note: It is necessary to connect other ceramic resonator or quartz-crystal oscillator across the pins XIN and X OUT .
Fig. 2.11.19 CRT clock selection register
2-88
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.12 ROM correction function
2.12 ROM correction function
Only the M37221M8-XXXSP and the M37221MA-XXXSP have this function.
This can correct ROM program data in ROM. Up to 2 addresses (2 blocks) can be corrected, a program for
correction is stored in the ROM correction memory in RAM. The ROM memory for correction is 32 bytes ✕
2 blocks.
Block 1 : addresses 02C016 to 02DF16
Block 2 : addresses 02E016 to 02FF 16
Set an address of the ROM data to be corrected into the ROM correction address register. When the value
of the counter matches the ROM data address in the ROM correction address, the main program branches
to the correction program stored in the ROM correction memory. To return from the correction program to
the main program, the op code and operand of the JMP instruction (total of 3 bytes) are necessary at the
end of the correction program. When the blocks 1 and 2 are used in series, the above instruction is not
needed at the end of the block 1.
The ROM correction function is controlled by the ROM correction enable register.
Notes 1 : Specify the first address (op code address) of each instruction as the ROM correction address.
2 : Use the JMP instruction (total of 3 bytes) to return from
the correction program to the main program.
3 : Do not set the same address to ROM correction addresses 1 and 2 (addresses to 021716 to
021A16).
ROM correction address 1 (high-order)
0217 16
ROM correction address 1 (low-order)
0218 16
ROM correction address 2 (high-order)
0219 16
ROM correction address 2 (low-order)
021A 16
Fig. 2.12.1 ROM correction address registers
ROM Correction Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
ROM correction enable register (RCR) [Address 021216]
B
Name
Functions
After reset R W
0
Block 1 enable bit (RCR0)
0: Disabled
1: Enabled
0
R W
1
Block 2 enable bit (RCR1)
0: Disabled
1: Enabled
0
R W
0
R —
0
R —
2, 3 Fix these bits to “0.”
4
to
7
Nothing is assigned. These bits are write disable bits. When
these bits are read out, the values are “0.”
Fig. 2.12.2 ROM correction enable register
7220 Group User’s Manual
2-89
FUNCTIONAL DESCRIPTION
2.13 Software runaway detect function
2.13 Software runaway detect function
The M37221M6-XXXSP/FP has a function to decode undefined instructions to detect a software runaway.
When an undefined op-code is input to the CPU as an instruction code during operation of the M37221M6XXXSP/FP, the following processing is done.
➀ The CPU generates an undefined instruction decoding signal.
➁ The device is internally reset because of occurrence of the undefined instruction decoding signal.
➂ As a result of internal reset, the same reset processing as in the case of ordinary reset operation is done,
and the program restarts from the reset vector.
Note, however, that the software runaway detecting function cannot be invalid.
φ
SYNC
Address
Data
PC
01,S
?
?
01,S–1
PCH
PCL
FFFE16
01,S–2
PS
ADH,
ADL
FFFF16
ADL
ADH
Reset sequence
Undefined instruction decoding signal occurs.
Internal reset signal occurs.
: Undefined instruction decode
? : Invalid
PC : Program counter
S : Stack pointer
ADL, ADH : Jump destination address of reset
Fig. 2.13.1 Sequence at detecting software runaway detection
2-90
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.14 Low-power dissipation mode
2.14 Low-power dissipation mode
The M37221M6-XXXSP/FP has 2 low-power dissipation modes: the stop mode and the wait mode.
2.14.1 Stop mode
The M37221M6-XXXSP/FP allows the oscillation of X IN to be stopped with keeping all states of registers
except timers 3 and 4, input/output ports, and internal RAM. Therefore, the M37221M6-XXXSP/FP can be
restarted with the same state where oscillation was stopped, and as a result, the power dissipation can be
greatly reduced.
To stop oscillating in such a way, execute the STP instruction. The stop mode is set by executing the STP
instruction. In this mode, the address to fetch the instruction next to the STP instruction is output to the
address bus, and the oscillation stops with HIGH state of the internal clock φ . At this time, the timer 3
overflow signal is further connected to timer 4. Value “FF16” is automatically set to timer 3; value “0716” is
automatically set to timer 4.
Immediately before executing the STP instruction, process the following sequence:
➀ Store registers (accumulator, index registers, etc.) in the CPU to internal RAM.
➁ Disable timers 3 and 4 interrupts (TM3E = TM4E = “0”).
➂ Clear timers 3 and 4 count stop bits to “0” (T34M2 = T34M3 = “0”).
➃ When an interrupt is used for return from the stop mode, enable that interrupt (by clearing the interrupt
disable flag to “0” and setting the interrupt enable bit to “1”).
➄ Set bit 0 of the timer 34 mode register (address 00F5 16) to “0” (TM34M0=“0”) to select f(XIN)/16 as the
timer 3 count source.
Oscillation is restarted (return from the stop mode) by accepting reset input or interrupt request of INT1,
INT2 or INT3. When the interrupt request is accepted, the interrupt processing routine is executed. Note,
however, that the internal clock φ is not supplied to the CPU until timer 4 overflows after the interrupt
request is accepted. This is because a finite time is required for stabilizing of oscillation when an external
quartz-crystal oscillator, etc. is used.
When the internal clock φ is supplied to the CPU, the CPU executes the interrupt routine. At this time, the
address for the first byte of the instruction next to the STP instruction is pushed to the stack as a return
address. Also note that the timers 3 and 4 interrupt request bits are remained setting to “1.” Therefore,
clear each bit to “0” in the interrupt routine. Enable one of the INT1, INT2 and INT3 interrupts to use
interrupts for restarting oscillation before the executing STP instruction (described in ➃ above).
Table 2.14.1 State in stop mode
Item
State in stop mode
Oscillation
Stops
CPU
Internal clock φ
Stops
I/O ports
State where STP instruction is executed is held.
Stops
Timer, CRT display functions
Stops at HIGH level
7220 Group User’s Manual
2-91
FUNCTIONAL DESCRIPTION
2.14 Low-power dissipation mode
Time to hold internal reset state =
approximately 32768 cycles of XIN
input
Stop mode
VCC
Oscillation stabilizing time
2 µs or more
RESET
XIN
(Note)
Execute STP instruction Returned by reset input
Fig. 2.14.1 Oscillation stabilizing time at return by reset input
lWhen returning from stop mode by using INT1 interrupt (rising edge selected)
Stop mode Oscillation stabilizing time
(approximately 32768 cycles)
XIN
(System clock)
XIN; HIGH
XCIN; in high-impedance state
INT1 pin
“FF16 ”
Timer 3
counter
Timer 4
counter
2048 counts
“0716”
INT1 interrupt
request bit
Peripheral device
CPU
Operating
Stopping
Operating
•Execute STP
instruction
Operating
Stopping
Operating
•2048 counts down by timer 3
•INT1 interrupt
•Supplying internal clock φ
signal is input
(INT1 interrupt
to CPU is started
request occurs) •INT1 interrupt request is accepted
•Oscillation starts
•Timer 3 count starts
Fig. 2.14.2 Execution sequence example at return by occurrence of INT0 interrupt request
2-92
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.14 Low-power dissipation mode
2.14.2 Wait mode
The wait mode is set by executing the WIT instruction.
In the wait mode, only the internal clock φ stops with supplying f(X IN) continuously.
In this case, there is no need to create a wait time by timers as in the case of return from the stop mode,
and operation is restarted immediately after return from the wait state.
When reset input or interrupt is accepted, supply of the internal clock φ is immediately started, and the
device is returned from the wait state. Because the clock f(X IN) is continuously supplied in the wait state,
return by an internal interrupt as a timer, etc. can also be used.
Table 2.14.2 State in wait mode
Item
State in wait mode
Oscillation
Operating
CPU
Internal clock φ
Stop
Stop at HIGH level
I/O ports
State where WIT instruction is executed is held.
Timer, CRT display functions
Operating
Time to hold internal reset state =
approximately 32768 cycles of XIN
input
Oscillation stabilizing time
Wait mode
VCC
2 µs or more
RESET
XIN
(Note)
Execute WIT instruction
Returned by reset input
Fig. 2.14.3 Reset input time
2.14.3 Interrupts in low-power dissipation mode
The following 4 kinds of interrupts are invalid in the wait mode. Therefore, 4 interrupts below cannot be
used to return from the wait mode to the ordinary mode.
Table 2.14.3 Invalid interrupts in the wait mode
Interrupt source
VSYNC interrupt
CRT interrupt
Condition
—
Timer 2 interrupt
Count source is input from pin P2 4/TIM2.
Timer 3 interrupt
Count source is input from pin P2 3/TIM3.
Reason
The interrupt request bit cannot be set.
The count source cannot be supplied.
The count source cannot be supplied.
The following 2 kinds of interrupts can be used to return from the stop mode to the ordinary mode.
➀ INT1 interrupt
➁ INT2 interrupt
➂ INT3 interrupt
Figure 2.14.4 shows a transitions of low-power dissipation mode.
7220 Group User’s Manual
2-93
FUNCTIONAL DESCRIPTION
2.14 Low-power dissipation mode
Reset
Wait mode
8 MHz oscillating
φ is stopped
Timer operating
(Note 1)
Ordinary mode
Stop mode
8 MHz oscillating
φ = 4 MHz
8 MHz stopped
φ is stopped
(Note 2)
* at f(XIN) = 8 MHZ
Notes 1: The following interrupts are invalid in the wait mode.
(1) V SYNC interrupt
(2) CRT interrupt
(3) Timer 2 interrupt that count source is supplied from pin P24 /TIM2.
(4) Timer 3 interrupt that count source is supplied from pin P23 /TIM3.
Fig. 2.14.4 State transitions of low-power dissipation mode
2-94
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.15 Reset
2.15 Reset
To reset the microcomputer, applied LOW level to pin RESET for 2 µ s or more. Reset is released when
HIGH level is applied to pin RESET, and the program starts from the address indicated with the reset vector
table.
2.15.1 Reset operation
If pin RESET is returned to an HIGH level after being held LOW for 2 µs or more when the power source
voltage is within the recommended range (4.5 V to 5.5 V), timers 3 and 4 are connected by hardware with
internally reset state (internal timing signal φ is not supplied).
At this time, “FF16” is set to timer 3, and “0716” is set to timer 4. Timer 3 counts down f(XIN)/16 as its count
source; timer 4 counts down the timer 3 overflow signal (even when the device is in internally reset state,
f(XIN) is continuously supplied to timer 3).
The internal reset is released by timer 4 overflow, and the program is started from an address determined
with the contents of address FFFF16 (as high-order address) and contents of address FFFE16 (as low-order
address). Figure 2.15.1 shows this sequence.
XIN
φ
RESET
Internal
reset
SYNC
Address
?
Data
?
?
01,S
?
01,S–1
PCH
01,S–2
PCL
FFFE16
PS
FFFF16
ADL
ADH,
ADL
ADH
32,768 counts of f(X IN) by
timers 3 and 4
Notes 1: f(XIN) and f(φ) are in the relation : f(XIN) = 2•f(φ).
2: A question mark (?) indicates an undefined state that depends on the previous state.
3: Immediately after a reset, timer 3 and timer 4 are connected by hardware. At this time, “FF16”
is set in timer 3 and “0716” is set to timer 4. Timer 3 counts down with f(XIN)/16, and reset
state is released by the timer 4 overflow signal.
Fig. 2.15.1 Timing diagram at reset
7220 Group User’s Manual
2-95
FUNCTIONAL DESCRIPTION
2.15 Reset
2.15.2 Internal state immediately after reset
Figures 2.15.2 to 2.15.4 show the internal state immediately after reset.
■SFR Area (addresses C016 to DF16)
< State immediately after reset >
0 : “0” immediately after reset
1 : “1” immediately after reset
? : Indeterminate immediately
after reset
Address
State immediately after reset
Register
b0
b7
C016
C116
C216
C316
C416
C516
C616
C716
C816
C916
CA16
CB16
CC16
CD16
CE16
CF16
D016
D116
D216
D316
D416
D516
D616
D716
D816
D916
DA16
DB16
DC16
DD16
DE16
DF16
Port P0 (P0)
Port P0 direction register (D0)
Port P1 (P1)
Port P1 direction register (D1)
Port P2 (P2)
Port P2 direction register (D2)
Port P3 (P3)
0
0
0
0
0
?
0
0
?
0
0
0
Port P3 direction register (D3)
Port P5 (P5)
Port P5 direction register (D5)
Port P3 output mode control register (P3S)
DA-H register (DA-H)
DA-L register (DA-L)
PWM0 register (PWM0)
PWM1 register (PWM1)
PWM2 register (PWM2)
PWM3 register (PWM3)
PWM4 register (PWM4)
PWM output control register 1 (PW)
PWM output control register 2 (PN)
I2 C data shift register (S0)
I2 C address register (S0D)
I2 C status register (S1)
I2 C control register (S1D)
I2 C clock control register (S2)
Serial I/O mode register (SM)
Serial I/O register (SIO)
Fig. 2.15.2 Internal state immediately after reset (1)
2-96
7220 Group User’s Manual
?
0016
?
0016
?
0016
? ?
0016
?
?
? ?
0016
?
0016
?
? ?
?
?
?
?
?
0016
0016
?
0016
1 0
0016
0016
0016
?
0016
0016
?
?
?
?
?
?
?
?
?
0
0
?
FUNCTIONAL DESCRIPTION
2.15 Reset
■SFR Area (addresses E016 to FF16)
< State immediately after reset >
0 : “0” immediately after reset
1 : “1” immediately after reset
? : Indeterminate immediately
after reset
Address
E016
E116
E216
E316
E416
E516
E616
E716
E816
E916
EA16
EB16
EC16
ED16
EE16
EF16
F016
F116
F216
F316
F416
F516
F616
F716
F816
F916
FA16
FB16
FC16
FD16
FE16
FF16
State immediately after reset
Register
b0
b7
0016
Horizontal position register (HR)
Vertical position register 1 (CV1)
Vertical position register 2 (CV2)
0
0
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0 ?
0 0
0016
0016
0016
0016
0016
?
0016
0016
? 0
0016
FF16
0716
FF16
0716
0016
0016
?
?
?
0 0
0016
1 1
0016
0016
0016
0016
?
?
?
0
?
?
0
0
0
0
0
?
1
0
0
?
0
0
0
0
0
0
0
0
0
Interrupt input polarity register (RE)
0
0
0
CPU mode register (CPUM)
?
?
1
Character size register (CS)
Border selection register (MD)
Color register 0 (CO0)
Color register 1 (CO1)
Color register 2 (CO2)
Color register 3 (CO3)
CRT control register (CC)
CRT port control register (CRTP)
CRT clock selection register (CK)
A-D control register 1 (AD1)
A-D control register 2 (AD2)
Timer 1 (TM1)
Timer 2 (TM2)
Timer 3 (TM3)
Timer 4 (TM4)
Timer 12 mode register (T12M)
Timer 34 mode register (T34M)
PWM5 register (PWM5)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Fig. 2.15.3 Internal state immediately after reset (2)
7220 Group User’s Manual
2-97
FUNCTIONAL DESCRIPTION
2.15 Reset
■2 Page Register Area (addresses 21716 to 21B16)
< State immediately after reset >
0 : “0” immediately after reset
1 : “1” immediately after reset
? : Indeterminate immediately
after reset
Address
21716
21816
21916
21A16
21B16
State immediately after reset
Register
b0
b7
ROM correction address 1 (high-order)
ROM correction address 1 (low-order)
ROM correction address 2 (high-order)
ROM correction address 2 (low-order)
ROM correction enable register (RCR)
?
?
?
?
0016
Fig. 2.15.4 Internal state immediately after reset (3) (only M37221M8-XXXSP and M37221MA-XXXSP)
2-98
7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.15 Reset
2.15.3 Notes for poweron reset
When poweron reset, set the external reset circuit
so that the reset input voltage must be kept 0.6 V
or less until the power source voltage reaches
4.5 V after the power is turned on.
Set the external reset circuit so that the reset input
voltage must be kept 0.6 V or less when the power
source voltage falls 4.5 V after the power is turned
off.
Figures 2.15.5 to 2.15.7 show examples of external
reset circuit.
M37221M6XXXSP/FP
RESET VCC 0 V
Power source
voltage
4.5 V
Reset input
voltage
0.6 V
0V
Poweron
Fig. 2.15.5 Voltage at poweron reset
RESET
VCC
M37221M6XXXSP/FP
VSS
Fig. 2.15.6 Example of reset circuit (1)
RESET
VCC
M37221M6XXXSP/FP
VSS
Fig. 2.15.7 Example of reset circuit (2)
7220 Group User’s Manual
2-99
FUNCTIONAL DESCRIPTION
2.16 Clock generating circuit
2.16 Clock generating circuit
Oscillation circuit consists of an “oscillation gate” which operates as an amplifier to provide the gain required
for oscillation and an “oscillating control flip-flop” to control this. Because of that, it is possible to start and
stop oscillating as required. For details concerning start and stop of oscillation, refer to “2.14 Low-power
dissipation mode.” Figure 2.16.1 shows the clock generating circuit block diagram.
Interrupt request
S
Interrupt disable
flag I
S
Q
Q
Reset
S
Q
Reset
STP instruction
WIT
instruction
R
R
R
STP
instruction
Internal clock φ
.
1/2
Selection gate :
Connected to black
side at reset.
1/8
Timer 3
T34M0
T34M2
X IN
XOUT
T34M : Timer 34 mode register
Fig. 2.16.1 Clock generating circuit block diagram
2-100
7220 Group User’s Manual
Timer 4
FUNCTIONAL DESCRIPTION
2.17 Oscillation circuit
2.17 Oscillation circuit
The M37221M6-XXXSP/FP has a internal oscillation circuits used to obtain the clocks required for operation.
Ordinarily, the frequency on clock input pin XIN divided by 2 is the internal clock (internal timing output) φ .
A quartz-crystal oscillator or ceramic resonator can be connected externally to these circuits.
(1) Oscillation circuit using a quartz-crystal oscillator or ceramic resonator
Figure 2.17.1 shows the circuit example using a quartz-crystal oscillator or a ceramic resonator. As
shown in the diagram, oscillation circuit can be constructed by connecting a ceramic resonator (a
quartz-crystal oscillator) between pins X IN and XOUT. In this case, set the circuit constants for C IN and
C OUT to the values recommended by the resonator manufacturer.
(2) External clock oscillation circuit
Supplying an external clock is possible, Figure 2.17.2 shows the circuit example.
M37221M6-XXXSP/FP
XIN
19
M37221M6-XXXSP/FP
XIN
XOUT
19
20
XOUT
20
Open
CIN
External oscillation circuit
VCC
VSS
COUT
Note: In the stop mode, keep the XIN pin input
signal at an “H” level.
Fig. 2.17.1 Clock oscillation circuit using a ceramic
resonator
Fig. 2.17.2 External clock input circuit example
The M37221M6-XXXSP/FP has a CRT display clock
oscillation circuit, so that display clock can be obtained
simply by connecting a inductor and capacitor between
pins OSC1 and OSC2. Figure 2.17.3 shows the circuit
example.
Refer to “2.11.9 Clock for display.”
M37221M6-XXXSP/FP
OSC1
OSC2
23
24
L
C1
C2
Fig. 2.17.3 Clock oscillation circuit for CRT display
7220 Group User’s Manual
2-101
CHAPTER 3
ELECTRICAL
CHARACTERISTICS
3.1 Electrical characteristics
3.2 Standard characteristics
ELECTRICAL CHARACTERISTICS
3.1 Electrical characteristics
3.1 Electrical characteristics
Absolute maximum ratings
Parameter
Symbol
Power source voltage V CC
VCC
Input voltage
CNVSS
VI
VI
Input voltage
VO
Output voltage
Conditions
All voltages are
based on V SS.
P00–P0 7,P1 0–P17, P20–
P2 7, P3 0–P34, OSC1, X IN,
H SYNC, V SYNC, RESET
P0 6, P07, P1 0–P1 7, P2 0–
Output transistors
are cut off.
Ratings
–0.3 to 6
Unit
V
–0.3 to 6
V
–0.3 to V CC + 0.3
V
–0.3 to V CC + 0.3
V
–0.3 to 13
V
P2 7, P30–P3 2, R, G, B,
OUT1, D-A, X OUT, OSC2
VO
Output voltage
P00–P05
I OH
Circuit current
R , G , B , O U T 1 , P 1 0– P 1 7,
P2 0–P2 7, P3 0, P3 1, D-A
0 to 1 (Note 1)
mA
IOL1
Circuit current
R, G, B, OUT1, P06, P0 7,
P1 0, P15–P1 7, P20–P2 3,
P3 0–P32, D-A
0 to 2 (Note 2)
mA
IOL2
P11–P14
P00–P05
0 to 6 (Note 2)
mA
IOL3
Circuit current
Circuit current
0 to 1 (Note 2)
mA
IOL4
Circuit current
P24–P27
Pd
Power dissipation
Topr
Tstg
Operating temperature
T a = 25 °C
Storage temperature
0 to 10 (Note 3)
mA
550
mW
–10 to 70
–40 to 125
°C
°C
Notes 1: The total current that flows out of the IC must be 20 mA (max.).
2: The total input current to IC (I OL1 + I OL2 + I OL3) must be 30 mA or less.
3: The total average input current for ports P2 4–P2 7 to IC must be 20 mA or less.
3-2
7220 Group User’s Manual
ELECTRICAL CHARACTERISTICS
3.1 Electrical characteristics
Recommended operating conditions (Ta = –10 °C to 70 °C, VCC = 5 V ± 10 %, unless otherwise noted)
Parameter
Min. Typ.
Symbol
Power source voltage (Note 4), During CPU, CRT operation
VCC
5.0
4.5
Power source voltage
VSS
0
0
HIGH
input
voltage
P0
0
–P0
7
,P1
0
–P1
7
,
P2
0
–P2
7
,
VIH1
0.8VCC
P30–P3 4, S IN, S CLK, H SYNC,
VSYNC, RESET, X IN, OSC1,
TIM2, TIM3, INT1, INT2, INT3
HIGH input voltage
VIH2
SCL1, SCL2, SDA1, SDA2
Max.
5.5
Unit
V
0
VCC
V
V
0.7VCC
VCC
V
(When using I2C-BUS)
VIL1
LOW input voltage
P00–P07,P10–P17, P2 0–P2 7,
P30–P3 4
0
0.4VCC
V
VIL2
LOW input voltage
SCL1, SCL2, SDA1, SDA2
0
0.3VCC
V
0
0.2VCC
V
1
mA
(When using I2C-BUS)
H SYNC, V SYNC, RESET, TIM2,
TIM3, INT1, INT2, INT3, XIN,
OSC1, S IN, S CLK
LOW input voltage
VIL3
HIGH average output current (Note 1)
I OH
R, G, B, OUT1, D-A,
P10–P17, P2 0–P2 7, P30, P3 1
I OL1
LOW average output current (Note 2)
R, G, B, OUT1, D-A, P06, P07,
P10, P15–P17, P20–P27, P30–
P32
2
mA
I OL2
LOW average output current (Note 2)
P11–P1 4
6
I OL3
P00–P0 5
P2 4–P2 7
1
I OL4
LOW average output current (Note 2)
LOW average output current (Note 3)
mA
mA
10
mA
f(X IN)
Oscillation frequency (for CPU operation) (Note 5) XIN
7.9
8.1
MHz
f CRT
f hs1
Oscillation frequency (for CRT display) (Note 5)
5.0
8.0
MHz
Input frequency
TIM2, TIM3
kHz
f hs2
Input frequency
SCLK
100
1
f hs3
Input frequency
SCL1, SCL2
400
OSC1
8.0
MHz
kHz
Notes 1:
2:
3:
4:
The total current that flows out of the IC must be 20 mA (max.).
The total input current to IC (I OL1 + I OL2 + I OL3) must be 30 mA or less.
The total average input current for ports P2 4 –P2 7 to IC must be 20 mA or less.
Connect 0.1 µ F or more capacitor externally across the power source pins V CC –V SS so as to
reduce power source noise. Also connect 0.1 µ F or more capacitor externally across the pins
VCC–CNVSS.
5: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit.
7220 Group User’s Manual
3-3
ELECTRICAL CHARACTERISTICS
3.1 Electrical characteristics
Electric characteristics (V CC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted)
Symbol
I CC
VOH
VOL
Power source current
Limits
Unit
Min. Typ. Max.
V,
40
20
mA
CRT OFF
MHz CRT ON
60
30
300 µ A
V, f(X IN ) = 0
V
V
2.4
Test conditions
Parameter
System operation
V CC = 5.5
f(X IN) = 8
Stop mode
V CC = 5.5
HIGH output voltage R, G, B, OUT1, D-A, V CC = 4.5
I OH = –0.5 mA
P1 0–P17, P20–P27,
P3 0, P3 1
LOW output voltage R, G, B, OUT1, D-A, V CC = 4.5 V
I OL = 0.5 mA
P0 0–P0 7, P10,
0.4
V
P1 5–P17, P20–P23,
P3 0–P32
V CC = 4.5 V
LOW output voltage P11–P14
VT+–V T–
I IZH
I IZL
I OZH
LOW output voltage P24–P27
V CC = 4.5 V
I OL = 10.0 mA
Hysteresis
Hysteresis (Note)
V CC = 5.0 V
RESET
H SYNC, V SYNC, TIM2,
TIM3, INT1, INT2,
INT3, SCL1, SCL2,
SDA1, SDA2, S IN,
SCLK
V CC = 5.0 V
HIGH input leak current RESET, P00–P0 7,
P1 0–P17, P20–P27,
P3 0–P3 4, HSYNC,
VSYNC
V CC = 5.5 V
LOW input leak current
V CC = 5.5 V
RESET, P00–P0 7,
P1 0–P17, P20–P27,
P3 0–P3 4, HSYNC,
VSYNC
HIGH output leak current P0 0–P05
I OL = 3 mA
0.4
I OL = 6 mA
0.6
3.0
0.5
0.5
0.7
V
1.3
5
µA
5
µA
10
µA
130
W
V I = 5.5 V
VI = 0 V
V CC = 5.5 V
V O = 12 V
R BS
2
I C-BUS·BUS switch connection resistor V CC = 4.5 V
(between SCL1 and SCL2, SDA1 and SDA2)
Note: P0 6, P07, P15 , P23 and P24 have the hysteresis when these pins are used as interrupt input pins or
timer input pins. P20–P22 have the hysteresis when these pins are used as serial I/O pins. P1 1–P14
have the hysteresis when these pins are used as multi-master I 2C-BUS interface pins.
3-4
7220 Group User’s Manual
ELECTRICAL CHARACTERISTICS
3.1 Electrical characteristics
A-D Comparator characteristics
(V CC = 5 V ± 10 %, V SS = 0 V, f(X IN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted)
Test conditions
Parameter
Symbol
—
Resolution
—
Absolute accuracy
Min.
0
Limits
Typ.
Max.
±1
Unit
6
bits
±2
LSB
Note: When V CC = 5 V, 1 LSB = 5/64 V.
Multi-master I 2C-BUS bus line characteristics
Standard clod mode High-speed clock mode
Unit
Min.
Max.
Typ.
Max.
µs
4.7
1.3
Parameter
Symbol
t BUF
Bus free time
t HD:STA
Hold time for START condition
4.0
0.6
t LOW
4.7
tR
LOW period of SCL clock
Rising time of both SCL and SDA signals
1.3
20+0.1C b
300
t HD:DAT
Data hold time
0
0.9
t HIGH
HIGH period of SCL clock
tF
Falling time of both SCL and SDA signals
t SU:DAT
Data set-up time
250
100
t SU:STA
t SU:STO
Set-up time for repeated START condition
Set-up time for STOP condition
4.7
0.6
0.6
1000
0
4.0
0.6
300
4.0
20+0.1C b
300
µs
µs
ns
µs
µs
ns
ns
µs
µs
Note: C b = total capacitance of 1 bus line
SDA
tHD:STA
tBUF
tLOW
P
tR
tSU:STO
tF
Sr
S
P
SCL
tHD:STA
tHD:DAT
tHIGH
tSU:DAT
tSU:STA
S : Start condition
Sr : Restart condition
P : Stop condition
Fig. 3.1.1 Definition diagram of timing on multi-master I 2C-BUS
7220 Group User’s Manual
3-5
ELECTRICAL CHARACTERISTICS
3.1
3.2 Electrical
Standard characteristics
characteristics
3.2 Standard characteristics
The data described in this section are characteristic examples. Refer to “3.1 Electrical characteristics” for
rated values.
1. Ports P00–P05 and P32
(a) IOL–VOL characteristics
LOW level output current I OL [mA]
100.00
80.00
VCC=5.5V
60.00
40.00
VCC=4.5V
20.00
0.000
0.000
1.200
2.400
3.600
4.800
6.000
LOW level output voltage V OL [V]
2. Ports P06 and P07
(a) IOH–VOL characteristics
HIGH level output current I OH [mA]
100.00
80.00
60.00
VCC=5.5V
40.00
VCC=4.5V
20.00
0.000
0.000
1.200
2.400
3.600
LOW level output voltage V OL [V]
3-6
7220 Group User’s Manual
4.800
6.000
ELECTRICAL CHARACTERISTICS
3.1
3.2 Electrical
Standard characteristics
3. Ports P10, P15–P17, P20–P23, P30, P31 and D-A
(a) IOL–VOL characteristics
LOW level output current I OL [mA]
100.00
80.00
60.00
VCC=5.5V
40.00
VCC=4.5V
20.00
0.000
0.000
1.200
2.400
3.600
4.800
6.000
LOW level output voltage V OL [V]
(b) IOH–VOH characteristics
HIGH level output current I OH [mA]
– 100.00
– 80.00
– 60.00
VCC=5.5V
– 40.00
– 20.00
VCC=4.5V
0.000
0.000
–1.200
– 2.400
– 3.600
– 4.800
– 6.000
HIGH level output voltage V OH [V]
7220 Group User’s Manual
3-7
ELECTRICAL CHARACTERISTICS
3.1
3.2 Electrical
Standard characteristics
characteristics
4. Ports P11–P14
(a) IOL–VOL characteristics
LOW level output current I OL [mA]
100.00
80.00
VCC=5.5V
60.00
VCC=4.5V
40.00
20.00
0.000
0.000
1.200
2.400
3.600
4.800
6.000
LOW level output voltage V OL [V]
(b) IOH–VOH characteristics
HIGH level output current I OH [mA]
– 100.00
– 80.00
– 60.00
VCC=5.5V
– 40.00
– 20.00
VCC=4.5V
0.000
0.000
– 1.200
– 2.400
– 3.600
HIGH level output voltage V OH [V]
3-8
7220 Group User’s Manual
– 4.800
– 6.000
ELECTRICAL CHARACTERISTICS
3.1
3.2 Electrical
Standard characteristics
LOW level output current I OL [mA]
5. Ports P24–P27
(a) IOL–VOL characteristics
100.00
80.00
60.00
VCC=5.5V
40.00
VCC=4.5V
20.00
0.000
0.000
1.200
2.400
3.600
4.800
6.000
LOW level output voltage V OL [V]
(b) IOH–VOH characteristics
HIGH level output current I OH [mA]
– 100.00
– 80.00
– 60.00
VCC=5.5V
– 40.00
– 20.00
0.000
0.000
VCC=4.5V
–1.200
– 2.400
– 3.600
– 4.800
– 6.000
HIGH level output voltage V OH [V]
7220 Group User’s Manual
3-9
ELECTRICAL CHARACTERISTICS
3.1
3.2 Electrical
Standard characteristics
characteristics
6. Ports P52–P55
(a) IOL–VOL characteristics
LOW level output current I OL [mA]
100.00
80.00
60.00
40.00
VCC=5.5V
20.00
VCC=4.5V
0.000
0.000
1.200
2.400
3.600
4.800
6.000
LOW level output voltage V OL [V]
(b) IOH–VOH characteristics
HIGH level output current I OH [mA]
– 100.00
– 80.00
– 60.00
– 40.00
– 20.00
0.000
0.000
VCC=5.5V
VCC=4.5V
– 1.200
– 2.400
– 3.600
HIGH level output voltage V OH [V]
3-10
7220 Group User’s Manual
– 4.800
– 6.000
CHAPTER 4
M37220M3-XXXSP/FP
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Performance overview
Pin configuration
Pin description
Functional block diagram
Functional description
Electrical characteristics
Standard characteristics
M37220M3-XXXSP/FP
4.1 Performance overview
4.1 Performance overview
This chapter is described about M37220M3-XXXSP/FP.
M37220M3-XXXSP/FP has the common functions with M37221M6-XXXSP/FP except for part of functions.
This chapter explains the differences between M37220M3-XXXSP/FP and M37221M6-XXXSP/FP. Therefore,
refer to the corresponding descriptions of M37221M6-XXXSP/FP about the common functions.
The 8-bit microcomputer M37220M3-XXXSP/FP has many additional functions for tuning system for TV:
Table 4.1.1 Performance overview (1)
Parameter
Number of basic instructions
Performance
71
Instruction execution time
0.5 µ s (the minimum instruction execution time, at 8
MHz oscillation frequency)
Clock frequency
8 MHz (maximum)
12 K bytes
Memory size
Input/Output ports
ROM
RAM
CRT ROM
256 bytes
CRT RAM
80 bytes
4 K bytes
P0 0–P07
I/O
8-bit ✕ 1 (N-channel open-drain output structure, can be
used as PWM output pins, INT input pins, A-D input pin)
P1 0–P17
I/O
P20, P2 1
I/O
8-bit ✕ 1 (CMOS input/output structure, can be used as
A-D input pins, INT input pin)
2-bit ✕ 1 (CMOS input/output or N-channel open-drain
output structure, can be used as serial I/O pins)
P2 2–P27
I/O
6-bit ✕ 1 (CMOS input/output structure, can be used as
serial input pin, external clock input pins)
P30, P3 1
I/O
2-bit ✕ 1 (CMOS input/output or N-channel open-drain
output structure, can be used as D-A conversion output
pins, A-D input pins)
P3 2
I/O
1-bit ✕ 1 (N-channel open-drain output structure)
P33, P3 4
P5 2–P55
Input
Output
2-bit ✕ 1 (can be used as CRT display clock I/O pins)
4-bit ✕ 1 (CMOS output structure, can be used as CRT
output pins)
Serial I/O
8-bit ✕ 1
A-D comparator
6 channels (6-bit resolution)
D-A converter
PWM output circuit
2 (6-bit resolution)
Timers
8-bit timer ✕ 4
96 levels (maximum)
Subroutine nesting
14-bit ✕ 1, 8-bit ✕ 6
Interrupt
External interrupt ✕ 3, Internal timer interrupt ✕ 4, Serial
I/O interrupt ✕ 1, CRT interrupt ✕ 1, f(XIN)/4096 interrupt
✕ 1, VSYNC interrupt ✕ 1, BRK interrupt ✕ 1
Clock generating circuit
2 built-in circuits (externally connected a ceramic resonator
or a quartz-crystal oscillator)
Power source voltage
5 V ± 10 %
4-2
7220 Group User’s Manual
M37220M3-XXXSP/FP
4.1 Performance overview
Table 4.1.2 Performance overview (2)
Power dissipation
Parameter
CRT ON
Performance
165 mW typ. (at oscillation frequency f(XIN ) = 8 MHz,
f CRT = 8 MHz)
CRT OFF
110 mW typ. (at oscillation frequency f(XIN) = 8 MHz)
In stop mode
1.65 mW (maximum)
6
12V withstand ports
LED drive ports
Operating temperature range
4
–10 °C to 70 °C
Device structure
CMOS silicon gate process
Package
CRT display function
M37220M3-XXXSP
42-pin shrink plastic molded DIP
M37220M3-XXXFP
42-pin shrink plastic molded SOP
Number of display characters
Dot structure
20 characters ✕ 2 lines (maximum 16 lines by software)
Kinds of characters
12 ✕ 16 dots
128 kinds
Kinds of character sizes
3 kinds
Kinds of character
colors
Maximum 7 kinds (R, G, B); can be specified by the
character
Display position (horizontal, vertical)
64 levels (horizontal) ✕ 128 levels (vertical)
7220 Group User’s Manual
4-3
M37220M3-XXXSP/FP
4.2 Pin configuration
4.2 Pin configuration
The pin configurations are shown in Figures 4.2.1 and 4.2.2.
1
42
P52/R
2
3
41
40
P53/G
P54/B
P01/PWM1
P02/PWM2
4
39
5
6
38
37
7
8
36
35
P55/OUT
P20/SCLK
P21/SOUT
P22/SIN
P03/PWM3
P04/PWM4
P05/PWM5
P06/INT2/A-D4
P07/INT1
P23/TIM3
P24/TIM2
P25
P26
P27
D-A
P32
9
10
11
12
13
14
15
M37220M3-XXXSP
HSYNC
VSYNC
P00/PWM0
34
33
32
31
30
29
28
P12
P13
P14
P15/A-D1/INT3
P16/A-D2
P17/A-D3
27
26
25
P30/A-D5/DA1
XIN
16
17
18
19
24
XOUT
20
23
OSC1/P33
OSC2/P34
VSS
21
22
VCC
CNVSS
Package type : 42P4B
Fig. 4.2.1 Pin configuration (top view) (1)
4-4
P10
P11
7220 Group User’s Manual
P31/A-D6/DA2
RESET
M37220M3-XXXSP/FP
4.2 Pin configuration
1
42
P52/R
2
3
41
40
P01/PWM1
P02/PWM2
4
39
P53/G
P54/B
P55/OUT
P03/PWM3
5
6
38
37
P20/SCLK
P21/SOUT
P04/PWM4
P05/PWM5
7
8
36
P22/SIN
P10
P06/INT2/A-D4
9
10
P07/INT1
M37220M3-XXXFP
HSYNC
VSYNC
P00/PWM0
35
34
33
P23/TIM3
P24/TIM2
P25
P26
11
12
P27
D-A
P32
15
31
30
29
28
16
17
27
26
CNVSS
18
19
25
24
20
21
23
22
XIN
XOUT
VSS
13
14
32
P11
P12
P13
P14
P15/A-D1/INT3
P16/A-D2
P17/A-D3
P30/A-D5/DA1
P31/A-D6/DA2
RESET
OSC1/P33
OSC2/P34
VCC
Package type : 42P2R-A
Fig. 4.2.2 Pin configuration (top view) (2)
7220 Group User’s Manual
4-5
M37220M3-XXXSP/FP
4.3 Pin description
4.3 Pin description
The pin description of M37220M3-XXXSP/FP is shown in Table 4.3.1.
Table 4.3.1 Pin description (1)
Pin
Name
Input/
Output
Functions
VCC,
VSS
Power source
Apply voltage of 5 V ± 10 % (typical) to V CC, and 0 V to V SS.
CNVSS
CNVSS
This is connected to V SS.
RESET
Reset input
Input
To enter the reset state, the reset input pin must be kept at a “L” for
2 µ s or more (under normal V CC conditions).
If more time is needed for the quartz-crystal oscillator to stabilize, this
“L” condition should be maintained for the required time.
XIN
Clock input
XOUT
Clock output
P0 0
I/O port P0
PWM0–
P0 5/
PWM5,
P 0 6 / I N T 2 / PWM output
A-D4,
P0 7/INT1
External
interrupt input
Analog input
P1 1–P14,
Input
This chip has an internal clock generating circuit. To control generating
frequency, an external ceramic resonator or a quartz-crystal oscillator
is connected between pins XIN and X OUT. If an external clock is used,
Output
the clock source should be connected to the XIN pin and the X OUT pin
should be left open.
I/O
Port P0 is an 8-bit I/O port with direction register allowing each I/O bit
to be individually programmed as input or output. At reset, this port is
set to input mode. The output structure is N-channel open-drain output.
The note out of this Table gives a full of port P0 function.
Output Pins P0 0 –P0 5 are also used as PWM output pins PWM0–PWM5
respectively. The output structure is N-channel open-drain output.
Input Pins P0 6 , P0 7 are also used as external interrupt input pins INT2,
INT1 respectively.
Input
Port P1 is an 8-bit I/O port and has basically the same functions as
port P0. The output structure is CMOS output.
Analog input
Input
Pins P1 5 –P1 7 are also used as analog input pins A-D1 to A-D3
respectively.
External
Input
P1 5 pin is also used as external interrupt input pin INT3.
P1 5/A-D1/
INT3,
P1 6/A-D2,
P1 7/A-D3
P0 6 pin is also used as analog input pin A-D4.
I/O
I/O port P1
interrupt input
4-6
7220 Group User’s Manual
M37220M3-XXXSP/FP
4.3 Pin description
Table 4.3.2 Pin description (2)
Input/
Pin
Name
Functions
Output
P2 0/S CLK, I/O port P2
I/O
Port P2 is an 8-bit I/O port and has basically the same functions as
port P0. The output structure is CMOS output.
P2 1/S OUT,
P2 2/S IN,
External clock
P2 3/TIM3, input
P2 4/TIM2, Serial I/O
P2 5–P27
Input
Pins P2 3, P24 are also used as external clock input pins TIM3, TIM2
respectively.
I/O
P20 pin is also used as serial I/O synchronous clock input/output pin
SCLK. The output structure is N-channel open-drain output.
I/O
Pins P2 1, P2 2 are also used as serial I/O data input/output pins SOUT,
SIN respectively. The output structure is N-channel open-drain output.
Ports P30–P32 are 3-bit I/O ports and have basically the same functions
as port P0. Either CMOS output or N-channel open-drain output structure
can be selected as the port P3 0 and P31. The output structure of port
P32 is N-channel open-drain output.
synchronous
clock input/
output
Serial I/O data
input/output
P3 0 /A-D5/ I/O port P3
DA1,
I/O
P3 1 /A-D6/
DA2, P3 2
Input Pins P30, P31 are also used as analog input pins A-D5, A-D6 respectively.
D-A conversion Output Pins P3 0, P31 are also used as D-A conversion output pins DA1, DA2
respectively.
output
Analog input
P3 3/OSC1, Input port P3
P3 4/OSC2 Clock input for
CRT display
Input
Ports P3 3, P3 4 are 2-bit input ports.
Input
P3 3 pin is also used as CRT display clock input pin OSC1.
P5 3/G,
Clock output for Output P3 4 pin is also used as CRT display clock output pin OSC2. The
output structure is CMOS output.
CRT display
Output port P5 Output Ports P5 2–P55 are 4-bit output ports. The output structure is CMOS
output.
P5 4/B,
CRT output
P5 2/R,
P5 5/OUT
Output Pins P52–P55 are also used as CRT output pins R, G, B, OUT respectively.
The output structure is CMOS output.
H SYNC
VSYNC
H SYNC input
Input
This is a horizontal synchronous signal input for CRT.
VSYNC input
Input
This is a vertical synchronous signal input for CRT.
D-A
DA output
Output This is a 14-bit PWM output pin.
7220 Group User’s Manual
4-7
15 14 13 12 11 36 37 38
28 29 30 31 32 33 34 35
I/O port P1
10 9 8 7 6 5 4 3
I/O port P0
Fig. 4.4.1 Functional block diagram
I/O port P2
P2 (8)
A-D
comparator
22
14-bit
PWM circuit
16
D-A
21
TIM3
TIM2
I/O ports P3 0–P32
17 26 27
P3 (3)
Stack
pointer
S (8)
18
VSS CNV SS
ROM
12 K bytes
VCC
Index
register
Y (8)
PC L (8)
PC H (8)
Index
register
X (8)
Program
counter
Program
counter
P1 (8)
Accumulator
A (8)
Processor
status
register
PS (8)
RAM
256 bytes
Data bus
25
P0 (8)
8-bit
arithmetic
and
logical unit
Address bus
Clock
generating
circuit
20
INT3
19
INT2
INT1
D-A
converter
Timer 4
T4 (8)
Timer 3
T3 (8)
Timer 2
T2 (8)
Timer 1
T1 (8)
Timer count source
selection circuit
8-bit PWM circuit
SI/O(8)
Instruction
register (8)
Instruction
decoder
Control signal
23
CRT circuit
24
P5 (4)
Input ports P3 3, P34
Clock input for display Clock output for display
OSC1 OSC2
SIN
SCLK
SOUT
Reset input
RESET
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
7220 Group User’s Manual
2 1
Output ports P5 2–P5 5
39 40 41 42
OUT
B
G
R
4-8
VSYNC
HSYNC
Clock input Clock output
XIN XOUT ( ) Timing output
M37220M3-XXXSP/FP
4.4 Functional block diagram
4.4 Functional block diagram
The functional block diagram is shown in Figure 4.4.1.
M37220M3-XXXSP/FP
4.5 Functional description
4.5 Functional description
Functions of M37220M3-XXXSP/FP are partially different from those of M37221M6-XXXSP/FP. Table 4.5.1
shows the difference between M37220M3-XXXSP/FP and M37221M6-XXXSP/FP.
Table 4.5.1 Difference between M37220M3-XXXSP/FP and M37221M6-XXXSP/FP
M37221M6-XXXSP/FP
M37220M3-XXXSP/FP
Paramater
33
33
Programmable I/O ports
8 bits
8 bits
Port P0
8 bits
8 bits
Port P1
(Functions except port are
partially different.)
Port P2
8 bits
8 bits
Port P3
8 bits
8 bits
(Functions except port are
partically different.)
Port P5
4 bits
4 bits
No multi-master I C-BUS
There is multi-master I2C-BUS
interface interrupt
interface interrupt
2
Interrupts
(Priority level is the same as
D-A converter
M37221M6-XXXSP/FP.)
Included
2 (6-bit resolution)
Included
Multi-master I2C-BUS interface
1 (2 systems)
CRT display function
Number of display characters
20 characters ✕ 2 lines
24characters ✕ 2 lines
Kinds of characters
128 kinds
256 kinds
Kinds of character back
Not available
Possible
(It can be specified by the character.)
ground colors
Maximum 7 kinds
7220 Group User’s Manual
4-9
M37220M3-XXXSP/FP
4.5 Functional description
4.5.1 Access area
Figure 4.5.1 shows the M37220M3-XXXSP/FP access area.
000016
RAM
(256 bytes)
Zero page
00C0 16
SFR area
00FF16
(Refer to Figures 4.5.3 and 4.5.4)
CRT display ROM
(4 K bytes)
Special function register
013F16
65536
1000016
Internal RAM
(192 bytes)
ROM
for display
10FFF16
69631
Internal RAM
(64 bytes)
Not used
CRT display RAM
(80 bytes)
(Note)
060016
06B316
RAM
for display
Not used
Not used
D000 16
: Internal ROM area for
program counter
Internal ROM
ROM
(12 K bytes)
FF0016
FFDE16
FFFF16
Interrupt vector area
Special page
1FFFF 16
Note: Refer to Table 4.5.7 Contents of CRT display RAM.
Fig. 4.5.1 Access area
4-10
7220 Group User’s Manual
131071
M37220M3-XXXSP/FP
4.5 Functional description
4.5.2 Memory assignment
Figure 4.5.2 shows the memory assignment M37220M3-XXXSP/FP.
Hexadecimal notation
Decimal notation
000016
0
Internal RAM
(192 bytes)
RAM
(256 bytes)
00C0 16
SFR area
192
1000016
CRT display ROM
(4 K bytes)
Zero page
Special function register
00FF16
013F16
(Refer to Figures 4.5.3 and 4.5.4)
Internal RAM
(64 bytes)
65536
ROM
for display
10FFF16
255
69631
319
Not used
CRT display RAM
(80 bytes)
(Note)
060016
06B316
RAM
for display
1536
1719
Not used
D000 16
Not used
53248
Internal ROM
ROM
(12 K bytes)
65280
65502
FF0016
FFDE16
FFFF16
Interrupt vector area
Special page
1FFFF 16
65535
131071
Note: Refer to Table 4.5.7 Contents of CRT display RAM.
Fig. 4.5.2 Memory assignment
7220 Group User’s Manual
4-11
M37220M3-XXXSP/FP
4.5 Functional description
■SFR Area (addresses C016 to DF16)
< Bit allocation >
< State immediately after reset >
0 : “0” immediately after reset
:
Function bit
Name
:
1 : “1” immediately after reset
: No function bit
? : Undefined immediately
after reset
0 : Fix this bit to “0”
(do not write “1”)
1 : Fix this bit to “1”
(do not write “0”)
Address
C016
C116
C216
C316
C416
C516
C616
C716
C816
C916
CA16
CB16
CC16
CD16
CE16
CF16
D016
D116
D216
D316
D416
D516
D616
D716
D816
D916
DA16
DB16
DC16
DD16
DE16
DF16
Register
Bit allocation
b7
Port P0 (P0)
Port P0 direction register (D0)
Port P1 (P1)
Port P1 direction register (D1)
Port P2 (P2)
Port P2 direction register (D2)
Port P3 (P3)
0
0
0
0
0
?
0
0
?
0
0
0
0
?
?
Port P3 direction register (D3)
Port P5 (P5)
Port P5 direction register (D5)
DA2S DA1S P31S P30S
Port P3 output mode control register (P3S)
DA-H register (DA-H)
DA-L register (DA-L)
PWM0 register (PWM0)
PWM1 register (PWM1)
PWM2 register (PWM2)
PWM3 register (PWM3)
PWM4 register (PWM4)
PWM output control register 1 (PW)
PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0
PN4 PN3 PN2
PWM output control register 2 (PN)
Serial I/O mode register (SM)
Serial I/O regsiter (SIO)
DA1 conversion register (DA1)
DA2 conversion register (DA2)
SM6 SM5
0
0
0
SM3 SM2 SM1 SM0
DA15 DA14 DA13 DA12 DA11 DA10
DA25 DA24 DA23 DA22 DA21 DA20
Fig. 4.5.3 Memory map of SFR (special function register) (1)
4-12
State immediately after reset
b0 b7
7220 Group User’s Manual
?
0016
?
0016
?
0016
? ?
0016
?
?
? ?
0016
?
0016
?
? ?
?
?
?
?
?
0016
0016
?
?
?
?
?
0016
?
? ?
? ?
b0
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
M37220M3-XXXSP/FP
4.5 Functional description
■SFR Area (addresses E016 to FF16)
< Bit allocation >
0 : “0” immediately after reset
:
Name
< State immediately after reset >
Function bit
:
1 : “1” immediately after reset
: No function bit
? : Undefined immediately
after reset
0 : Fix this bit to “0”
(do not write “1”)
1 : Fix this bit to “1”
(do not write “0”)
Address
E016
E116
E216
E316
E416
E516
E616
E716
E816
E916
EA16
EB16
EC16
ED16
EE16
EF16
F016
F116
F216
F316
F416
F516
F616
F716
F816
F916
FA16
FB16
FC16
FD16
FE16
FF16
Register
Bit allocation
b7
State immediately after reset
b0 b7
Horizontal position register (HR)
HR5 HR4 HR3 HR2 HR1 HR0
Vertical position register 1 (CV1)
Vertical position register 2 (CV2)
CV16 CV15 CV14 CV13 CV12 CV11 CV10
CV26 CV25 CV24 CV23 CV22 CV21 CV20
CS21 CS20 CS11 CS10
Character size register (CS)
Border selection register (MD)
Color register 0 (CO0)
CO05
CO03 CO02 CO01
Color register 1 (CO1)
CO15
CO13 CO12 CO11
Color register 2 (CO2)
CO25
CO23 CO22 CO21
Color register 3 (CO3)
CRT control register (CC)
CO35
CO33 CO32 CO31
CRT port control register (CRTP)
CRT clock selection register (CK)
MD20
MD10
b0
0
0
?
?
?
?
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
CC2 CC1 CC0
OP7 OP6 OP5 OUT
0
0
0
0
R/G/B VSYC HSYC
0
ADM4
A-D control register 1 (AD1)
A-D control register 2 (AD2)
Timer 1 (TM1)
0
CK1 CK0
ADM2 ADM1 ADM0
ADC5 ADC4 ADC3 ADC2 ADC1 ADC0
Timer 2 (TM2)
Timer 3 (TM3)
Timer 4 (TM4)
Timer 12 mode register (T12M)
0
T12M4 T12M3 T12M2 T12M1 T12M0
T34M5 T34M4 T34M3 T34M2 T34M1 T34M0
Timer 34 mode register (T34M)
PWM5 register (PWM5)
Interrupt input polarity register (RE)
Test register (TEST)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
0
1
RE5 RE4
CK0 RE3
1
IT3R
1
0
0
CM2
0
0
VSCR CRTR TM4R TM3R TM2R TM1R
0
S1R 1T2R 1T1R
MSR
CK0
IT3E
0
0016
1 1
VSCE CRTE TM4E TM3E TM2E TM1E
0
0
MSE
0
S1E 1T2E 1T1E
0016
? ?
? ?
?
0 ?
0 0
0016
0016
0016
0016
0016
?
0016
0016
? 0
0016
FF16
0716
FF16
0716
0016
0016
?
?
?
0 0
0016
1 1
0016
0016
0016
0016
?
?
?
?
?
?
?
?
?
0
?
?
0
0
0
0
0
?
1
0
0
Fig. 4.5.4 Memory map of SFR (special function register) (2)
7220 Group User’s Manual
4-13
M37220M3-XXXSP/FP
4.5 Functional description
4.5.3 Input/Output pins
Table 4.5.2 shows the difference of programmable ports between M37221M6-XXXSP/FP and M37220M3XXXSP/FP.
Table 4.5.2 Difference of programmable ports between M37221M6-XXXSP/FP and M37220M3XXXSP/FP
Functions except port
Port
P0 0–P05
✽
M37221M6-XXXSP/FP
PWM0–PWM5
P0 6
✽
INT2/A-D4
P0 7
✽
INT1
P1 0
No function
OUT2
P1 1
No function
SCL1
P1 2
P1 3
No function
No function
SCL2
SDA1
P1 4
No function
SDA2
P1 5
✽
A-D1/INT3
P1 6
✽
A-D2
P1 7
✽
A-D3
P2 0
P2 1
✽
✽
SCLK
SOUT
P2 2
✽
SIN
P2 3
✽
TIM3
P2 4
✽
TIM2
P2 5–P27
✽
A-D5/DA1
—
A-D5
A-D6/DA2
A-D6
P3 2
✽
—
P3 3
✽
OSC1
P3 4
✽
OSC2
P5 2
✽
✽
R
G
✽
B
OUT
OUT1
M37220M3-XXXSP/FP
P3 0
P3 1
P5 3
P5 4
P5 5
✽: It is the same as M37221M6-XXXSP/FP.
4-14
7220 Group User’s Manual
M37220M3-XXXSP/FP
4.5 Functional description
4.5.4 Interrupts
The M37220M3-XXXSP/FP has 13 sources (reset is included) of interrupts.
Table 4.5.3 Interrupt sources, vector addresses and priority
Priority
Interrupt sources
Vector addresses
High-order byte Low-order byte
FFFF16
FFFE16
Remarks
1
2
Reset (Note)
CRT interrupt
FFFD 16
FFFC16
3
INT2 interrupt
FFFB16
FFFA16
Active edge selectable
4
INT1 interrupt
FFF9 16
FFF816
Active edge selectable
5
Timer 4 interrupt
f(XIN)/4096 interrupt
FFF5 16
FFF416
FFF216
FFF016
6
7
8
VSYNC interrupt
FFF3 16
FFF1 16
Timer 3 interrupt
FFEF16
FFEE16
9
Timer 2 interrupt
FFED16
FFEC16
10
Timer 1 interrupt
FFEB 16
FFEA16
11
Serial I/O interrupt
INT3 interrupt
FFE916
FFE816
12
13
BRK instruction interrupt
FFE516
FFDF 16
FFE416
FFDE16
Non-maskable
Active edge selectable
Active edge selectable
Non-maskable (software interrupt)
Note: Reset are included in the table because it operates in the same way as interrupts.
The different interrupt-related registers from those of M37221M6-XXXSP/FP are shown in the following
pages.
7220 Group User’s Manual
4-15
M37220M3-XXXSP/FP
4.5 Functional description
Interrupt Request Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address 00FC16]
B
Name
0
Functions
0 : No interrupt request issued
Timer 1 interrupt
1 : Interrupt request issued
request bit (TM1R)
Timer 2 interrupt
0 : No interrupt request issued
request bit (TM2R)
1 : Interrupt request issued
0 : No interrupt request issued
Timer 3 interrupt
1 : Interrupt request issued
request bit (TM3R)
0 : No interrupt request issued
Timer 4 interrupt
1 : Interrupt request issued
request bit (TM4R)
0 : No interrupt request issued
CRT interrupt
request bit (CRTR) 1 : Interrupt request issued
0 : No interrupt request issued
V SYNC interrupt
request bit (VSCR) 1 : Interrupt request issued
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
INT3 interrupt
0 : No interrupt request issued
request bit (IT3R)
1 : Interrupt request issued
1
2
3
4
5
6
7
After reset R W
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R —
0
R ✽
✽: “0” can be set by software, but “1” cannot be set.
Fig. 4.5.5 Interrupt request register 1 (address 00FC 16)
Interrupt Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address 00FE16]
B
0
1
2
3
4
5
6
7
Name
Functions
Timer 1 interrupt
enable bit (TM1E)
0 : Interrupt disabled
1 : Interrupt enabled
Timer 2 interrupt
0 : Interrupt disabled
enable bit (TM2E)
1 : Interrupt enabled
Timer 3 interrupt
0 : Interrupt disabled
enable bit (TM3E)
1 : Interrupt enabled
Timer 4 interrupt
0 : Interrupt disabled
enable bit (TM4E)
1 : Interrupt enabled
0 : Interrupt disabled
CRT interrupt enable
1 : Interrupt enabled
bit (CRTE)
VSYNC interrupt
0 : Interrupt disabled
enable bit (VSCE)
1 : Interrupt enabled
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
INT3 interrupt
enable bit (IT3E)
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 4.5.6 Interrupt control register 1 (address 00FE 16)
4-16
7220 Group User’s Manual
After reset R W
0
R W
0
R W
0
R W
0
R W
0
R W
0
R W
0
R —
0
R W
M37220M3-XXXSP/FP
4.5 Functional description
4.5.5 D-A converter
M37220M3-XXXSP/FP has 2 D-A converter with 6-bit resolution. Figure 4.5.7 shows the D-A converter
block diagram.
Data bus
DA1 conversion register
6
DA2 conversion register
6
(address 00DE 16)
(address 00DF 16)
Resistor ladder
Resistor ladder
DA2 output enable bit
DA1 output enable bit
P30 /A-D5/DA1
P31/A-D6/DA2
Fig. 4.5.7 D-A converter block diagram
D-A conversion is performed by setting the value in
the DA conversion register. The result of D-A
conversion is output from the DA pin by setting “1”
to the DA output enable bit of the port P3 output
mode control register (bits 2 and 3 at address 00CD16).
The output analog voltage V is determined with the
value n (n: decimal number) in the DA conversion
register.
V=V CC
✕ n (n= 0 to 63)
64
The DA output does not build in a buffer, so connect
an external buffer when driving a low-impedance
load.
Table 4.5.4 Relationship between contents of D-A conversion
register and output voltage “V”
Output
A-D control register
voltage “V”
bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0
0
0
0
0
0
0/64 V CC
0
0
0
0
0
1
1/64 V CC
0
:
0
:
0
:
0
:
1
:
0
:
2/64 V CC
1
1
1
1
0
1
1
1
1
1
1
0
61/64 V CC
62/64 V CC
1
1
1
1
1
1
63/64 V CC
7220 Group User’s Manual
:
4-17
M37220M3-XXXSP/FP
4.5 Functional description
DA n Conversion Register
b7 b6 b5 b4 b3 b2 b1 b0
0
DA n conversion register (DAn) (n = 1 and 2) [Address 00DE 16, 00DF 16]
B
Name
0 DA conversion set
to bits
5 (DAn0–DAn5)
Functions
b5
0
0
0
b4
0
0
0
b3
0
0
0
b2
0
0
0
b1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
b0
0 : 0/64Vcc
1 : 1/64Vcc
0 : 2/64Vcc
After reset
Indeterminate R W
1 : 61/64Vcc
0 : 62/64Vcc
1 : 63/64Vcc
6 Fix this bit to “0.”
0
R —
7
0
R —
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “ 0.”
Fig. 4.5.8 DA n conversion register (addresses 00DE 16 and 00DF 16)
Port P3 Output Mode Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Port P3 output mode control register (P3S) [address 00CD 16]
B
Name
Functions
After reset R W
0
P30 output structure
selection bit (P30S)
0 : CMOS output
1 : N-channel open-drain output
0
R W
1
P31 output structure
selection bit (P31S)
0 : CMOS output
1 : N-channel open-drain output
0
R W
2
DA1 output enable bit
(DA1S)
0 : P3 0 input/output
1 : DA1 output
0
R W
3
DA2 output enable bit
(DA2S)
0 : P3 1 input/output
1 : DA2 output
0
R W
4
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
0
R —
Fig. 4.5.9 Port P3 output mode control register (address 00CD16)
4-18
R W
7220 Group User’s Manual
M37220M3-XXXSP/FP
4.5 Functional description
4.5.6 CRT Display function
Table 4.5.5 shows the outline the CRT display function of the M37220M3-XXXSP/FP.
Table 4.5.5 Outline of CRT display function
Parameter
Number of display character
Performance
20 characters ✕ 2 lines
Kinds of character
12 dots ✕ 16 dots
128 kinds
Kinds of character sizes
3 kinds
Dot structure
Color
Kind of colors
1 screen; 4 kinds, maximum 7 kinds
Coloring unit
Display extension
A character
Raster coloring
Possible (maximum 7 kinds)
Possible (multiline display)
7220 Group User’s Manual
4-19
M37220M3-XXXSP/FP
4.5 Functional description
OSC1
OSC2
H SYNC VSYNC
(Address 00EA 16)
CRT control register
Display oscillation
circuit
(Addresses 00E1 16, 00E2 16)
Vertical position registers
(Address 00E4 16)
Character size register
Display position control circuit
(Address 00E0 16)
Horizontal position register
(Address 00E5 16)
Border selection register
Display control
circuit
RAM for display
9 bits ✕ 20 characters ✕
2 lines
ROM for display
12 bits ✕ 16 dots ✕
128 characters
(Addresses 00E6 16
to 00E9 16)
Shift register
12 bits
Color registers
Shift register
12 bits
(Address 00EC 16)
Output circuit
CRT port control register
Data bus
R
Fig. 4.5.10 CRT display circuit block diagram
4-20
7220 Group User’s Manual
G
B
OUT
M37220M3-XXXSP/FP
4.5 Functional description
(1) Memory for display
There are 2 types of display memory: CRT display ROM (addresses 1000016 to 10FFF16) and CRT
display RAM (addresses 0600 16 to 06B316). Each type of display memory is described below.
■ CRT display ROM (addresses 1000016 to 10FFF16)
CRT display ROM has a capacity of 4 K bytes. Since 32 bytes are required for 1 character data,
the ROM can stores up to 128 kinds of characters.
CRT display ROM is broadly divided into 2 areas. The [vertical 16 dots] ✕ [horizontal (left side)
8 dots] data of display characters are stored in addresses 10000 16 to 107FF 16 ; the [vertical 16
dots] ✕ [horizontal (right side) 4 dots] data of display characters are stored in addresses 1080016
to 10FFF 16 (refer to “Figure 4.5.11”). Note however that the high-order 4 bits of the data to be
written to addresses 1080016 to 10FFF 16 must be set to “1” (by writing data FX16).
10XX016
10XXF 16
b7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
b0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
10XX016
+80016
10XXF 16
+80016
b7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b3
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Fig. 4.5.11 Example of display character data storing form
7220 Group User’s Manual
4-21
M37220M3-XXXSP/FP
4.5 Functional description
The character code used to specify a display character is determined based on the address in the
CRT display ROM in which that character data is stored.
Assume that 1 character data is stored in addresses 10XX0 16 to 10XXF16 (XX denotes 0016 to 7F16)
and 10YY0 16 to 10YYF 16 (YY denotes “XX+800 16”), then the character code is “XX 16 .”
In other words, a character code is constructed with the low-order second and third digits (hexadecimal
notation) of the 5-digit address (1000016 to 107FF 16) where that character data is stored.
A character code is “YY16 ” in addresses 1100016 to 11FFF 16.
Table 4.5.6 shows the character code table.
Table 4.5.6 Character code table (be omitted partly)
00 16
Character data stored address
Left side 8 dots
Right 4 side 8 dots
10000 16 to 1000F16
10800 16 to 1080F 16
01 16
10010 16 to 1001F16
10810 16 to 1081F 16
02 16
10020 16 to 1002F16
10820 16 to 1082F 16
03 16
10030 16 to 1003F16
10830 16 to 1083F 16
:
:
:
7E 16
7F16
107E0 16 to 107EF16
107F0 16 to 107EF 16
10FE0 16 to 10FEF 16
10FF016 to 10FFF 16
Character code
■ CRT display RAM (addresses 0600 16 to 06B316)
CRT display RAM is assigned to addresses 060016 to 06B316. Table 4.5.7 shows the contents of
CRT display RAM.
Table 4.5.7 Contents of CRT display RAM
Block number
Block 1
Display position (from left side)
1st character
Character code specifying
060016
Color specifying
2nd character
068116
3rd character
060116
060216
:
:
068216
:
18th character
061116
069116
19th character
20th character
061216
069216
061316
069316
061416
to
069416
061F16
:
069F16
1st character
062016
06A016
2nd character
3rd character
062116
06A116
062216
06A216
:
:
18th character
:
063116
19th character
063216
06116
06216
20th character
063316
06316
Not used
Block 2
4-22
068016
7220 Group User’s Manual
M37220M3-XXXSP/FP
4.5 Functional description
Figure 4.5.12 shows the structure of CRT display RAM.
Block 1
[Character specification]
7
0
1st character : 0600 16
to
20th character : 0613 16
Character code
Specify 128 characters (“00 16” to “7F16”)
[Color specification]
1st character : 0680 16
1
0
to
20th character : 0693 16
Color register specification
0 0 : Specifying color register 0
0 1 : Specifying color register 1
1 0 : Specifying color register 2
1 1 : Specifying color register 3
Block 2
[Character specification]
1st character : 0620 16
7
0
to
20th character : 0633 16
Character code
Specify 128 characters (“00 16” to “7F16”)
[Color specification]
1st character : 06A0 16
1
0
to
20th character : 06B3 16
Color register specification
0 0 : Specifying color register 0
0 1 : Specifying color register 1
1 0 : Specifying color register 2
1 1 : Specifying color register 3
Fig. 4.5.12 Structure of CRT display RAM
7220 Group User’s Manual
4-23
M37220M3-XXXSP/FP
4.5 Functional description
The different CRT display function–related registers from those of M37221M6-XXXSP/FP are shown in the
following pages.
Border Selection Register
b7 b6 b5 b4 b3 b2 b1 b0
Border selection register (MD) [Address 00E5 16]
B
Name
Functions
0
Block 1 OUT output
0 : Same output as character output
border selection bit (MD10) 1 : Border output
1
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
2
Block 1 OUT output
0 : Same output as character output
border selection bit (MD20) 1 : Border output
3
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
After reset
R W
Indeterminate R W
0
R —
Indeterminate R W
0
R —
Fig. 4.5.13 Border selection register (addresses 00E5 16)
Color Register n
b7 b6 b5 b4 b3 b2 b1 b0
Color register n (COn) (n = 0 to 3) [Addresses 00E6 16 to 00E916]
B
Name
Functions
0
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
0
R —
1
B signal output
selection bit (COn1)
0 : No character is output
1 : Character is output
0
R W
2
G signal output
selection bit (COn2)
0 : No character is output
1 : Character is output
0
R W
3
R signal output
selection bit (COn3)
0 : No character is output
1 : Character is output
0
R W
4
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
0
R —
5
OUT signal output
control bit (COn5)
0
R W
0
R —
0 : Character is output
1 : Blank is output
6, 7 Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
Fig. 4.5.14 Color register n (addresses 00E6 16 to 00E9 16)
4-24
After reset R W
7220 Group User’s Manual
M37220M3-XXXSP/FP
4.5 Functional description
CRT Control Register
b7 b6 b5 b4 b3 b2 b1 b0
CRT control register (CC) [Address 00EA 16]
B
Name
Functions
After reset R W
0
All-blocks display control
bit (Note) (CC0)
0 : All-blocks display off
1 : All-blocks display on
0
R W
1
Block 1 display control bit
(CC1)
0 : Block 1 display off
1 : Block 1 display on
0
R W
2
Block 2 display control bit
(CC2)
0 : Block 2 display off
1 : Block 2 display on
0
R W
3
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
0
R —
Note: Display is controlled by logical product (AND) between the all-blocks display
control bit and each block control bit.
Fig. 4.5.15 CRT control register (address 00EA 16)
CRT Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0
CRT port control register (CRTP) [Address 00EC 16]
B
Name
Functions
After reset R W
0
HSYNC input polarity
switch bit (HSYC)
0 : Positive polarity
1 : Negative polarity
0
R W
1
VSYNC input polarity
switch bit (VSYC)
0 : Positive polarity
1 : Negative polarity
0
R W
2
R, G, B output polarity
switch bit (R/G/B)
0 : Positive polarity
1 : Negative polarity
0
R W
3
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
0
R —
4
OUT output polarity
switch bit (OUT)
0 : Positive polarity
1 : Negative polarity
0
R W
5
R signal output switch bit
(OP5)
0 : R signal output
1 : MUTE signal output
0
R W
6
G signal output switch bit
(OP6)
0 : G signal output
1 : MUTE signal output
0
R W
7
B signal output switch bit
(OP7)
0 : B signal output
1 : MUTE signal output
0
R W
Fig. 4.5.16 CRT port control register (address 00EC 16)
7220 Group User’s Manual
4-25
M37220M3-XXXSP/FP
4.5 Functional description
4.5.7 Internal state immediately after reset
Figures 4.5.17 and 4.5.18 show the internal state immediately after reset.
■SFR Area (addresses C016 to DF16)
< State immediately after reset >
0 : “0” immediately after reset
1 : “1” immediately after reset
? : Undefined immediately
after reset
Address
Register
State immediately after reset
b7
C016 Port P0 (P0)
C116 Port P0 direction register (D0)
C216 Port P1 (P1)
C316
C416
C516
C616
C716
C816
C916
CA16
CB16
CC16
CD16
CE16
CF16
D016
D116
D216
D316
D416
D516
D616
D716
D816
D916
DA16
DB16
DC16
DD16
DE16
DF16
Port P1 direction register (D1)
Port P2 (P2)
Port P2 direction register (D2)
Port P3 (P3)
0
0
0
0
0
?
0
0
?
0
0
0
0
?
?
Port P3 direction register (D3)
Port P5 (P5)
Port P5 direction register (D5)
Port P3 output mode control register (P3S)
DA-H register (DA-H)
DA-L register (DA-L)
PWM0 register (PWM0)
PWM1 register (PWM1)
PWM2 register (PWM2)
PWM3 register (PWM3)
PWM4 register (PWM4)
PWM output control register 1 (PW)
PWM output control register 2 (PN)
Serial I/O mode register (SM)
Serial I/O regsiter (SIO)
DA1 conversion register (DA1)
DA2 conversion register (DA2)
Fig. 4.5.17 Internal state immediately after reset (1)
4-26
7220 Group User’s Manual
?
0016
?
0016
?
0016
? ?
0016
?
?
? ?
0016
?
0016
?
? ?
?
?
?
?
?
0016
0016
?
?
?
?
?
0016
?
? ?
? ?
b0
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
M37220M3-XXXSP/FP
4.5 Functional description
■SFR Area (addresses E016 to FF16)
< State immediately after reset >
0 : “0” immediately after reset
1 : “1” immediately after reset
? : Undefined immediately
after reset
Address
E016
E116
E216
E316
E416
E516
E616
E716
E816
E916
EA16
EB16
EC16
ED16
EE16
EF16
F016
F116
F216
F316
F416
F516
F616
F716
F816
F916
FA16
FB16
FC16
FD16
FE16
FF16
Register
State immediately after reset
b7
b0
Horizontal position register (HR)
Vertical position register 1 (CV1) 0
Vertical position register 2 (CV2) 0
?
?
?
?
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
Character size register (CS)
Border selection register (MD)
Color register 0 (CO0)
Color register 1 (CO1)
Color register 2 (CO2)
Color register 3 (CO3)
CRT control register (CC)
CRT port control register (CRTP)
CRT clock selection register (CK)
A-D control register 1 (AD1)
A-D control register 2 (AD2)
Timer 1 (TM1)
Timer 2 (TM2)
Timer 3 (TM3)
Timer 4 (TM4)
Timer 12 mode register (T12M)
Timer 34 mode register (T34M)
PWM5 register (PWM5)
Interrupt input polarity register (RE)
Test register (TEST)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
0016
? ?
? ?
?
0 ?
0 0
0016
0016
0016
0016
0016
?
0016
0016
? 0
0016
FF16
0716
FF16
0716
0016
0016
?
?
?
0 0
0016
1 1
0016
0016
0016
0016
?
?
?
?
?
?
?
?
?
0
?
?
0
0
0
0
0
?
1
0
0
Fig. 4.5.18 Internal state immediately after reset (2)
7220 Group User’s Manual
4-27
M37220M3-XXXSP/FP
4.6 Electrical characteristics
4.6 Electrical characteristics
Absolute maximum ratings
Symbol
Conditions
Ratings
–0.3 to 6
Unit
–0.3 to 6
VCC
Parameter
Power source voltage V CC
VI
Input voltage
CNVSS
VI
Input voltage
P00–P0 7,P10–P17, P20– Output transistors
P27, P30–P34, OSC1, XIN, are cut off.
H SYNC, VSYNC, RESET
–0.3 to V CC + 0.3
V
V
VO
Output voltage
P0 6, P0 7, P1 0–P1 7, P2 0–
P2 7, P30–P3 2, R, G, B,
OUT, D-A, X OUT, OSC2
–0.3 to V CC + 0.3
V
VO
Output voltage
P00–P05
–0.3 to 13
V
I OH
Circuit current
R, G, B, OUT, P10–P1 7,
P2 0–P2 7, P3 0, P3 1, D-A
0 to 1 (Note 1)
mA
I OL1
Circuit current
R, G, B, OUT1, P06, P07,
P10–P1 7, P20–P2 3, P30–
0 to 2 (Note 2)
mA
0 to 1 (Note 2)
0 to 10 (Note 3)
mA
mA
550
mW
–10 to 70
°C
–40 to 125
°C
All voltages are
based on V SS.
V
P3 2, D-A
I OL3
Circuit current
Circuit current
Pd
Power dissipation
T opr
Operating temperature
T stg
Storage temperature
I OL2
P00–P05
P24–P27
T a = 25 °C
Notes 1: The total current that flows out of the IC must be 20 mA (max.).
2: The total input current to IC (IOL1 + IOL2 ) must be 30 mA or less.
3: The total average input current for ports P2 4 –P2 7 to IC must be 20 mA or less.
4-28
7220 Group User’s Manual
M37220M3-XXXSP/FP
4.6 Electrical characteristics
Recommended operating conditions (Ta = –10 °C to 70 °C, VCC = 5 V ± 10 %, unless otherwise noted)
Parameter
Symbol
VCC
Power source voltage (Note 4), During CPU, CRT operation
VSS
Power source voltage
VIH
HIGH input voltage
P00–P0 7,P10–P17, P2 0–P2 7,
P3 0–P3 4, S IN, S CLK, HSYNC,
V SYNC, RESET, XIN, OSC1,
TIM2, TIM3, INT1, INT2, INT3
VIL1
LOW input voltage
P00–P0 7,P10–P17, P2 0–P2 7,
P3 0–P34
VIL2
LOW input voltage
H SYNC, V SYNC, RESET, TIM2,
Min.
Typ.
Max.
4.5
5.0
5.5
Unit
V
0
0.8VCC
0
0
VCC
V
V
V
0
0.4VCC
V
0
0.2VCC
V
TIM3, INT1, INT2, INT3, X IN,
OSC1, S IN, S CLK
I OH
HIGH average output current (Note 1)
R, G, B, OUT, D-A, P10–P17,
P20–P2 7, P3 0, P3 1
1
mA
I OL1
LOW average output current (Note 2)
R, G, B, OUT, D-A, P06, P07,
P1 0–P17, P20–P27, P30–P32
2
mA
I OL2
P0 0–P0 5
P2 4–P2 7
1
mA
I OL3
LOW average output current (Note 2)
LOW average output current (Note 3)
10
mA
f(X IN)
Oscillation frequency (for CPU operation) (Note 5) XIN
8.1
MHz
f CRT
f hs1
Oscillation frequency (for CRT display) (Note 5)
8.0
Input frequency
TIM2, TIM3
MHz
kHz
f hs2
Input frequency
SCLK
OSC1
7.9
5.0
8.0
100
1
MHz
Notes 1:
2:
3:
4:
The total current that flows out of the IC must be 20 mA (max.).
The total input current to IC (IOL1 + IOL2 ) must be 30 mA or less.
The total average input current for ports P2 4 –P2 7 to IC must be 20 mA or less.
Connect 0.1 µ F or more capacitor externally across the power source pins V CC –V SS so as to
reduce power source noise. Also connect 0.1 µ F or more capacitor externally across the pins
VCC–CNVSS.
5: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit.
7220 Group User’s Manual
4-29
M37220M3-XXXSP/FP
4.6 Electrical characteristics
Electric characteristics (V CC = 5 V ± 10 %, V SS = 0 V, f(XIN) = 8 MHz, T a = –10 °C to 70 °C, unless otherwise noted)
Symbol
I CC
VOH
VOL
Limits
Unit
Min. Typ. Max.
20
40
Power source current System operation V CC = 5.5 V,
mA
CRT OFF
f(X IN) = 8 MHz CRT ON
30
60
V CC = 5.5 V, f(X IN) = 0
300 µ A
Stop mode
HIGH output voltage
R, G, B, OUT, D-A, V CC = 4.5 V
V
2.4
P10–P17, P2 0–P2 7, I OH = –0.5 mA
P30, P31
0.4
LOW output voltage R, G, B, OUT, D-A, V CC = 4.5 V
V
P 0 0 – P 0 7 , P10 – P1 7 , I OL = 0.5 mA
Test conditions
Parameter
P20–P2 3, P3 0–P3 2
LOW output voltage
VT+–V T–
I IZH
I IZL
I OZH
P24–P2 7
Hysteresis RESET
V CC = 5.0 V
0.5
0.5
Hysteresis (Note)
H SYNC, V SYNC, TIM2,
TIM3, INT1, INT2,
INT3, S IN, S CLK
V CC = 5.0 V
HIGH input leak current
RESET, P00–P07,
P10–P17, P2 0–P2 7,
P3 0–P3 4, HSYNC,
VSYNC
V CC = 5.5 V
RESET, P00–P07,
P10–P17, P2 0–P2 7,
P3 0–P3 4, HSYNC,
VSYNC
P00–P0 5
V CC = 5.5 V
LOW input leak current
HIGH output leak current
3.0
V CC = 4.5 V
I OL = 10.0 mA
0.7
1.3
V
5
µA
5
µA
10
µA
V I = 5.5 V
VI = 0 V
V CC = 5.5 V
V O = 12 V
Note: P0 6, P0 7, P15, P2 3 and P2 4 have the hysteresis when these pins are used as interrupt input pins or
timer input pins. P2 0–P2 2 have the hysteresis when these pins are used as serial I/O pins.
4-30
7220 Group User’s Manual
M37220M3-XXXSP/FP
4.6 Electrical characteristics
A-D Comparator characteristics
(V CC = 5 V ± 10 %, V SS = 0 V, f(X IN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted)
Parameter
Symbol
—
—
Test conditions
Min.
Limits
Typ.
Max.
6
Resolution
Absolute accuracy
0
±1
±2
Unit
bits
LSB
Note: When V CC = 5 V, 1 LSB = 5/64 V.
D-A Converter characteristics
(V CC = 5 V ± 10 %, V SS = 0 V, f(X IN) = 8 MHz, T a = –10 °C to 70 °C, unless otherwise noted)
Parameter
Symbol
Test conditions
Min.
Limits
Typ.
Max.
—
Resolution
6
—
tsu
Absolute accuracy
2
Setting time
3
RO
Output resistor
1
7220 Group User’s Manual
2.5
4
Unit
bits
%
µs
kΩ
4-31
M37220M3-XXXSP/FP
4.7 Standard characteristics
4.7 Standard characteristics
The data described in this section are characteristic examples. Refer to “4.6 Electrical characteristics” for
rated values.
1. Ports P00–P05 and P32
(a) IOL–VOL characteristics
LOW level output current I OL [mA]
100.00
80.00
VCC=5.5V
60.00
40.00
VCC=4.5V
20.00
0.000
0.000
1.200
2.400
3.600
4.800
6.000
LOW level output voltage V OL [V]
2. Ports P06 and P07
(a) IOH–VOL characteristics
HIGH level output current I OH [mA]
100.00
80.00
60.00
VCC=5.5V
40.00
VCC=4.5V
20.00
0.000
0.000
1.200
2.400
3.600
LOW level output voltage V OL [V]
4-32
7220 Group User’s Manual
4.800
6.000
M37220M3-XXXSP/FP
4.7 Standard characteristics
3. Ports P10–P17, P20–P23, P30, P31 and D-A
(a) IOL–VOL characteristics
LOW level output current I OL [mA]
100.00
80.00
60.00
VCC=5.5V
40.00
VCC=4.5V
20.00
0.000
0.000
1.200
2.400
3.600
4.800
6.000
LOW level output voltage V OL [V]
(b) IOH–VOH characteristics
HIGH level output current I OH [mA]
– 100.00
– 80.00
– 60.00
VCC=5.5V
– 40.00
– 20.00
VCC=4.5V
0.000
0.000
– 1.200
– 2.400
– 3.600
– 4.800
– 6.000
HIGH level output voltage V OH [V]
7220 Group User’s Manual
4-33
M37220M3-XXXSP/FP
4.7 Standard characteristics
LOW level output current I OL [mA]
4. Ports P24–P27
(a) IOL–VOL characteristics
100.00
80.00
60.00
VCC=5.5V
40.00
VCC=4.5V
20.00
0.000
0.000
1.200
2.400
3.600
4.800
6.000
LOW level output voltage V OL [V]
(b) IOH–VOH characteristics
HIGH level output current I OH [mA]
–100.00
– 80.00
– 60.00
VCC=5.5V
– 40.00
– 20.00
0.000
0.000
VCC=4.5V
–1.200
– 2.400
– 3.600
HIGH level output voltage V OH [V]
4-34
7220 Group User’s Manual
– 4.800
– 6.000
M37220M3-XXXSP/FP
4.7 Standard characteristics
5. Ports P52–P55
(a) IOL–VOL characteristics
LOW level output current I OL [mA]
100.00
80.00
60.00
40.00
VCC=5.5V
20.00
VCC=4.5V
0.000
0.000
1.200
2.400
3.600
4.800
6.000
LOW level output voltage V OL [V]
(b) IOH–VOH characteristics
HIGH level output current I OH [mA]
–100.00
– 80.00
– 60.00
– 40.00
– 20.00
0.000
0.000
VCC=5.5V
VCC=4.5V
–1.200
– 2.400
– 3.600
– 4.800
– 6.000
HIGH level output voltage V OH [V]
7220 Group User’s Manual
4-35
CHAPTER 5
APPLICATION
5.1 Example of multi-line display
5.2 Notes on programming for OSD
(M37220M3-XXXSP/FP)
5.3 Usage example of ROM correction
function (M37221M8/MA-XXXSP)
5.4 Example of I2C-BUS interface control
(M37221Mx-XXXSP/FP)
5.5 Example of I2C-BUS interface control
by software (M37220M3-XXXSP/FP)
5.6 Application circuit example
APPLICATION
5.1 Example of multi-line display
5.1 Example of multi-line display
The M37221Mx-XXXSP/FP is used as a general example in describing this application for the 7220 group.
The M377221Mx-XXXSP/FP ordinarily displays 2 lines on a CRT screen by displaying 2 blocks at different
vertical positions. In addition to this, it can display 3 lines or more (multi-line display) by rewriting both
character data and display positions during interrupt processing, using CRT interrupts. An example of the
software processing for implemention this multi-line display is described below. This example is 12-line
multi-line display using blocks 1 and 2.
For CRT display details, refer to “2.11 CRT display function.”
5.1.1 Specifications
●Pins required: R, G, B, OUT1, H SYNC , and V SYNC
●H SYNC/V SYNC input polarity: positive polarity input
●R/G/B/OUT1 output polarity: positive polarity output
●Character colors: red, blue, white, and cyan
●No character background color
●Bordering (OUT) is available
●Character size: minimum size
●12-line display
5.1.2 Connection example
P52/R
P53/G
P54/B
P55/OUT1
HSYNC
VSYNC
Color TV signal processor
M37221Mx-XXXSP/FP
Monitor
Fig. 5.1.1 Connection example
Blue (B)
C A L E N D A R
Cyan
(R+G)
JAN
Sun.
Red (R)
3
10
17
24
31
Mon. Tues.
4
11
18
25
Wed. Thur.
5
12
19
26
6
13
20
27
7
14
21
28
Fri.
1
8
15
22
29
Sat.
2
9
16
23
30
←The 1st line
← The 2nd line
← The 3rd line
← The 4th line
Block 1
Block 2
Block 1
Block 2
← The 5th line
← The 6th line
← The 7th line
← The 8th line
← The 9th line
← The 10th line
← The 11th line
← The 12th line
Block 1
Block 2
Block 1
Block 2
Block 1
Block 2
Block 1
Block 2
White (R+G+B)
Fig. 5.1.2 Display example
5-2
7220 Group User’s Manual
APPLICATION
5.1 Example of multi-line display
5.1.3 General flowchart
The multi-line display processing routine consists of initialization processing routine, VSYNC interrupt processing
routine, and CRT interrupt processing routine.
(1) Initialization processing routine
This routine is used to initialize to cause a CRT interrupt.
CRTE : Bit 4 of interrupt control register 1
<CRT interrupt enable bit>
CRTR : Bit 4 of interrupt request register 1
<CRT interrupt request bit>
CS : Character size register
HR : Horizontal position register
Multi-line display start
Initialization
CRTE (bit4 at address 00FE 16) ←“0”
←“00000000 2”
CC (address 00EA 16)
P5D (address 00CB 16) ←“00000000 2”
CRTP (address 00EC 16) ←“00000000 2”
CO0 (address 00E6 16)
CO1 (address 00E7 16)
CO2 (address 00E8 16)
CO3 (address 00E9 16)
←“00001000 2” (red)
←“00000010 2” (blue)
←“00001110 2” (white)
←“00000110 2” (cyan)
Line counter :
CV1, CV2 :
P5D :
CRTP :
CC :
CO0 to CO3 :
F_VSYNC :
MD :
CK :
Counter RAM for line counting
Vertical position registers 1, 2
Port P5 direction register
CRT port control register
CRT control register
Color registers 0 to 3
VSYNC flag
Border selection register
CRT clock selection register
Disable only CRT interrupt
All blocks display off
Select R/G/B/OUT1
HSYNC/VSYNC input polarity : positive polarity input
R/G/B/OUT1 output polarity : positive polarity output
Color register 0 : red
Color register 1 : blue
Color register 2 : white
Color register 3 : cyan
Block 1 display RAM ←
Display character (blank) of block 1 (addresses 0600 16 to 0617 16)
Character color (no output) of block 1 (addresses 0680 16 to 0697 16)
CV1 (address 00E1 16)←
Vertical display start position of the 11th line (block 1)
Block 2 display RAM ←
Display character (blank) of block 2 (addresses 0620 16 to 0637 16)
Character color (no output) of block 2 (addresses 06A0 16 to 06B7 16)
CV2 (address 00E2 16)←
Vertical display start position of the 12th line (block 2)
CS (address 00E4 16)
MD (address 00E5 16)
HR (address 00E0 16)
CK (address 00ED 16)
Line counter
F_VSYNC
←“00000000 2”
←“00000101 2”
←“XXXXXXXX 2”
←“00000010 2”
Character size : minimum size
Border output
Set a horizontal display start position
Set display clock
←“0”
←“1”
Enable CRT interrupt in synchronized
with the next V SYNC
Note: This routine is not interrupt
processing routine.
END
Fig. 5.1.3 Flowchart of initialization processing routine
7220 Group User’s Manual
5-3
APPLICATION
5.1 Example of multi-line display
(2) VSYNC interrupt processing routine
The V SYNC interrupt processing routine consists of; multi-line display start processing and multi-line
display correction processing. The correction processing corrects erroneous multi-line display due to
various influences.
ICON1, ICON2: Interrupt control registers 1, 2
CRTE : Bit 4 of interrupt control register 1
<CRT interrupt enable bit>
CRTR : Bit 4 of interrupt request register 1
<CRT interrupt request bit>
CC :
Line counter :
F_VSYNC :
CV1,CV2 :
V_ICON1, V_ICON2 :
A:
X:
Y:
T:
D:
VSYNC interrupt processing routine
Setting for
multiple
interrupts
←“0”
T
←“0”
D
←ICON1
V_ICON1
←ICON2
V_ICON2
ICON1 (address 00FE 16) ←“00000001 2” ➀
ICON2 (address 00FF 16) ←“00000000 2” ➁
I
←“0”
Push registers X, Y, A
CRT control register
Counter RAM for line counting
VSYNC flag
Vertical position registers 1, 2
Back up RAM for interrupt control
registers 1, 2 during V SYNC interrupt
Accumulator
Index register X
Index register Y
X modified operation mode flag
Decimal operation mode flag
←Push ICON1 contents during V SYNC interrupt
←Push ICON2 contents during V SYNC interrupt
←Enable only Timer 1 interrupt
←Enable multipule interrupt set by steps ➀, ➁
(Refer to “5.1.7 (2)”)
=0
F_VSYNC
=1
Pass this
process only
once at
display start.
F_VSYNC
←“0”
CRTR (bit 4 at address 00FE 16) ←“0”
CRTE (bit 4 at address 00FC 16) ←“1”
CC (address 00EA 16)
←“0716”
←Enable CRT interrupt
←All blocks display on
Line counter←“2”
C
Correction for
erroneous
multi-line display
(Refer to “5.1.6”)
CV1←Vertical display start position of the 1st line (block 1)
CV2←Vertical display start position of the 2nd line (block 2)
CRTR (bit 4 at address 00FE 16)←“0”
Setting for
multiple
interrupts
Pop registers X, Y, A
←“1”
I
←V_ICON1
ICON1
←V_ICON2
ICON2
RETURN
←Disable all interrupts
←Pop ICON 1 and 2 contents during
VSYNC interrupt (Refer to “5.1.7 (2)”)
Note: The multiple interrupt priority of this system
interrupt is as below.
Timer 1 > VSYNC > CRT
Fig. 5.1.4 Flowchart of VSYNC interrupt processing routine
5-4
7220 Group User’s Manual
APPLICATION
5.1 Example of multi-line display
(3) CRT interrupt processing routine
The CRT interrupt processing routine executes the display character data setup routine for each line,
in order to perform multi-line display. The line to be displayed is determined by the line counter value.
ICON1, ICON2:
CS :
HR :
Line counter :
CV1,CV2 :
CRT_ICON1, CRT_ICON2 :
CRT interrupt processing routine
T
D
CRT_ICON1
CRT_ICON2
ICON1 (address 00FE 16)
ICON2 (address 00FF 16)
I
A:
X:
Y:
T:
D:
Interrupt control registers 1, 2
Character size register
Horizontal position register
Counter RAM for line counting
Vertical position registers 1, 2
Back up RAM for interrupt control
registers 1, 2 during CRT interrupt
Accumulator
Index register X
Index register Y
X modified operation mode flag
Decimal operation mode flag
←“0”
←“0”
←ICON1
←ICON2
←“00100001 2” ← Enable Timer 1 interrupt and
←“00000000 2”
VSYNC interrupt
←“0”
Push registers X, Y, A
← Specify jump destination by
Line counter value
Line counter = 0
=1
= 11
Block 1 display RAM ←
Display character of block 1 (the 1st line)
Character color of block 1 (the 1st line)
Block 2 display RAM ←
Display character of block 2 (the 2nd line)
Character color of block 2 (the 2nd line)
Block 2 display RAM ←
Display character of block 2 (the 12th line)
Character color of block 2 (the 12th line)
CV1 ← Vertical display start position
of the 1st line (block 1)
Set CS, HR
CV2 ← Vertical display start position
of the 2nd line (block 2)
Set CS, HR
CV2 ← Vertical display start position
of the 12th line (block 2)
Set CS, HR
Line counter +1
≠12
Line counter =12
=12
Line counter ← “0”
Save the value of Line counter
in internal RAM
Pop registers X, Y, A
I
←“1”
ICON1
←CRT_ICON1
ICON2
←CRT_ICON2
RETURN
←Disable all interrupts
←Pop ICON 1 and 2 contents during
CRT interrupt (Refer to “5.1.7 (2)”)
Note: The multiple interrupt priority of
this system is as below.
Timer 1 > VSYNC > CRT
Fig. 5.1.5 Flowchart of CRT interrupt processing routine
7220 Group User’s Manual
5-5
APPLICATION
5.1 Example of multi-line display
5.1.4 Set of display character data
To display the character data, set the character codes (“00 16 ” to “FF 16 ”) in the character addresses
(block 1: addresses 0600 16 to 0617 16, block 2: addresses 062016 to 0637 16). Also, set the color register
specifying (“00 2” to “112”) in the color addresses (block 1: addresses 068016 to 0697 16, block 2: addresses
06A016 to 06B7 16).
Character code
(“0016” to “FF 16”)
Character addresses
060016 060116
061616 061716
Block 1
Color addresses
068016 068116
Color register specifying
(“00 2” to “11 2”)
069616 069716
24 characters
Character code
(“001 16” to “FF 16”)
Character addresses
062016 062116
063616 063716
Block 2
Color addresses
06A016 06A116
Color register specifying
(“00 2” to “11 2”)
06B616 06B7 16
24 characters
Fig. 5.1.6 Set of display character data
5-6
7220 Group User’s Manual
APPLICATION
5.1 Example of multi-line display
5.1.5 Line counter
The line counter determines which line of display data is to be set. For example, if a CRT interrupt occurs
at the end of the first line display, the line counter value will be “2.” Therefore, the 3rd line display data
must be set from the end of the 1st line display to the start of the 3rd line display. Then, the line counter
value is incremented and becomes “3.”
Figure 5.1.7 shows the example of the setup timing for the line counter and the display character data.
Line counter value
2
End of the
1st line display
The 1st line (block 1)
3
The 2nd line (block 2)
4
The 3rd line (block 1)
CRT interrupt
Line counter value : 2
Set 3rd line display data
by the start of 3rd line
display
↓
Line counter value: 3
The 4th line (block 2)
A
...
Start of the
3rd line display
0
The 11th line (block 1)
1
The 12th line (block 2)
Fig. 5.1.7 Example of setup timing for line counter and display character data
7220 Group User’s Manual
5-7
APPLICATION
5.1 Example of multi-line display
5.1.6 Processing time
When setting display data by a CRT interrupt, the processing time is limited.
As shown in Figure 5.1.7, a CRT interrupt occurs at the end of the first line (block 1) display and setting
for the 3rd line display is started. This setting must be completed before a scanning line reaches to the
3rd line display position. If the setting is not completed, display characters flicker or rewriting is looked.
And also, for multi-line display of 12 lines, be sure that CRT interrupts occur 12 times from a VSYNC to the
next V SYNC. If CRT interrupts do not occur as many times as the number of display lines, the following
causes can be assumed.
• Display position overlaps.
• CRT interrupt processing time is too long, resulting in no display of that line (2 lines after the line being
displayed).
For example, a CRT interrupt occurs at the end of the second line display in Figure 5.1.7. Within this
interrupt processing, setting for the 4th line display is completed. However, if a scanning line is over the
display position of the 4th line (that is, A in Figure 5.1.7) during this setting, one CRT interrupt request is
deleted (or does not occur). Therefore, the line counter value is disordered and multi-line display is not
displayed correctly. In such cases, due to whatever causes, correct the value with processing C of VSYNC
interrupt processing (refer to “Figure 5.1.4”). When the CRT interrupt software processing overtime causes
this state, change the display positions or shorten the CRT interrupt software processing time.
5-8
7220 Group User’s Manual
APPLICATION
5.1 Example of multi-line display
5.1.7 Set of multiple interrupts
(1) When not setting multiple interrupts
When two or more interrupt requests occur at the same sampling point, the interrupt with the higher
priority (refer to “2.5 Interrupts, Table 2.5.1”) is received. This priority level is determined by
hardware but various priority processing by software can be executed using the interrupt enable bit
and each interrupt disable flag (I).
Assume, for example, that all interrupts (CRT, V SYNC, Timer 1) are enabled. When the multiple
interrupt is not set, these interrupt request bits are set to “1” and the interrupts are determined by
hardware as follows:
➀CRT interrupt
➁VSYNC interrupt
➂Timer 1 interrupt
Figure 5.1.8 shows the timing of interrupt processing when not setting multiple interrupts.
The I flag is set to “1” (all interrupts are disabled) automatically by hardware as soon as the interrupt
processing starts. Unless the I flag is cleared to “0,” other interrupt will not occur during the interrupt
processing.
CRT interrupt request bit
1
0
1
VSYNC interrupt request bit
Timer 1 interrupt request bit
0
1
0
CRT interrupt processing
VSYNC interrupt processing
1
2
3
Timer 1 interrupt processing
3’
Interrupt disable flag (I)
Fig. 5.1.8 Timing of interrupt processing when not setting multiple interrupts
7220 Group User’s Manual
5-9
APPLICATION
5.1 Example of multi-line display
(2) When setting multiple interrupts
Various priority processings are executed by enabling multiple interrupts and by setting priorities by
software. For example, to set the priority listed below;
➀Timer 1 interrupt
➁VSYNC interrupt
➂CRT interrupt
execute the following process:
Set only interrupt enable bits (ICON1, ICON2) whose priorities are higher than the current interrupt,
and enable the interrupt disable flag (I) in only the current interrupt processing routine.
Figure 5.1.9 shows the timing when all interrupt request bits (CRT, VSYNC, Timer 1) are “1” at the
same sampling point.
Note: When setting multiple interrupts, be sure to determine priority levels to prevent occurrence of
plural interrupts with the same priority level.
1
CRT interrupt request bit
VSYNC interrupt request bit
Timer 1 interrupt request bit
0
1
0
1
0
CRT interrupt processing
3
(series of 3 )
(series of 3 )
A
B
VSYNC interrupt processing
(series of 2 )
2
A’
Timer 1 interrupt processing
B’
1
1’
Interrupt disable flag (I)
Fig. 5.1.9 Timing when all interrupt request bits are “1” at the same sampling point
5-10
7220 Group User’s Manual
APPLICATION
5.1 Example of multi-line display
(3) CRT interrupt processing routine when setting multiple interrupts
Figure 5.1.10 shows the flowchart of CRT interrupt processing routine when setting multiple interrupts.
A and B are the setting routines for multiple interrupts.
T
D
A
Set routine for
multiple
interrupts
ICON1, ICON2: Interrupt control registers 1, 2
CRT_ICON1, CRT_ICON2 : Back up RAM for interrupt control
registers 1, 2 during CRT interrupt
A : Accumulator
CRT interrupt processing routine
X : Index register X
Y : Index register Y
T : X modified operation mode flag
←“0”
D : Decimal operation mode flag
←“0”
←ICON1
CRT_ICON1
CRT_ICON2
←ICON2
ICON1 (address 00FE 16) ←“00100001 2”
ICON2 (address 00FF 16) ←“00000000 2”
I
←“0”
Push registers X, Y, A
Enable state of
multiple interrupts
(VSYNC, Timer 1)
←Enable V SYNC and Timer 1 interrupts to
take priority than CRT interrupt.
And also, be sure to disable the following interrupts:
-CRT interrupt
-all interrupts with lower priority than CRT
interrupt.
CRT interrupt processing
Pop the registers X, Y, A
B
Disable
multiple interrupts
I
ICON1
ICON2
←“1”
←CRT_ICON1
←CRT_ICON2
←Disable all interrupts
←Pop ICON 1 and 2 contents
during CRT interrupt
RETURN
Fig. 5.1.10 Flowchart of CRT interrupt processing routine (when setting multiple interrupts)
7220 Group User’s Manual
5-11
APPLICATION
5.1 Example of multi-line display
(4) VSYNC interrupt processing routine when setting multiple interrupts
Figure 5.1.11 shows the flowchart of VSYNC interrupt processing routine when setting multiple interrupts.
A’ and B’ are the setting routines for multiple interrupts.
T
D
A’
Set routine for
multiple
interrupts
ICON1, ICON2: Interrupt control registers 1, 2
V_ICON1, V_ICON2 : Back up RAM for interrupt control
registers 1, 2 during V SYNC interrupt
A : Accumulator
VSYNC interrupt processing routine
X : Index register X
Y : Index register Y
T : X modified operation mode flag
←“0”
D : Decimal operation mode flag
←“0”
←ICON1
V_ICON1
V_ICON2
←ICON2
ICON1 (address 00FE 16)←“00000001 2”
ICON2 (address 00FF 16)←“00000000 2”
I
←“0”
Push registers X, Y, A
←Enable Timer 1 interrupt to
take priority than V SYNC interrupt.
And also, be sure to disable the following interrupts:
-VSYNC interrupt
-all interrupts with lower priority than V SYNC
interrupt.
VSYNC interrupt processing
Enable state of
multiple interrupts
(Timer 1)
Pop the registers X, Y, A
B’
Disable
multiple interrupts
I
ICON1
ICON2
←“1”
←V_ICON1
←V_ICON2
←Disable all interrupts
←Pop ICON 1 and 2 contents
during V SYNC interrupt
RETURN
Fig. 5.1.11 Flowchart of VSYNC interrupt processing routine (when setting multiple interrupts)
5-12
7220 Group User’s Manual
APPLICATION
5.2 Notes on programming for OSD (M37220M3-XXXSP/FP)
5.2 Notes on programming for OSD (M37220M3-XXXSP/FP)
The emulator MCU M37221ERSS is used for programming development with the M37220M3-XXXSP/FP.
However, the functions of the M37221ERSS are compatible with those of the M37221Mx-XXXSP/FP, and
therefore has some functions which the M37220M3-XXXSP/FP does not have. Note the following differences
when programming using the M37220M3-XXXSP/FP.
5.2.1 Setting of color registers
The color registers of M37220M3-XXXSP/FP are different from those of M37221ERSS (refer to “Figures
5.2.1 and 5.2.2”). Character background colors can be output when programming with the M37221ERSS,
but not with the M37220M3-XXXSP/FP mask version. This character background color program does not
operate on the M37220M3-XXXSP/FP and therefore, it cannot output character background colors (except
character background colors by OUT signal; bit 5).
Color Register n
b7 b6 b5 b4 b3 b2 b1 b0
Color register n (CO0 to CO3) (n = 0 to 3) [Addresses 00E6 16 to 00E9 16]
B
Name
Functions
After reset R W
0
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
0
R —
1
B signal output
selection bit (COn1)
0 : No character is output
1 : Character is output
0
R W
2
G signal output
selection bit (COn2)
0 : No character is output
1 : Character is output
0
R W
3
R signal output
selection bit (COn3)
0 : No character is output
1 : Character is output
0
R W
4
B signal output (background) 0 : No background color is output
1 : Background color is output (See note 1)
selection bit (COn4)
0
R W
5
OUT1 signal output
control bit (COn5)
0
R W
0 : Character is output
1 : Blank is output
(See notes 1, 2)
6
G signal output (background) 0 : No background color is output
selection bit (COn6)
1 : Background color is output
0
R W
7
R signal output (background) 0 : No background color is output
1 : Background color is output (See note 2)
selection bit (COn7)
0
R W
Notes 1: When bit 5 = “0” and bit 4 = “1,” there is output same as a character or border output
from the OUT1 pin.
Do not set bit 5 = “0” and bit 4 = “0.”
2: When only bit 7 = “1” and bit 5 = “0,” there is output from the OUT2 pin.
Fig. 5.2.1 Color register n (M37221ERSS)
7220 Group User’s Manual
5-13
APPLICATION
5.2 Notes on programming for OSD (M37220M3-XXXSP/FP)
Color Register n
b7 b6 b5 b4 b3 b2 b1 b0
Color register n (COn) (n = 0 to 3) [Addresses 00E6 16 to 00E916]
B
Name
Functions
After reset R W
0
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
0
R —
1
B signal output
selection bit (COn1)
0 : No character is output
1 : Character is output
0
R W
2
G signal output
selection bit (COn2)
0 : No character is output
1 : Character is output
0
R W
3
R signal output
selection bit (COn3)
0 : No character is output
1 : Character is output
0
R W
4
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
0
R —
5
OUT signal output
control bit (COn5)
0
R W
0
R —
0 : Character is output
1 : Blank is output
6, 7 Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
Fig. 5.2.2 Color register n (M37220M3-XXXSP/FP)
5.2.2 Setting border selection register
The M37220M3-XXXSP/FP can output neither character background (OUT) nor border at the same time.
When setting the border selection bits (bit 0 or 2) to “1,” the border output takes over OUT (setting of
bit 5 of the color registers). Therefore, select either the character background output or the border output.
Border Selection Register
b7 b6 b5 b4 b3 b2 b1 b0
Border selection register (MD) [Address 00E5 16]
B
Name
Functions
0
Block 1 OUT output
0 : Same output as character output
border selection bit (MD10) 1 : Border output
1
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
2
Block 2 OUT output
0 : Same output as character output
border selection bit (MD20) 1 : Border output
3
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
After reset
R W
Indeterminate R W
0
R —
Indeterminate R W
0
R —
Fig. 5.2.3 Border selection register (M37220M3-XXXSP/FP)
5.2.3 Number of display characters
The M37221ERSS can display up to 24 characters in each block. However, the M37220M3-XXXSP/FP can
display only up to 20 characters in each block. Note this when programming using the M37220M3-XXXSP/
FP.
5-14
7220 Group User’s Manual
APPLICATION
5.3 Usage example of ROM correction function (M37221M8/MA-XXXSP)
5.3 Usage example of ROM correction function (M37221M8/MA-XXXSP)
Application example using the ROM correction function is described below. In this example, it is assumed
that the program must be changed by specifications modification after completion of ROM mask. Also,
E2PROM is connected to this system.
5.3.1 Connection example
M37221M8-XXXSP
M37221MA-XXXSP
M6M80012P
I2C-BUS
<Microcomputer>
<E2PROM>
Fig. 5.3.1 Connection example
5.3.2 Correction example
The following is an example when 2 addresses (2 blocks) of ROM are corrected.
(1) Correction example 1
Address
E120
E122
E123
E126
Program before correction
Machine
Description style
instructions
LDA #00H
A900
3A
INC A
STA 0111H
8D1101
60
RTS
Address
(block 1)
02C0
02C2
02C3
02C6
02C7
02CA
Correction program
Machine
Description style
instructions
A980
LDA #80H
1A
DEC A
8D1201
STA 0112H
1A
DEC A
8D1301
DEC 0113H
JMP E126H ➀ (See note)
4C26E1
Note: In ➀, E126H is specified as the return destination address of JMP.
In this example, since the instruction at the return destination address is RTS,
even if RTS is used instead of JMP, the operation is the same as that of JMP.
As a result, the number of bytes is reduced.
Fig. 5.3.2 Correction example (1)
7220 Group User’s Manual
5-15
APPLICATION
5.3 Usage example of ROM correction function (M37221M8/MA-XXXSP)
(2) Correction example 2
The loop processing is performed between ➁ and ➂ in Figure 5.3.3. Two examples of this part are
shown in detail. Example A corrects in loop units and example B corrects only error instructions.
Examples A and B are the same operation, differing in processing time and correction bytes only.
Depending on the contents of loop processing, it may be preferable to include correct codes with the
codes to be corrected, simplifying the correction program and making it easier to read.
When omitting FE96H (➃) and correcting from FE98H, the program cannot move to FE96H by the
BPL instruction (the jump destination addresses of the BPL instruction are limited to bytes between
–128 and +127). Therefore, the example B is provided.
Example A
Program before correction
Address
Description style
Machine
instructions
025H, X ➁
FE96
9525
STA
FE98
CA
DEX
FE99
10FB
BPL 0FE96H ➂
(See note 2)
FE9B
60
RTS
Address
(block 2)
02E0
02E2
02E5
02E6
02E7
02E9
Correction program
Description style
Machine
instructions
9525
STA 025H, X ➃
9D2501
STA 0125H, X
3A
INC A
CA
DEX
10F7
BPL 02E0H ➄
(See note 2)
RTS (See note 1)
60
Example B
Address
(block 2)
02E0
02E3
02E4
02E5
02E7
02EA
Correction program
Description style
Machine
instructions
9D2501
STA 0125H, X
3A
INC A
CA
DEX
3003
BMI 02EAH
(See note 2)
JMP FE96H
4C96FE
JMP FE9BH ➀
4C9BFE
(See note 1)
Notes 1: In ➀, FE9BH is specified as the return destination address of JMP.
In this example, since the instruction at the return destination address is RTS,
even if RTS is used instead of JMP , the operation is the same as that of JMP .
As a result, the number of bytes is reduced.
2: BPL and BMI, as machine instructions, have no absolute addresses, but relative
addresses as branch destinations.
Fig. 5.3.3 Correction example (2)
5-16
7220 Group User’s Manual
APPLICATION
5.3 Usage example of ROM correction function (M37221M8/MA-XXXSP)
5.3.3 E2PROM map
Figures 5.3.4 and 5.3.5 show the E 2PROM map when using the ROM correction function. To store correction
codes by using both ROM correction functions 1 and 2, the capacity of E 2PROM needs to be approximately
70 bytes.
E2PROM
address
Contents
Stored data
(Machine instruction)
Valid/invalid
ROM correction function 1
(55H: valid, others: invalid)
ROM correction function 1
Execution address (high-order)
ROM correction function 1
Execution address (low-order)
55H
003 16
ROM correction function 1
Correction code 1
A9H
004 16
ROM correction function 1
Correction code 2
80H
005 16
ROM correction function 1
Correction code 3
006 16
ROM correction function 1
007 16
008 16
000 16
001 16
002 16
Instructions in
correction program
E1H
20H
LDA
#80H
1AH
DEC
A
Correction code 4
8DH
STA
0112H
ROM correction function 1
Correction code 5
12H
ROM correction function 1
Correction code 6
01H
009 16
ROM correction function 1
Correction code 7
1AH
DEC
A
00A16
ROM correction function 1
Correction code 8
8DH
STA
0113H
00B16
ROM correction function 1
Correction code 9
13H
00C16
ROM correction function 1
Correction code 10
01H
00D16
ROM correction function 1
Correction code 11
4CH
JMP
E126H
00E16
ROM correction function 1
Correction code 12
26H
00F 16
ROM correction function 1
Correction code 13
E1H
010 16
ROM correction function 1
Correction code 14
EAH
NOP (see note)
011 16
ROM correction function 1
Correction code 15
EAH
NOP
012 16
ROM correction function 1
Correction code 16
EAH
NOP
013 16
ROM correction function 1
Correction code 17
EAH
NOP
014 16
ROM correction function 1
Correction code 18
EAH
NOP
015 16
ROM correction function 1
Correction code 19
EAH
NOP
016 16
ROM correction function 1
Correction code 20
EAH
NOP
017 16
ROM correction function 1
Correction code 21
EAH
NOP
018 16
ROM correction function 1
Correction code 22
EAH
NOP
019 16
ROM correction function 1
Correction code 23
EAH
NOP
01A16
ROM correction function 1
Correction code 24
EAH
NOP
01B16
ROM correction function 1
Correction code 25
EAH
NOP
01C16
ROM correction function 1
Correction code 26
EAH
NOP
01D16
ROM correction function 1
Correction code 27
EAH
NOP
01E16
ROM correction function 1
Correction code 28
EAH
NOP
01F 16
ROM correction function 1
Correction code 29
EAH
NOP
020 16
ROM correction function 1
Correction code 30
4CH
021 16
ROM correction function 1
Correction code 31
XXH
022 16
ROM correction function 1
Correction code 32
YYH
JMP YYXXH
Set reset vector
address to YYXXH
(see note).
Refer to
“Figure 5.3.2”
Note: When operating normally, this instruction is not executed. This is a redundant processing to
reset during program runaway.
Fig. 5.3.4 E2PROM map when using ROM correction function (1)
7220 Group User’s Manual
5-17
APPLICATION
5.3 Usage example of ROM correction function (M37221M8/MA-XXXSP)
E2PROM
address
Contents
Stored data
(Machine instruction)
Valid/invalid
ROM correction function 2
(55H: valid, others: invalid)
ROM correction function 2
Execution address (high-order)
ROM correction function 2
Execution address (low-order)
55H
026 16
ROM correction function 2
Correction code 1
95H
027 16
ROM correction function 2
Correction code 2
25H
028 16
ROM correction function 2
Correction code 3
9DH
029 16
ROM correction function 2
Correction code 4
25H
02A16
ROM correction function 2
Correction code 5
01H
02B16
ROM correction function 2
Correction code 6
02C16
ROM correction function 2
02D16
ROM correction function 2
02E16
023 16
024 16
025 16
Instructions in
correction program
FEH
96H
LDA
025H, X
LDA
0125H, X
3AH
INC
A
Correction code 7
CAH
DEX
Correction code 8
10H
BPL
ROM correction function 2
Correction code 9
F7H
02F 16
ROM correction function 2
Correction code 10
60H
RTS
030 16
ROM correction function 2
Correction code 11
EAH
NOP (see note)
031 16
ROM correction function 2
Correction code 12
EAH
NOP
032 16
ROM correction function 2
Correction code 13
EAH
NOP
033 16
ROM correction function 2
Correction code 14
EAH
NOP
034 16
ROM correction function 2
Correction code 15
EAH
NOP
035 16
ROM correction function 2
Correction code 16
EAH
NOP
036 16
ROM correction function 2
Correction code 17
EAH
NOP
037 16
ROM correction function 2
Correction code 18
EAH
NOP
038 16
ROM correction function 2
Correction code 19
EAH
NOP
039 16
ROM correction function 2
Correction code 20
EAH
NOP
03A16
ROM correction function 2
Correction code 21
EAH
NOP
03B16
ROM correction function 2
Correction code 22
EAH
NOP
03C16
ROM correction function 2
Correction code 23
EAH
NOP
03D16
ROM correction function 2
Correction code 24
EAH
NOP
03E16
ROM correction function 2
Correction code 25
EAH
NOP
03F 16
ROM correction function 2
Correction code 26
EAH
NOP
040 16
ROM correction function 2
Correction code 27
EAH
NOP
041 16
ROM correction function 2
Correction code 28
EAH
NOP
042 16
ROM correction function 2
Correction code 29
EAH
NOP
043 16
ROM correction function 2
Correction code 30
4CH
044 16
ROM correction function 2
Correction code 31
XXH
045 16
ROM correction function 2
Correction code 32
YYH
JMP YYXXH
Set reset vector
address to YYXXH
(see note).
02E0H
Note: When operating normally, this instruction is not executed. This is a redundant processing to
reset during program runaway.
Fig. 5.3.5 E2PROM map when using ROM correction function (2)
5-18
7220 Group User’s Manual
Refer to
“Figure 5.3.3
example A”
APPLICATION
5.3 Usage example of ROM correction function (M37221M8/MA-XXXSP)
5.3.4 General flowchart
Figure 5.3.6 shows the general flowchart when using ROM correction function. E2PROM addresses in the
flowchart corresponds to E2PROM map (refer to “Figures 5.3.4 and 5.3.5”).
START
After reset release, read the data
from E 2PROM
• ROM correction function 1 (address 000 16)
Valid/invalid
• ROM correction function 2 (address 023 16)
Valid/invalid
Yes
←5516: valid, others: invalid
No
Use ROM correction function 1 ?
• ROM correction address 1 (high-order)
address 021716← 00116 of E2PROM
• ROM correction address 1 (low-order)
address 021816← 00216 of E2PROM
address 02C0 16 to 02DF 16
← 00316 to 022 16 of E 2PROM
ROM correction enable register
(b0 at address 021B 16)← “0” (disabled)
Disable block 1 enable bit.
Store execution address
into ROM correction address 1.
Store correction codes of ROM
correction function 1 into ROM
correction memory 1 (block 1).
ROM correction enable register
(b0 at address 021B 16)← “1” (enabled) Enable block 1 enable bit.
Yes
No
Use ROM correction function 2 ?
• ROM correction address 2 (high-order)
address 0219 16← 02416 of E2PROM
• ROM correction address 1 (low-order)
address 021A16← 02516 of E 2PROM
address 02E0 16 to 02FF 16
← 02616 to 045 16 of E 2PROM
ROM correction enable register
(b1 at address 021B 16)← “0” (disabled)
Store execution address
into ROM correction address 2.
Disable block 2 enable bit.
Store correction codes of ROM
correction function 2 into ROM
correction memory 2 (block 2).
ROM correction enable register
(b1 at address 021B 16)← “1” (enabled) Enable block 2 enable bit.
END
Fig. 5.3.6 General flowchart when using ROM correction function
7220 Group User’s Manual
5-19
APPLICATION
5.3 Usage example of ROM correction function (M37221M8/MA-XXXSP)
5.3.5 Notes on use
When using the ROM correction function, note the following.
●Specify the first address (op code address) of each instruction as the ROM correction address.
●Use the RTS, RTI or JMP instruction (total of 3 bytes) to return from the correction program to the main
program.
●Do not set the same address to ROM correction addresses 1 and 2 (addresses 021716 to 021A16 ).
5-20
7220 Group User’s Manual
APPLICATION
5.4 Example of I2C-BUS interface control (M37221Mx-XXXSP/FP)
5.4 Example of I2C-BUS interface control (M37221Mx-XXXSP/FP)
The M37221Mx-XXXSP/FP has multi-master I2C-BUS interface. This interface, offering both arbitration lost
detection and synchronous functions, is useful for the multi-master serial communications.
This paragraph explains transmit/receive control example of E 2PROM (M6M80012P) adaptable to the I2CBUS interface.
For details on the I 2C-BUS interface, refer to “2.8 Multi-master I2C-BUS interface.”
5.4.1 Specifications
● E2PROM required: M6M80012P
● Synchronous clock: internal clock
● Standard clock mode: 100 kHz
● Number of transfer bits: 8 bits
● Data format: addressing format
● Pins required: SCL1, SDA1
● Direction of data transfer: MSB first
5.4.2 Connection example
P11/SCL1
P13/SDA1
SCL
SDA
SCL
SDA
SCL : Serial clock
SDA : Serial data
M37221Mx-XXXSP
<Master>
M6M80012P
<Slave>
Fig. 5.4.1 Connection example
7220 Group User’s Manual
5-21
APPLICATION
5.4 Example of I2C-BUS interface control (M37221Mx-XXXSP/FP)
5.4.3 E2PROM functions
(1) Byte write
Bytes are written by sending the START condition, slave address “A016,” sub-address (1 byte), data
(1 byte), and the STOP condition from the master. Writing to the E2PROM will be started after the
master sends the STOP condition, that is, in synchronization with a rising edge of the SDA signal.
This writing will be automatically terminated by the on-chip sequential controller. In this period, no
acknowledge bits are generated.
Figure 5.4.2 shows the byte write timing.
S
Bus operation of T
A
master side: R
T
Slave
address (W)
Sub-address (n)
S
T
O
P
Data (n)
W
SDA signal S
P
A
C
K
Bus operation of
slave side:
S
P
ACK
W
A
C
K
A
C
K
: START condition
: STOP condition
: Acknowledge bit
: Write bit (0)
Fig. 5.4.2 Byte write timing
(2) Random address read
In this mode, the data of an arbitrary address is read. To set the first-read address, the master sends
the START condition, slave address “A016,” and sub-address (1 byte). Upon receiving the acknowledge
bit (ACK) from the E 2PROM, the master sends the RESTART condition signal and slave address
“A116” again. After ACK is generated from the E 2PROM, the data of the corresponding sub-address
is read out.
After the data is output, no acknowledge bits are generated, but the STOP condition is sent by the
master, completing this read operation.
S
T
Bus operation of A
master side: R
T
Slave
address (W)
SDA signal S
Sub-address (n)
R
S
W
A
C
K
Bus operation of
slave side:
S
P
ACK
W
S
T
A Slave address (R)
R
T
A
C
K
: START condition
R : Read bit (1)
: STOP condition
RS : RESTART condition
: Acknowledge bit NACK : No acknowledge bit
: Write bit (0)
Fig. 5.4.3 Random address read timing
5-22
7220 Group User’s Manual
N
AS
CT
KO
P
R
P
A
C
K
Data (n)
APPLICATION
5.4 Example of I2C-BUS interface control (M37221Mx-XXXSP/FP)
5.4.4 General flowchart
The processing routines which controls I 2C-BUS devices branch to the write processing routine and the
read processing routine. The data output processing routine is used as the common processing routine.
(1) Write processing routine
➀
S
➁
➂
Slave address
(W) “A016”
A
C
K
Sub-address
A
C
K
➃
➄
Data
A
C P
K
A:
S1:
S2:
S1D:
IICE:
Accumulator
I2C status register
I2C clock control register
I2C control register
Multi-master I 2C interface interrupt
enable bit
BB: Bit 5 of I 2C status register
Write start
Initialization
S2 (address 00DB 16)
S1D (address 00DA 16)
IICE (bit6 at address 00FE 16)
S1 (address 00D9 16)
A
“11000101 2”
“01001000 2”
“0”
“00010000 2”
Setting for outputting the START condition
in data output processing routine.
Slave address (W) “A0 16”
➀➁ Transmit the START condition and slave address (W).
➂➃ Transmit sub-address and data.
Data output
Within 10
machine
cycles
Disable multi-master I 2C-BUS interface interrupt.
I
S1 (address 00F8 16)
S1 (address 00F8 16)
I
Note 1: Refer to “(3) Data output processing
routine.”
“1”
“11000000 2”
“11010000 2”
“0”
➄
Transmit the STOP condition.
Note 2: Be sure to set between S1 and S1 within
10 machine cycles.
End
Fig. 5.4.4 Flowchart of write processing routine
7220 Group User’s Manual
5-23
APPLICATION
5.4 Example of I2C-BUS interface control (M37221Mx-XXXSP/FP)
(2) Read processing routine
➀
S
➁
➂
Slave address
(W) “A0 16”
A
C
K
➃
Sub-address
A
R
C
K S
➄
Slave address
(R) “A1 16”
A
C
K
➅
➆
Data
A
C P
K
A:
S0:
S1:
S2:
S1D:
IICE:
BB:
TRX:
Read start
Initialization
S2 (address 00DB 16)
S1D (address 00DA 16)
ACK BIT:
PIN:
←“11000101 2”
←“01001000 2”
IICE (bit6 at address 00FE 16) ←“0”
←“00010000 2”
S1 (address 00D9 16)
Disable multi-master I 2C-BUS interface. RS:
Setting for outputting the START condition
in data output processing routine.
Accumulator
I2C data shift register
I2C status register
I2C clock control register
I2C control register
Multi-master I 2C interface
interrupt enable bit
Bus busy flag
Communication mode
specification bit
ACK bit
I2C-BUS interface interrupt
request bit
Restart condition
(A)←Slave address (W) “A0 16”
➀➁➂
Data output
Transmit the START condition, slave
address (W) , and sub-address.
S1 (address 00D9 16) ←“00100000 2”
(A)←Slave address (R) “A1 16”
➃➄
Data output
←“0”
TRX (bit 6 at address 00D9 16)
ACK BIT (bit 6 at address 00DB 16) ←“0”
Transmit the RESTART condtion and
slave address (R).
Set to receive mode
Set ACK return mode.
No
Immediately before
the last receive byte?
Yes
Set to non-ACK return mode.
ACK BIT (bit 6 at address 00DB 16)←“1”
No
End of reception of
the last receive byte
S0 (address 00D7 16 )←“FF 16”
➅Input start
(Set dummy data to
generate clock.)
Preparation for judging of timeout.
Yes
Yes
After data is received, no
acknowledge bits are
generated, but the STOP
condition is sent by the
master, completing this
read operation.
Timeout ? (See note 2)
No
Waiting receive end
PIN (bit 4 at address 00D9 16)≠“1”?
No (not end)
Yes (end)
Store recive data to internal RAM
Within 10
←“1”
machine
I
cycles
S1 (address 00F8 16) ←“11000000 2”
S1 (address 00F8 16) ←“11010000 2”
I
←“0”
➆Transmit the STOP condition.
Note 1: Be sure to set between S1
and S1 within 10 machine cycles.
End
Note 2: The timeout count is performed by software with interrupts, such as timers. Accordingly, if receive
operation is not completed due to various influences, the loop continues. Therefore, if receive
operation does not complete within a certain time, I 2 C-BUS access is stopped by outputting STOP
condition. If I 2C-BUS access is stopped by timeout, the obtained data is incorrect data.
Fig. 5.4.5 Flowchart of read processing routine
5-24
7220 Group User’s Manual
APPLICATION
5.4 Example of I2C-BUS interface control (M37221Mx-XXXSP/FP)
(3) Data output processing routine
The data output processing routine is the common routine within the transmit/receive processing
routine.
A:
S0:
S1:
TRX:
AL:
PIN:
Accumulator
I2C data shift register
I2C status register
Communication mode specification bit
Arbitration lost detecting flag
Multi-master I 2C interface interrupt
enable bit
LRB: Last receive bit
Data output
Store the number of output bytes to internal RAM
S0 (address 00D7 16)←Data to be output
N
The first byte ?
Yes
Output A.
S1 (address 00D9 16)←11110000 2
An error occurs when data
transmit does not end within a
certain period.
Preparation for judging timeout.
An error
such as timeout occurs ?
TRX (bit 6 at address 00D9 16)≠“0” or
AL (bit 3 at address 00D9 16)≠“1” ?
TRX = 0 :
AL = 1 :
arbitration lost is
detected (error)
Error
No error
= 1 (Not yet)
1-byte data transmit completes?
PIN (bit 4 at address 00D9 16) ≠ “1” ?
= 0 (Completion of 1-byte data transmit)
Stop judging of timeout.
LRB (bit 0 at address 00D9 16) ≠ “1” ?
= 1 (No ACK)
No ACK?
= 0 (ACK)
Store the next data to A
No
The last byte ?
Yes
END
END
Fig. 5.4.6 Flowchart of data output processing routine
7220 Group User’s Manual
5-25
APPLICATION
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP)
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP)
Althogh, the M37220M3-XXXSP/FP has no multi-master I 2C-BUS interface, it can control single-master I 2CBUS by software. Most TV systems can be controlled in this way.
This paragraph explains transmit/receive control example of a single-chip color TV signal processor (M52340SP)
adaptable to the I2C-BUS interface.
5.5.1 Specifications
● Single-chip color TV signal processor required: M52340SP
● Number of transfer bits: 8 bits
● Data format: addressing format
● Pins required: P2 1, P2 0
● Direction of data transfer: MSB first
5.5.2 Connection example
SCL
P20/SCLK
SDA
P21/S OUT
SCL
SDA
SCL : Serial clock
SDA : Serial data
M37220M3-XXXSP/FP
<Master>
Fig. 5.5.1 Connection example
5-26
7220 Group User’s Manual
M52340SP
<Slave>
APPLICATION
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP)
5.5.3 Single-chip color TV signal processor function
(1) Status read
Status is read by sending the START condition, slave address “BB16.” After ACK is generated from
the M52340SP, the status data is read out. After the status data is output, any acknowledge bit is
not generated, but the STOP condition is sent by the master. Then this read operation is completed.
N
AS
CT
KO
P
S
T
Bus operation of A
Slave address (R)
master side: R
T
SDA signal S
P
R
A
C
K
Bus operation of
slave side:
S
P
ACK
R
NACK
Data (n)
: START condition
: STOP condition
: Acknowledge bit
: Read bit (1)
: No acknowledge bit
Fig. 5.5.2 Staus read timing
(2) Byte write
Bytes are written by sending the START condition, slave address “BA16,” sub-address (1 byte), data
(1 byte), and the STOP condition from the master.
S
Bus operation of T
A
master side: R
T
Slave
address (W)
Sub-address (n)
S
T
O
P
Data (n)
W
SDA signal S
P
A
C
K
Bus operation of
slave side:
S
P
ACK
W
A
C
K
A
C
K
: START condition
: STOP condition
: Acknowledge bit
: Write bit (0)
Fig. 5.5.3 Byte write timing
7220 Group User’s Manual
5-27
APPLICATION
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP)
5.5.4 General flowchart
(1) Write processing routine
The processing routine which controls I 2C-BUS devices branch to the write processing routine and
the read processing routine. The START condition, the STOP condition and the data output processing
routine are used as the common processing routine.
➀
S
➁
➂
Slave address
(W) “BA 16”
A
C
K
Sub-address
A
C
K
➃
➄
Data
A
C P
K
Write start
RAM: WRITEDATA
NO ACK COUNTER
WRITE DATA COUNTER
Flag: F_ACK
“WRITEDATA”
←Slave address (W) “BA 16”
“WRITE DATA COUNTER”
= “1” (number of write bytes)
“NO ACK COUNTER” = “0”
START condition
Data output
No (no ACK)
➀
➁
“F_ACK” = “0”?
Yes (ACK)
“WRITEDATA” ←Sub-address
Data output
➂
No (no ACK)
“F_ACK” = “0”?
STOP condition
Yes (ACK)
“WRITE DATA
“NO ACK COUNTER”
←“NO ACK COUNTER” + 1
No (not yet)
COUNTER” = “0”?
Yes (end)
“NO ACK COUNTER”
No (try 3 times)
≥ “3”?
Yes (give up)
STOP condition
➄
Bus H
Data output
End
“WRITE DATA COUNTER”
←“WRITE DATA COUNTER” – 1
Fig. 5.5.4 Flowchart of write processing routine
5-28
“WRITEDATA” ←Write data
7220 Group User’s Manual
➃
APPLICATION
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP)
(2) Read processing routine
➀
➁
➂
➃
➄
➅
➆➇
(See note 1)
S
Slave address
(W) “A0 16”
A
C
K
Sub-address
A
R
C
K S
Slave address
(R) “A1 16”
A
C
K
Data
N
A P
C
K
RAM: WRITEDATA
NO ACK COUNTER
READ DATA COUNTER
Flag: F_ACK
Read start
To M52340SP ?
(See note 2)
No (to other devices (cf. E 2PROM))
Yes (sub-address is not necessary at reading)
“WRITEDATA”
←Slave address (W) “A0 16”
“NO ACK COUNTER” = “0”
START condition
Data output
No (no ACK)
➀
➁
“F_ACK” = “0”?
Yes (ACK)
“WRITEDATA” ←Sub-address
Data output
➂
No (no ACK)
“F_ACK” = “0”?
Yes (ACK)
START condition
➃
“WRITEDATA”
←Slave address (R) “A1 16”
Data output
➄
No (no ACK)
Notes 1: NACK = No ACK
2: Branches according to whether the
device needs sub-address or not.
“F_ACK” = “0”?
Yes (ACK)
Data input
➅
STOP condition
“READ DATA
No (not yet)
COUNTER” = “0”?
“NO ACK COUNTER”
←“NO ACK COUNTER” + 1
Yes (end)
Return NACK
➆
STOP condition
➇
“NO ACK COUNTER”
No (try 3 times)
≥ “3”?
Yes (give up)
Bus H
Return ACK
“READ DATA COUNTER”
←“READ DATA COUNTER” – 1
End
Fig. 5.5.5 Flowchart of read processing routine
7220 Group User’s Manual
5-29
APPLICATION
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP)
(3) Data output processing routine
The data output, the START condition, the STOP condition, and the bus H processing routines are
the common routines within the transmit/receive processing routine.
RAM: WRITEDATA
BIT COUNTER
Flag: F_ACK
Data output
Bit 0 of port P2 direction register
= “output mode”
“BIT COUNTER” = “0”
Rotate “WRITEDATA” left
with Carry flag
Carry flag = “1”?
No
Yes
P20 (SDA) = “1”
P20 (SDA) = “0”
P21 (SCL) = “1”
Wait 6 µs
P21 (SCL) = “0”
“BIT COUNTER”
←“BIT COUNTER” + 1
No
“BIT COUNTER”
≥ “8”?
Yes
Bit 0 of port P2 direction register
= “input mode
Wait 6 µs
P21 (SCL) = “1”
Wait 6 µs
No
P20 (SDA) = “1”?
Yes
F_ACK = “1”
P21 (SCL) = “0”
RETURN
Fig. 5.5.6 Flowchart of data output processing routine
5-30
7220 Group User’s Manual
F_ACK = “0”
APPLICATION
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP)
(4) START condition processing routine
START condition
P20 (SDA) = “1”
Bit 0 of port P2 direction register
= “output mode”
Wait 6 µs
P21 (SCL) = “1”
P20 (SDA) = “0”
Wait 6 µs
P21 (SCL) = “0”
RETURN
Fig. 5.5.7 Flowchart of START condition processing routine
(5) STOP condition processing routine
STOP condition
Bit 0 of port P2 direction register
= “output mode”
P20 (SDA) = “0”
P21 (SCL) = “1”
Wait 6 µs
P20 (SDA) = “1”
RETURN
Fig. 5.5.8 Flowchart of STOP condition processing routine
(6) Bus H processing routine
Bus H
Bit 0 of port P2 direction register
= “output mode”
P21 (SCL) = “1”
Wait 6 µs
P20 (SDA) = “1”
RETURN
Fig. 5.5.9 Flowchart of bus H processing routine
7220 Group User’s Manual
5-31
APPLICATION
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP)
(7) Data input processing routine
RAM: READDATA
BIT COUNTER
Data intput
Bit 0 of port P2 direction register
= “input mode”
“BIT COUNTER” = “0”
P21 (SCL) = “1”
Wait 6 µs
P20 (SDA) = “1”?
No
Yes
Carry flag = “1”
Rotate “READDATA”
with Carry flag, to left
P21 (SCL) = “1”
“BIT COUNTER”
←“BIT COUNTER” + 1
No
“BIT COUNTER”
≥ “8”?
Yes
RETURN
Fig. 5.5.10 Flowchart of data input processing routine
5-32
7220 Group User’s Manual
Carry flag = “0”
APPLICATION
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP)
(8) Return ACK processing routine
Return ACK
Bit 0 of port P2 direction register
= “output mode”
P20 (SDA) = “0”
Wait 6 µs
P21 (SCL) = “1”
Wait 6 µs
P21 (SCL) = “0”
RETURN
Fig. 5.5.11 Flowchart of return ACK processing routine
(9) Return NACK processing routine
Return NACK
Bit 0 of port P2 direction register
= “output mode”
P20 (SDA) = “1”
Wait 6 µs
P21 (SCL) = “1”
Wait 6 µs
P21 (SCL) = “0”
RETURN
Fig. 5.5.12 Flowchart of return NACK processing routine
7220 Group User’s Manual
5-33
APPLICATION
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP)
5.5.5 Data setting according to key processing
Examples of the M52340SP settings, corresponding to each actual TV set key input, are described below.
(1) “Power ON/OFF key” input
When power supply is supplied to the
M52340SP by this input, the data is set to all
registers (at sub-addresses “0016” to “1316”).
(2) “Tuning and search-related keys” (CH
UP/DOWN key, CH direct selection key) input
When tuning, the color system data (refer to
“Table 5.5.10”) is set according to the
determination result of the color system by
the status data register (refer to “Table 5.5.1”).
Also, the corresponding data is set when the
color system search-related keys are input.
However, note that the above-mentioned setting
is valid only when setting AUTO (bit 5 at subaddress 0616, write data) to “0.” When setting
to “1,” the data is automatically set inside the
M52340SP.
When tuning, the data is set as shown in Table
5.5.1.
Table 5.5.1 Data setting at tuning and searching
Sub-address
Data
Bit
(3) “Volume UP/DOWN key” input
When the volume up/down key is input, the
data is set as shown in Table 5.5.2.
Table 5.5.2 Data setting at “volume UP/DOWN key”
input
Sub-address
Data
Bit
03 16
AUDIO ATT
D0 to D6
(4) “Screen-size-related keys” input
When the screen-related keys are input on
TVs with various screen sizes (wide aspect
TV, etc.), the screen size data and position
data is set as shown in Table 5.5.3. Also, the
data of each frequency (50 Hz or 60 Hz) is
occasionally held.
Table 5.5.3 Data setting at “screen-size-related
keys” input
Sub-address
Data
Bit
0916
H PHASE
D3 to D6
(5)
Table 5.5.4 Data setting at “picture data control
key” and “picture memory switching
key” input
“Picture data control key” and “Picture
memory switching key” input
When changing picture data, the data is set
to the corresponding write data register as
shown in Table 5.5.4.
02 16
06 16
Sub-address
TRAP
D4
D1
DBF
D0, D1
DFA
DL TIME
Bit
Data
04 16
D0 to D5
SHARPNESS
05 16
D0 to D6
CONTRAST
07 16
08 16
D0 to D6
TINT
D0 to D6
D0 to D6
COLOR
BRIGHT
0A16
5-34
D5
7220 Group User’s Manual
APPLICATION
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP)
(6) Data setting when changing AFT (auto fine
tuning) state
To change the state of auto fine tuning at
presetting CH and ordinary tuning, the bit is
set as shown in Table 5.5.5.
Table 5.5.5 Data setting when changing AFT state
Sub-address
Data
Bit
04 16
DEFEAT
D6
(7) Data setting when changing audio mute
state
When the audio mute key is input, the bit is
set as shown in Table 5.5.6. If it is necessary
to delete the sound while tuning with the tuning
key input or presetting CH, the bit is set as
shown in Table 5.5.6.
Table 5.5.6 Data setting when changing audio mute
state
(8) Data setting when changing video mute
state
When muting the video on screen while tuning
with the tuning key input, the bit is set as
shown in Table 5.5.7.
(9) D a t a s e t t i n g w h e n a d j u s t i n g w h i t e
balance
When adjusting the TV picture in the factory,
set the data shown in Table 5.5.8 to ready
the service mode for adjusting the white color.
Sub-address
0116
Bit
Data
D6
A MUTE
Table 5.5.7 Data setting when changing video mute
state
Data
Sub-address
Bit
MUTE
0B 16
D6
Table 5.5.8 Data setting when adjusting white color
balance
Data
Sub-address
Bit
SERSW
1316
D3
7220 Group User’s Manual
5-35
APPLICATION
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP)
5.5.6 Flowchart of data setting according to key processing
Figures 5.5.13 to 5.5.15 show the flowcharts of controlling the M52340SP when there are various event
inputs to the actual TV system.
(1) Poweron processing by “power key“ input
Power on
Wait for stabilizing time to supply
power source.
•Set write data register of M52340SP
•To mute video and audio;
MUTE (D6 at sub-address 0B 16)←“1”
A MUTE (D6 at sub-address 01 16)←“1”
Related processings:
•OSD when power on
•Write last data to E 2PROM
, etc.
Wait for muting time
To release mute of picture and sound:
MUTE (D6 at sub-address 0B 16)←“0”
A MUTE (D6 at sub-address 01 16)←“0”
END
Fig. 5.5.13 Flowchart of poweron processing
5-36
7220 Group User’s Manual
APPLICATION
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP)
(2) “CH UP/DOWN key“ input processing
CH UP/DOWN
To mute video and audio:
MUTE (D6 at sub-address 0B 16)←“1”
A MUTE (D6 at sub-address 01 16)←“1”
Related processings:
•Changing CH
•OSD when changing CH
•Write last data to E 2PROM
, etc.
Set the following (color system):
•3.58 (D2 at sub-address 09 16)
•NTSC (D1 at sub-address 02 16)
•SECAM (D0 at sub-address 09 16)
Wait for muting time
To release mute of picture and sound;
MUTE (D6 at sub-address 0B 16)←“0”
A MUTE (D6 at sub-address 01 16)←“0”
END
Fig. 5.5.14 Flowchart of “CH UP/DOWN key” input processing
7220 Group User’s Manual
5-37
APPLICATION
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP)
(3) Processing of “picture memory switching key“ input
Picture memory switching
Related processings:
•Read out picture data from RAM
•Changing picture data
•OSD when switching picture memory
•Write last data to E 2PROM
, etc.
Set the following according to
each picture memory mode:
•SHARPNESS (D0 to D5 at sub-address 04 16)
•CONTRAST (D0 to D6 at sub-address 05 16)
•TINT (D0 to D6 at sub-address 07 16)
•COLOR (D0 to D6 at sub-address 08 16)
•BRIGHT (D0 to D6 at sub-address 0A 16)
END
Fig. 5.5.15 Flowchart of “picture memory switching key” input processing
5-38
7220 Group User’s Manual
APPLICATION
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP)
5.5.7 Register map
The M52340SP has 2 kinds of registers; the status data register and the write data registers.
(1) Status data register
The status data register indicates various signal state from the M52340SP side. The state is confirmed
by regularly reading each bit.
Status data register
b7 b6 b5 b4 b3 b2 b1 b0
Status data register
0
1
Name
Color system determination bit 0
(CONDITION)
Color system determination bit 1
(SECAM)
2
Color system determination bit 2
(NTSC)
3
3.58/4.43 determination bit
(3.58)
4
AFT signal detection
bit 0 (AFT0)
5
AFT signal detection
bit 1 (AFT1)
6
7
Functions
0
R —
0
R W
0
R W
0 : 4.43 MHz
1 : 3.58 MHz
0
R W
0
R W
0
R W
0
R W
0
R W
0 : Under determination
1 : Determination is completed
b2
0
0
1
1
b1
0
1
0
1
Image system
PAL
SECAM
NTSC
SECAM
-100kHz f0 +100kHz Freq.
D5: AFT1 1
1
0
0
D4: AFT0 1
0
0
1
Synchronous presence
0 : Without synchronization
determination bit (COINCIDENCE) 1 : It is synchronization
Frequency determination bit
(50/60)
After reset R W
Pin1 AFT OUT
B
0 : 50 Hz
1 : 60 Hz
Fig. 5.5.16 Status data register
7220 Group User’s Manual
5-39
APPLICATION
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP)
■ Bit 0: Color system determination bit 0 (CONDITION)
This bit indicates whether the color system is being determined or not. Figure 5.5.16 shows the
state of determination, according to the bit, when AUTO (bit 5 at sub-address 06 16, write data) is
set to “1.” When AUTO (bit 5 at sub-address 06 16, write data) is set to “0,” bit 0 is invalid as the
color system is not determined automatically.
■ Bit 1: Color system determination bit 1 (SECAM)
Bit 2: Color system determination bit 2 (NTSC)
These bits determine the color system.
■ Bit 3: 3.58/4.43 determination bit (3.58)
This bit determines whether a color signal sub-carrier of the color system is 3.58 MHz or 4.43 MHz.
■ Bit 4: AFT signal detection bit 0 (AFT0)
Bit 5: AFT signal detection bit 1 (AFT1)
These bits detect the level of the auto fine tuning signal.
■ Bit 6: Synchronous presence determination bit (COINCIDENCE)
This bit determines whether Pin H.OUT output is synchronized with the video signal or not.
■ Bit 7: Field Frequency determination bit (50/60)
This bit determines whether the field frequency is 50 Hz or 60 Hz. According to the state of this
bit, the display position or a vertical direction size of video can be changed.
5-40
7220 Group User’s Manual
APPLICATION
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP)
(2) Write data register
Write data register
Sub-address
D7
D6
D5
D4
D3
D2
00 16
POS/NEG
DELAY ADJ
01 16
A MUTE
VCO ADJ
TRAP
02 16
DBF
03 16
04 16
D0
DFA
4.5/6.0
AUDIO ATT
SHARPNESS
DEFEAT
CONTRAST
05 16
06 16
TINT
08 16
COLOR
09 16
DL TIME
TV/EXT
AUTO
07 16
3.58
H PHASE
0A16
0B16
D1
NTSC
SECAM
BRIGHT
MUTE
DRIVE R
DRIVE B
0C16
0D16
CUT OFF R
0E16
CUT OFF G
0F16
CUT OFF B
10 16
F TRAP
11 16
12 16
13 16
AFCG
HST
SERSW
: No function
Fig. 5.5.17 Map of write data register
7220 Group User’s Manual
5-41
APPLICATION
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP)
■ DELAY ADJ
This adjusts the RF AGC delay point. The output level of tuner decreases when the value
increase, the output level increases when the value decreases.
■ POS/NEG
This switch sets the VIF output signal to either the positive or the negative modulation signal.
When “0,” the negative modulation signal is selected; when “1,” the positive modulation signal is
selected.
■ VCO ADJ
This register changes the free running frequency of VIF VCO. The frequency increases when the
value increases, the frequency decreases when the value decreases.
■ A MUTE
This is the audio mute ON/OFF.
■ 4.5/6.0
This bit must be set to “1” when the sound carrier frequency is 4.5 MHz. Set “0” when the
frequency is other values.
■ DFA, DL TIME
In order to adjust the color signal and the luminance signal is delayed using the on-chip delay-line.
The DL TIME register adjusts the delay approximately, and the DFA register performes the fine
adjustments. When DFA is “1,” actual delay time is +50 ns; when “0,” it is +0 ns. For relationship
between DFA and DL TIME, refer to “Table 5.5.9.”
Table 5.5.9 Relationship between DFA and DL TIME
DL
DL
TIME1
TIME0
0
0
0
170 ns
1
2
0
0
0
1
120 ns
Data
DFA
Actual
delay time
3
0
0
1
1
0
1
330 ns
280 ns
4
1
0
0
410 ns
5
1
0
1
360 ns
6
1
0
490 ns
7
1
1
1
1
440 ns
■ DBF
The M52340SP has 2 TRAP; the second TRAP extends the bandwidth of the TRAP, described
below. DBF is the ON/OFF switch for the second TRAP. When “1,” it is on; when “0,” it is off. DBF
is used in SECAM and other methods.
■ TRAP
This is the TRAP ON/OFF switch for taking out the luminance signal (Y-signal) by Y/C separation
(Y = Y-signal, C = color signal) of the composite video signal. When “1,” it is on; when “0,” it is
off.
■ AUDIO ATT
Data is set (“0” to “127”) to change the volume.
5-42
7220 Group User’s Manual
APPLICATION
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP)
■ SHARPNESS, CONTRAST, TINT, COLOR, BRIGHT
Data is set to change the picture data.
Some TVs have a picture mode function (such as the movie mode, standard mode), the fixed data
is set according to the mode. Accordingly, it is necessary to change the picture data when changing
the picture mode.
■ DEFEAT
This switch turns DEFEAT off when AFT is on, and vice versa.
■ TV/EXT
This selects either a TV’s signal or an external device’s signal. This bit should be set to “0” when
TV’s signal is selected and set to “1” when an external device’s signal is selected.
■ AUTO
This determines whether the automatic determination of the color system is used or not. When
AUTO is “0,” manual determination is set; when “1,” determination is performed automatically.
■ 3.58/NTSC/SECAM
When setting AUTO (bit 5 at sub-address 0616, write data) to “1,” these bits are automatically set
inside the M52340SP. When setting AUTO to “0,” it is necessary to set the data shown in Table
5.5.10, according to the color system.
Table 5.5.10 Setting of color system (at sub-address
09 16, write data)
Color system
D2
D1
D0
3.58
NTSC
SECAM
SECAM
0
0
0
0
0
1
NTSC3.58
1
1
0
NTSC4.43
0
1
0
PAL
■ H PHASE
The picture’s horizontal position is adjusted. Data is given every 50 Hz or 60 Hz and the data is
set when frequency changes. For wide TVs etc., data is given for each screen size mode, and the
data is set when the screen size mode changes.
■ DRIVE R, DRIVE B
Data is used to adjust the output amplitude ratio of R, G and B signals. Since G is the fixed data,
its ratio is adjusted by R and B.
■ MUTE
This is the video mute ON/OFF switch.
■ CUT OFF R, CUT OFF G, CUT OFF B
Data is used to adjust the output DC level of R, G and B signals.
■ F TRAP
This register performes the fine adjustments to the trap frequency of TRAP for Y/C separation.
7220 Group User’s Manual
5-43
APPLICATION
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP)
■ SERSW
This switch is for white balance adjustments of the TV picture in the factory. When SERSW is “0,”
it is OFF; when “1,” it is ON.
■ HST
This switch stops horizontal oscillation. When HST is “0,” the oscillation continues; when “1,” it
stops.
■ AFCG
This switch increases AFC gain. When AFCG is “0,” AFC gain is normal; when “1,” it is high.
5-44
7220 Group User’s Manual
E2PROM
M6M80012P/22P
SCL
M52340SP
7220 Group User’s Manual
SDA
SCL
SDA
TELETEXT
TV/
AV
POW
VOL
(+)
A-D key
CH
(—)
CH
(+)
Vol
(—)
Sound multiplex
input
I2C Bus
Pre-amplifier
X OUT
X IN
A-D2
A-D1
P30
P31
SDA1
SCL1
INT1
V CC
VSS CNVSS
5V
M37221Mx-XXXSP/FP
Fig. 5.6.1 Application circuit example 1 (I2C-BUS chassis)
Single-chip color TV
signal processor
(Including volume, color,
brightness, contrast and
tint control. Also including
AFC and synchronous
information.)
SDA
SCL
M34238MK-XXXGP
Remote controller
I2C-BUS chassis (voltage synthesizer)
OSC2
OSC1
RESET
P03
P04
P05
P06
P20
P25
HSYNC
VSYNC
R
G
B
OUT
P26
PWM0
PWM1
PWM2
P21
P22
P23
P24
D-A
MUTE
Power ON/OFF
Reset
TV/VIDEO exchange
Sound multiplex exchange
R
G
B
OUT
HSYNC
VSYNC
ON TIMER LED
Bass control
Treble control
Balance control
Electric
tuner
Note: The oscillation for OSD can be
also obtained from main clock
(refer to application example 2).
Low pass filter
Low pass filter
VHF-L
VHF-H
UHF
CATV
Antenna
APPLICATION
5.6 Application circuit example
5.6 Application circuit example
5.6.1 Application circuit example 1
5-45
5-46
7220 Group User’s Manual
TV/
AV
POW
VOL
(+)
A-D key
CH
(—)
CH
(+)
Vol
(—)
TIM2
X OUT
X IN
A-D2
A-D1
P13
P14
P21
P17
A-D4
AFC input
P20
P33
P22
P23
INT1
Synchronous input
Pre-amplifier
V CC
VSS CNVSS
M37220M3-XXXSP/FP
Fig. 5.6.1 Application circuit example 2 (Non-BUS chassis)
PAL
SECAM
NTSC4.43
NTSC3.58
CS
E2PROM
M6M80011P/21P
CLK
DATA IN
DATA OUT
M34236MJ-XXXGP
Remote controller
Non-BUS chassis (voltage synthesizer)
TV/VIDEO exchange
Sound multiplex exchange
Power ON/OFF
Reset
P32
RESET
P30
P31
P25
P26
P27
Note: The oscillation for OSD can be obtained from
main clock, so external oscillation circuit can be
omitted.
MUTE
Antenna
Volume control
Color control
Brightness control
Contrast control
Tint control
Sharpness control
Electric
tuner
HSYNC
VSYNC
R
G
B
OUT
Low pass filter
VHF-L
VHF-H
UHF
CATV
HSYNC
VSYNC
R
G
B
OUT
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
AFT defeat
Band decoder
P10
P11
P12
Low pass filter
D-A
APPLICATION
5.6 Application circuit example
5.6.2 Application circuit example 2
CHAPTER 6
APPENDIX
6.1 Package outlines
6.2 Termination of unused pins
6.3 Notes on use
6.4 Countermeasures against noise
6.5 Memory assignment
6.6 SFR assignment
6.7 Control registers
6.8 Ports
6.9 Machine instruction table
6.10 Instruction code table
6.11 Mask ROM ordering method
6.12 Mark specification form
APPENDIX
6.1 Package outline
6.1 Package outline
6-2
7220 Group User’s Manual
APPENDIX
6.2 Termination of unused pins
6.2 Termination of unused pins
Table 6.2.1 Termination of unused pins
Pin
M37221Mx-XXXSP/FP
M37220M3-XXXSP/FP
Input/
Output
Termination
I/O
Set the port direction registers for the input
mode and pull-down through a resistor.
P0 0/PWM0–P05/PWM5
P0 6/INT2/A-D4
✽
P0 7/INT1
P1 0/OUT2
P10
P1 1/SCL1
P11
P1 2/SCL2
P12
P1 3/SDA1
P13
P1 4/SDA2
P14
P1 5/A-D1/INT3
P1 6/A-D2
P1 7/A-D3
P2 0/S CLK
P2 1/S OUT
✽
P2 2/S IN
P2 3/TIM3
P2 4/TIM2
P2 5–P27
P3 0/A-D5
P30/A-D5/DA1
P3 1/A-D6
P30/A-D6/DA2
P3 2
✽
P3 3/OSC1
P3 4/OSC2
H SYNC
✽
Input
Pull-down through a resistor.
Output
Open
VSYNC
P5 2/R
P5 3/G
✽
P5 4/B
P5 5/OUT1
P55/OUT
XOUT
D-A
✽
✽ It is the same as M37221Mx-XXXSP/FP.
7220 Group User’s Manual
6-3
APPENDIX
6.3 Notes on use
6.3 Notes on use
Notes on programming and equipping when using M37221M6-XXXSP/FP are described below.
6.3.1 Notes on processor status register
(1) Initialization of processor status register
The contents of processor status register (PS)
are undefined except the I flag (I = “1”)
immediately after reset. Therefore initialize the
flags that affect execution of a program.
Especially be sure to initialize the T and D
flags because they have an important effect
on calculations.
Reset
Initialization of flags
Main program
Fig. 6.3.1 Initialization of flags in PS
(2) How to refer to processor status register
When referring to the processor status register
(PS) contents, execute the PHP instruction to
push the processor status register contents
into the stack (S) + 1. And then read the
contents of stack (S) + 1.
If necessary, execute the PLP instruction to
pull the pushed PS contents. In that case, be
sure to execute the NOP instruction immediately
after the PLP instruction.
(S)
(S) + 1
Pushed PS
Fig. 6.3.2 Stack contents after PHP instruction
execution
Execute PLP instruction
Execute NOP instruction
Fig. 6.3.3 Note when executing PLP instruction
6-4
7220 Group User’s Manual
APPENDIX
6.3 Notes on use
6.3.2 Notes on decimal operation
(1) How to execute arithmetic operation
instructions in decimal operation mode
To calculate in decimal notation, set the decimal
operation mode flag (D) to “1” by using the
SED instruction, and execute the ADC and
SBC instructions. After that, execute at least
one instruction to execute the SEC, CLC, or
CLD instruction.
(2) Status flags in decimal operation mode
When the ADC or SBC instruction are executed
in decimal operation mode (D flag = “1”), the
N, V, and Z flags are invalid.
The carry flag (C) is set to “1” when a carry
occurs as a result of an arithmetic operation,
or is cleared to “0” when a borrow occurs.
Therefore, the carry flag can be used to
determine whether a carry or a borrow has
occurred or not. Be sure to initialize the C
flag before each arithmetic operation.
6.3.3 Notes on Interrupts
(1) Executing BBC or BBS instruction
When executing the BBC or BBS instruction
to an interrupt request bit immediately after
this bit is set to “0” by using a data transfer
instruction✽1, execute one or more instructions
before executing the BBC or BBS instruction.
Set the decimal mode flag D
to “1”
Execute ADC or SBC instruction
Execute NOP instruction
Execute SEC, CLC, or CLD instruction
Fig. 6.3.4 Note in decimal arithmetic operation
Clear the interrupt request (request distinguish)
bit to “0” (no interrupt issued)
NOP (one or more instructions)
Reason
If the BBC or BBS instruction is executed
immediately after an interrupt request bit of
an interrupt request register is cleared to “0,”
the value of the interrupt request bit before
being cleared to “0” is read.
✽1: data transfer instructions: LDM, LDA, STA,
STX, and STY instructions
Execute BBC or BBS instruction
Fig. 6.3.5 Execution of BBC or BBS instruction
7220 Group User’s Manual
6-5
APPENDIX
6.3 Notes on use
(2) How to switch an external interrupt detection
edge
For the products able to switch the external
interrupt detection edge, switch it as Figure
6.3.6.
Clear an interrupt enable bit to “0” (interrupt disabled)
Reason
The interrupt circuit recognizes the switching
of the detection edge as the change of external
input signals. This may cause an unnecessary
interrupt.
Switch the detection edge
Clear an interrupt request bit to “0”
(no interrupt request issued)
Set the interrupt request bit to “1” (interrupt enabled)
Fig. 6.3.6 Sequence for switching an external
interrupt detection edge
6.3.4 Notes on serial I/O
(1) Initialization for the serial I/O
For the serial I/O interrupt, initialize as Figure
6.3.7.
(2) Write transmit data to transmit buffer
When an external clock is used as the
synchronous clock for the clock synchronous
serial I/O, write the transmit data to the serial
I/O shift register at HIGH of the transfer clock
input level.
Clear the serial I/O interrupt enable bit to “0”
(interrupt disabled)
Select the serial I/O mode
(set the serial I/O port selection bit to “1”)
NOP (one or more instructions)
Clear the serial I/O interrupt request bit to “0”
(no interrupt request issued)
Set the serial I/O interrupt enable bit to “1”
(interrupt enabled)
Fig. 6.3.7 Initialization for serial I/O
6-6
7220 Group User’s Manual
APPENDIX
6.3 Notes on use
6.3.5 Notes on timer
When a timer value is read, “the timer value at read timing + 1” may be read.
Reason
Figure 6.3.8 shows the relation between timer values and their values read. Timer values are changed at
the rising edge of the count source, but the values read are counted down at the falling edge of the count
source. Therefore, “the timer value + 1” may be read in some read timings.
Figure 6.3.9 shows the relation between timer values and their values read when two 8-bit timers are
connected in series. In this example, timers 1 and 2 are connected in series and an overflow signal of
timer 1 is used as the count source of timer 2. The timer 2 values read are counted down at the falling
edge of the count source. When timers 1 and 2 are used as a single 16-bit counter, the timer 2 values
read take the same value at timing A and B (or at timing C and D) as shown in Figure 6.3.9. This is
because the count source of timer 2 changes at the falling edge of the count source of timer 1.
Timer count
source
Timer value
Timer 1
count
source
1
0
FF
Timer value read
2 1
0
Interrupt request
Writing to
timer 1
FF
1
0
1
FF
0
FF
1
0
Timer 1
value
1
0
FF 1
0
FF 1
0
FF 1
1
Timer 1
value read
Fig. 6.3.8 Relation between timer values and their
values read (timer setting value = 2)
Timer 1
interrupt
request
Timer 2
count
source
Timer 2
value
Timer 2
value read
Timer 2
interrupt
request
2 1
0
FF 1
0 FF
1
0
FF
1
Writing to
timer 1
0
FF
A
1
0
BC
0
FF
D
FF
0
Writing to
timer 2
Fig. 6.3.9 Relation between timer values and their
values read when two timers are
connected in series (timers 1 and 2
are connected, timer 1 setting value
= 2, timer 2 setting value = 1)
7220 Group User’s Manual
6-7
APPENDIX
6.3 Notes on use
6.3.6 Notes on A-D comparator
(1) Signal source impedance for analog input
Make the signal source impedance for analog input low, or equip an analog input pin with an external
capacitor of 0.01 µ F to 1 µ F. Further, be sure to verify the operation of application products on the
user side.
Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when signals
from signal source with high impedance are input to an analog input pin, charge and discharge noise
generates. This may cause the A-D comparison precision to be worse.
(2) Note during an A-D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A-D comparison.
●f(X IN) is 500 kHz or more
●Do not execute the STP instruction and WIT instruction
6.3.7 Note on RESET pin
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the RESET
pin and the V SS pin. And use a 1000 pF or more capacitor for high frequency use. When connecting the
capacitor, note the following :
●Make the length of the wiring which is connected to a capacitor as short as possible.
●Be sure to check the operation of application products on the user side.
Reason
______
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may cause
a microcomputer failure.
6-8
7220 Group User’s Manual
APPENDIX
6.3 Notes on use
6.3.8 Notes on input and output pins
(1) Fix of a port input level in stand-by state
In stand-by state ✽2 for low-power dissipation, do not make input levels of an input port and an I/O
port “undefined,” especially for I/O ports of the P-channel and the N-channel open-drain.
Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor.
When determining a resistance value, note the following points:
●External circuit
●Variation of output levels during the ordinary operation
When using built-in pull-up or pull-down resistor, note on varied current values.
●When setting as an input port : fix its input level
●When setting as an output port : prevent current from flowing out to external
Reason
Even when setting as an output port with its direction register, in the following state :
●N-channel......when the content of the port latch is “1”
the transistor becomes the OFF state, which causes the ports to be the high-impedance state. Note
that the level becomes “undefined” depending on external circuits.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the
state that input levels of a input port and an I/O port are “undefined.” This may cause power source
current.
✽2 stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
(2) Modify of the contents of I/O port latch
When the port latch of an I/O port is modified with the bit managing instruction✽3, the value of the
unspecified bit may be changed.
Reason
The bit managing instructions✽3 are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the data register of an
I/O port, the following is executed to all bits of the data register.
●As for a bit which is set for an input port :
The pin state is read in the CPU, and is written to this bit after bit managing.
●As for a bit which is set for an output port :
The bit value is read in the CPU, and is written to this bit after bit managing.
Note the following :
●Even when a port which is set as an output port is changed for an input port, its data register holds
the output data.
●As for a bit of which is set for an input port, its value may be changed even when not specified
with a bit managing instruction in case where the pin state differs from its data register contents
✽3 bit managing instructions : SEB, and CLB instruction
6.3.9 Note on JMP instruction
When using the JMP instruction (the indirect addressing mode), do not specify the last address in a page
as an indirect address.
Memory (addresses 0000 16 to FFFF 16) is separated into pages (by each 256 address).
7220 Group User’s Manual
6-9
APPENDIX
6.3 Notes on use
6.3.10 Note on multi-master I 2C-BUS interface
This function is used at f(X IN) = 8.0 MHz of oscillation frequency.
6.3.11 Termination of unused pins
(1) Proper termination of unused pins
■ Output ports : Open
■ Input ports :
Connect each pin to V CC or V SS through each resistor of 1 kW to 10 kW.
Ports that permit the selecting of a built-in pull-up or pull-down resistor can also use this resistor.
As for pins whose potential affects to operation modes such as pins CNVSS, INT or others, select
the VCC pin or the V SS pin according to their operation mode.
■ I/O ports :
•Set the I/O ports for the input mode and connect them to V CC or V SS through each resistor of
1 kΩ to 10 kΩ. Set the I/O ports for the output mode and open them at “L” or “H.”
•When opening them in the output mode, the input mode of the initial status remains until the mode
of the ports is switched over to the output mode by the program after reset. Thus, the potential
at these pins is undefined and the power source current may increase in the input mode. With
regard to an effects on the system, thoroughly perform system evaluation on the user side.
•Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability.
(2) Incorrect termination of unused pins
■ input ports and I/O ports :
Do not open in the input mode.
Reason
•The power supply current may increase depending on the first-stage circuit.
•An effect due to noise may be easily produced as compared with proper termination (1).
shown on the above.
■ I/O ports :
Set for input mode and do not connect to VCC or V SS directly.
Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and VCC (or V SS).
■ I/O ports :
Set for the input mode and do not connect multiple ports in a lump to VCC or VSS through a resistor.
Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
(3) At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or
less) from microcomputer pins.
6-10
7220 Group User’s Manual
APPENDIX
6.4 Countermeasures against noise
6.4 Countermeasures against noise
Countermeasures against noise are described below. The following countermeasures are effective against
noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual
use.
6.4.1 Shortest wiring length
The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer.
(1) Wiring for reset input pin
Make the length of wiring which is connected
to the RESET input pin as short as possible.
Especially, connect a capacitor across the
RESET input pin and the V SS pin with the
shortest possible wiring (within 20mm).
Noise
Reset
circuit
RESET
VSS
VSS
Reason
The width of a pulse input into the RESET
pin is determined by the timing necessary
conditions. If noise having a shorter pulse width
than the standard is input to the RESET input
pin, the reset is released before the internal
state of the microcomputer is completely
initialized. This may cause a program runaway.
N.G.
Reset
circuit
VSS
RESET
VSS
O.K.
Fig.6.4.1 Wiring for RESET input pin
(2) Wiring for clock input/output pins
●Make the length of wiring which is connected
to clock
●I/O pins as short as possible.
●Make the length of wiring (within 20mm)
across the grounding lead of a capacitor
which is connected to an oscillator and the
V SS pin of a microcomputer as short as
possible.
●Separate the V SS pattern only for oscillation
from other V SS patterns.
Noise
XIN
XOUT
VSS
N.G.
Reason
If noise enters clock I/O pins, clock waveforms
may be deformed. This may cause a program
failure or program runaway. Also, if a potential
difference is caused by the noise between
the VSS level of a microcomputer and the VSS
level of an oscillator, the correct clock will not
be input in the microcomputer.
XIN
XOUT
VSS
O.K.
Fig.6.4.2 Wiring for clock I/O pin
7220 Group User’s Manual
6-11
APPENDIX
6.4 Countermeasures against noise
(3) Wiring to CNVss pin
Connect the CNVSS pin to the VSS pin with the
shortest possible wiring.
Reason
The processor mode of a microcomputer is
influenced by a potential at the CNVSS pin. If
a potential difference is caused by the noise
between pins CNV SS and V SS, the processor
mode may become unstable. This may cause
a microcomputer malfunction or a program
runaway.
Noise
CNV SS
CNV SS
VSS
VSS
O.K.
N.G.
Fig.6.4.3 Wiring for CNV SS pin
(4) Wiring to VPP pin of One Time PROM version
and EPROM version
When the V PP pin is also used as the CNVSS
pin✽1
Connect an approximately 5 kW resistor to
the VPP pin the shortest possible in series and
also to the VSS pin. When not connecting the
resistor, make the length of wiring between
the VPP pin and the VSS pin the shortest possible
(refer to “countermeasure example 1 of
Figure 6.4.4”)
✽1 When a microcomputer has the CNVSS pin,
the VPP pin is also used as the CNV SS pin.
Note: Even when a circuit which included an
approximately 5 kW resistor is used in
the Mask ROM version, the microcomputer operates correctly.
Approximately
5kΩ
CNVSS/VPP
VSS
In the shortest
distance
Fig.6.4.4 Wiring for V PP pin of One Time
PROM and EPROM version
Reason
The V PP pin of the One Time PROM and the
EPROM version is the power source input pin
for the built-in PROM. When programming in
the built-in PROM, the impedance of the VPP
pin is low to allow the electric current for writing
flow into the PROM. Because of this, noise
can enter easily. If noise enters the V PP pin,
abnormal instruction codes or data are read
from the built-in PROM, which may cause a
program runaway.
6-12
7220 Group User’s Manual
APPENDIX
6.4 Countermeasures against noise
6.4.2 Connection of a bypass capacitor across
VSS line and V CC line
Connect an approximately 0.1 µ F bypass capacitor
across the VSS line and the VCC line as follows:
●Connect a bypass capacitor across the V SS pin
and the V CC pin at equal length.
●Connect a bypass capacitor across the VSS pin
and the VCC pin with the shortest possible wiring.
●Use lines with a larger diameter than other signal
lines for V SS line and V CC line.
Chip
VCC
VSS
Fig.6.4.5 Bypass capacitor across V SS line and
V CC line
6.4.3 Wiring to analog input pins
●Connect an approximately 100 Ω to 1 kΩ resistor
to an analog signal line which is connected to an
analog input pin in series. Besides, connect the
resistor to the microcomputer as close as possible.
●Connect an approximately 1000 pF capacitor across
the V SS pin and the analog input pin. Besides,
connect the capacitor to the V SS pin as close as
possible. Also, connect the capacitor across the
analog input pin and the VSS pin at equal length.
Noise
(Note)
Microcomputer
Analog
input pin
Thermistor
N.G.
Reason
Signals which is input in an analog input pin (such
as an A-D converter/comparator input pin) are usually
output signals from sensor. The sensor which detects
a change of event is installed far from the printed
circuit board with a microcomputer, the wiring to an
analog input pin is longer necessarily. This long
wiring functions as an antenna which feeds noise
into the microcomputer, which causes noise to an
analog input pin.
If a capacitor between an analog input pin and the
VSS pin is grounded at a position far away from the
V SS pin, noise on the GND line may enter a
microcomputer through the capacitor.
O.K.
VSS
Note : The resistor is used for dividing
resistance with a thermistor.
Fig.6.4.6 Analog signal line and resistor and capacitor
7220 Group User’s Manual
6-13
APPENDIX
6.4 Countermeasures against noise
6.4.4 Oscillator concerns
Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected
by other signals.
(1) Keeping an oscillator away from large
current signal lines
Install a microcomputer (and especially an
oscillator) as far as possible from signal lines
where a current larger than the tolerance of
current value flows.
Microcomputer
Mutual inductance
M
Reason
In the system using a microcomputer, there
are signal lines for controlling motors, LEDs,
and thermal heads or others. When a large
current flows through those signal lines, strong
noise occurs because of mutual inductance.
XIN
XOUT
VSS
Large
current
GND
Fig.6.4.7 Wiring for large current signal line
(2) Installing an oscillator away from signal
lines where potential levels change
frequently
Install an oscillator and a connecting pattern
of an oscillator away from signal lines where
potential levels change frequently. Also, do
not cross such signal lines over the clock lines
or the signal lines which are sensitive to noise.
Reason
Signal lines where potential levels change
frequently (such as the CNTR pin signal line)
may affect other lines at signal rising edge or
falling edge. If such lines cross over a clock
line, clock waveforms may be deformed, which
causes a microcomputer failure or a program
runaway.
(3) Oscillator protection using VSS pattern
As for a two-sided printed circuit board, print
a VSS pattern on the underside (soldering side)
of the position (on the component side) where
an oscillator is mounted.
Connect the VSS pattern to the microcomputer
V SS pin with the shortest possible wiring.
Besides, separate this VSS pattern from other
VSS patterns.
N.G.
Do not cross
CNTR
XIN
XOUT
VSS
Fig.6.4.8 Wiring for signal line where potential
levels charge frequently
An example of V SS patterns on the
underside of a printed circuit board
Oscillator wiring
pattern example
XIN
XOUT
VSS
Separate the V SS line for oscillation from other V SS lines
Fig.6.4.9 VSS pattern on underside of an oscillator
6-14
7220 Group User’s Manual
APPENDIX
6.4 Countermeasures against noise
6.4.5 Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
●Connect a resistor of 100 Ω or more to an I/O port in series.
<Software>
●As for an input port, read data several times by a program for checking whether input levels are equal
or not.
●As for an output port, since the output data may reverse because of noise, rewrite data to its data register
at fixed periods.
●Rewrite data to direction registers and pull-up control registers (only the product having it) at fixed
periods.
When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse may
be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise pulse.
XIN
XOUT
VSS
N.G.
XIN
XOUT
VSS
O.K.
Fig. 6.4.10 Setup for I/O ports
7220 Group User’s Manual
6-15
APPENDIX
6.4 Countermeasures against noise
6.4.6 Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer
and the microcomputer can be reset to normal operation. This is equal to or more effective than program
runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer
provided by software.
In the following example, to reset a microcomputer to normal operation, the main routine detects errors of
the interrupt processing routine and the interrupt processing routine detects errors of the main routine.
This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
<The main routine>
●Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value N in the
SWDT once at each execution of the main routine. The initial value N should satisfy the following
condition:
N+1 (Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others, the initial
value N should have a margin.
●Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts
of interrupt processing after the initial value N has been set.
●Detects that the interrupt processing routine has failed and determines to branch to the program initialization
routine for recovery processing in the following case:
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
●Decrements the SWDT contents by 1 at each interrupt processing.
●Determins that the main routine operates normally when the SWDT contents are reset to the initial value
N at almost fixed cycles (at the fixed interrupt processing count).
●Detects that the main routine has failed and determines to branch to the program initialization routine for
recovery processing in the following case:
If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach
0 or less.
≠N
Main routine
Interrupt processing routine
(SWDT)← N
(SWDT) ← (SWDT)—1
CLI
Interrupt processing
Main processing
(SWDT)
≤0?
(SWDT)
=N?
N
Interrupt processing
routine errors
≤0
>0
RTI
Return
Main routine
errors
Fig. 6.4.11 Watchidog timer by software
6-16
7220 Group User’s Manual
APPENDIX
6.5 Memory assignment
6.5 Memory assignment
Hexadecimal notation
0000 16
Decimal notation
0
Internal RAM
RAM
(384 bytes)
for
M37221M6
RAM
(320 bytes)
for
M37221M4
00C0 16
00FF16
0100 16
SFR area
CRT display ROM
(8 K bytes)
Special function register
(Refer to Figures 2. 3. 3 and 2. 3. 4)
ROM
for display
Zero page
192
65536
10000 16
73727
11FFF16
255
Internal RAM
383
447
017F16
01BF 16
Not used
CRT display RAM
(96 bytes)
(See note)
0600 16
06B716
RAM
for display
1536
1719
Not used
Not used
A00016
40960
C000 16
49152
Internal ROM
ROM
(24 K bytes)
for
M37221M6
ROM
(16 K bytes)
for
M37221M4
65280
65502
FF0016
Interrupt vector area
FFFF 16
Special page
65535
1FFFF 16
131071
Note: Refer to Table 2.11.4 Contents of CRT display RAM.
Fig. 6.5.1 Memory assignment of M37221M4-XXXSP and M37221M6-XXXSP/FP
7220 Group User’s Manual
6-17
APPENDIX
6.5 Memory assignment
Decimal notation
Hexadecimal notation
0
000016
Internal RAM
1000016
65536
Zero page
RAM
(640 bytes)
for
M37221MA
RAM
(512 bytes)
for
M37221M8
00C0 16
192
Special function register
00FF16
010016
01FF16
021716
021B16
02C0 16
02FF16
030016
CRT display RAM
(96 bytes)
(See note)
SFR area
(Refer to Figures 2. 3. 3 to 2. 3. 5)
Internal RAM
255
511
2 page register
73727
535
540
Not used
ROM correction
memory (RAM)
Internal RAM
704
767
768
831
03BF 16
959
06B716
11FFF16
Not used
033F16
060016
ROM
for display
CRT display ROM
(8 K bytes)
Not used
RAM
for display
ROM correction memory
Block 1: addresses 02C0 16 to 02DF16
Block 2: addresses 02E0 16 to 02FF 16
Not used
1536
1719
Not used
24576
32768
600016
800016
ROM
(40 K bytes)
for
M37221MA
ROM
(32 K bytes)
for
M37221M8
Internal ROM
FF0016
FFDE16 Interrupt vector area
FFFF 16
65280
65502
Special page
1FFFF16
65535
Note: Refer to Table 2.11.4 Contents of CRT display RAM.
Fig. 6.5.2 Memory assignment of M37221M8-XXXSP and M37221MA-XXXSP
6-18
7220 Group User’s Manual
131071
APPENDIX
6.5 Memory assignment
Hexadecimal notation
Decimal notation
0
000016
Internal RAM
(192 bytes)
RAM
(256 bytes)
00C0 16
192
SFR area
CRT display ROM
(4 K bytes)
Zero page
Special function register
00FF16
013F16
(Refer to Figures 4.5.3 and 4.5.4)
Internal RAM
(64 bytes)
65536
1000016
ROM
for display
69631
10FFF16
255
319
Not used
CRT display RAM
(80 bytes)
(Note)
060016
06B316
RAM
for display
1536
1719
Not used
Not used
53248
D000 16
Internal ROM
ROM
(12 K bytes)
65280
65502
FF0016
FFDE16
FFFF16
Interrupt vector area
Special page
1FFFF 16
65535
131071
Note: Refer to Table 4.5.7 Contents of CRT display RAM.
Fig. 6.5.3 Memory assignment of M37220M3-XXXSP/FP
7220 Group User’s Manual
6-19
APPENDIX
6.6 SFR assignment
6.6 SFR assignment
■SFR Area (addresses C016 to DF16)
< Bit allocation >
:
Name
Function bit
:
: No function bit
0 : Fix this bit to “0”
(do not write “1”)
Address
Register
1 : Fix this bit to “1”
(do not write “0”)
Bit allocation
b0
b7
C016
C116
C216
C316
C416
C516
C616
C716
C816
C916
CA16
CB16
CC16
CD16
CE16
CF16
D016
D116
D216
D316
D416
D516
D616
D716
D816
D916
DA16
DB16
DC16
DD16
DE16
DF16
Port P0 (P0)
Port P0 direction register (D0)
Port P1 (P1)
Port P1 direction register (D1)
Port P2 (P2)
Port P2 direction register (D2)
Port P3 (P3)
Port P3 direction register (D3)
Port P5 (P5)
Port P5 direction register (D5)
Port P3 output mode control register (P3S)
DA-H register (DA-H)
0
0
P31S P30S
DA-L register (DA-L)
PWM0 register (PWM0)
PWM1 register (PWM1)
PWM2 register (PWM2)
PWM3 register (PWM3)
PWM4 register (PWM4)
PWM output control register 1 (PW)
PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0
PWM output control register 2 (PN)
I2 C data shift register (S0)
I2 C address register (S0D)
PN4 PN3 PN2
D7
D6
D5
D4
D3
D2
D1
D0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
I2 C status register (S1)
MST TRX BB
I2 C
BSEL1 BSEL0 10 BIT ALS ES0 BC2 BC1 BC0
SAD
ACK FAST
ACK BIT
CCR4 CCR3 CCR2 CCR1 CCR0
MODE
control register (S1D)
I2 C clock control register (S2)
Serial I/O mode register (SM)
Serial I/O register (SIO)
SM6 SM5
PIN
0
AL AAS AD0 LRB
SM3 SM2 SM1 SM0
0016
0016
Fig. 6.6.1 SFR assignment (including internal state immediately after reset and access characteristics) (1)
(M37221Mx-XXXSP/FP)
6-20
7220 Group User’s Manual
APPENDIX
6.6 SFR assignment
< State immediately after reset >
0 : “0” immediately after reset
RW : Read enabled, write enabled
1 : “1” immediately after reset
RO : Read enabled, write disabled
? : Indeterminate immediately
after reset
Access characteristics
State immediately after reset
b7
0
0
b0
0
0
0
?
0
0
?
0
0
0
?
0016
?
0016
?
0016
? ?
0016
?
?
? ?
0016
?
0016
?
? ?
?
?
?
?
?
0016
0016
?
0016
1 0
0016
0016
0016
?
0016
0016
b0
b7
RW
RW
RW
RW
RW
RW
?
?
RW
?
RW
?
?
RW
RW
?
RW
RW
?
?
?
0
0
?
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RW
RW
RW
RW
RW
7220 Group User’s Manual
6-21
APPENDIX
6.6 SFR assignment
■SFR Area (addresses E016 to FF16)
< Bit allocation >
:
Name
Function bit
:
: No function bit
0 : Fix this bit to “0”
(do not write “1”)
1 : Fix this bit to “1”
(do not write “0”)
Address
E016
E116
E216
E316
E416
E516
E616
E716
E816
E916
EA16
EB16
EC16
ED16
EE16
EF16
F016
F116
F216
F316
F416
F516
F616
F716
F816
F916
FA16
FB16
FC16
FD16
FE16
FF16
Register
Bit allocation
b0
b7
Horizontal position register (HR)
HR5 HR4 HR3 HR2 HR1 HR0
Vertical position register 1 (CV1)
Vertical position register 2 (CV2)
CV26 CV25 CV24 CV23 CV22 CV21 CV20
CV16 CV15 CV14 CV13 CV12 CV11 CV10
Character size register (CS)
Border selection register (MD)
Color register 0 (CO0)
CO07 CO06 CO05 CO04
CO03 CO02 CO01
Color register 1 (CO1)
CO17 CO16 CO15 CO14
CO13 CO12 CO11
Color register 2 (CO2)
CO27 CO26 CO25 CO24
CO23 CO22 CO21
Color register 3 (CO3)
CRT control register (CC)
CO37 CO36 CO35 CO34
CO33 CO32 CO31
CC7
CRT port control register (CRTP)
OP7 OP6 OP5 OUT1 OUT2 R/G/B VSYC HSYC
CRT clock selection register (CK)
CS21 CS20 CS11 CS10
MD20
0
MD10
CC2 CC1 CC0
0
A-D control register 1 (AD1)
A-D control register 2 (AD2)
Timer 1 (TM1)
0
0
0
ADM4
0
CK1 CK0
ADM2 ADM1 ADM0
ADC5 ADC4 ADC3 ADC2 ADC1 ADC0
Timer 2 (TM2)
Timer 3 (TM3)
Timer 4 (TM4)
Timer 12 mode register (T12M)
0
Timer 34 mode register (T34M)
T12M4 T12M3 T12M2 T12M1 T12M0
T34M5 T34M4 T34M3 T34M2 T34M1 T34M0
PWM5 register (PWM5)
Interrupt input polarity register (RE)
0
CPU mode register (CPUM)
1
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
IT3R
RE5 RE4
CK0 RE3
1
1
0
0
0
CM2
0
0
IICR VSCR CRTR TM4R TM3R TM2R TM1R
0
IT3E
0016
1 1
S1R 1T2R 1T1R
MSR
CK0
IICE VSCE CRTE TM4E TM3E TM2E TM1E
0
0
MSE
0
S1E 1T2E 1T1E
Fig. 6.6.2 SFR assignment (including internal state immediately after reset and access characteristics) (2)
(M37221Mx-XXXSP/FP)
6-22
7220 Group User’s Manual
APPENDIX
6.6 SFR assignment
< State immediately after reset >
0 : “0” immediately after reset
RW : Read enabled, write enabled
1 : “1” immediately after reset
RO : Read enabled, write disabled
? : Indeterminate immediately
after reset
State immediately after reset
b0
b7
0
0
?
?
?
?
0
0
0
0
0
0
0
0
0
0
0
0
?
?
1
0016
? ?
? ?
?
0 ?
0 0
0016
0016
0016
0016
0016
?
0016
0016
? 0
0016
FF16
0716
FF16
0716
0016
0016
?
?
?
0 0
0016
1 1
0016
0016
0016
0016
?
?
?
?
?
?
?
?
?
0
?
?
b7
Access characteristics
b0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
0
0
?
1
0
0
RW
RW
RW
CK0
RW
RW
RW
7220 Group User’s Manual
RW
RW
6-23
APPENDIX
6.6 SFR assignment
■2 Page Register Area (addresses 21716 to 21B16)
< Bit allocation >
:
Function bit
Name
:
: No function bit
0 : Fix this bit to “0”
(do not write “1”)
Address
21716
21816
21916
21A16
21B16
Register
1 : Fix this bit to “1”
(do not write “0”)
Bit allocation
b0
b7
ROM correction address 1 (high-order)
ROM correction address 1 (low-order)
ADH17 ADH16 ADH15 ADH14 ADH13 ADH12 ADH11 ADH10
ROM correction address 2 (high-order)
ADH27 ADH26 ADH25 ADH24 ADH23 ADH22 ADH21 ADH20
ROM correction address 2 (low-order)
ROM correction enable register (RCR)
ADL27 ADL26 ADL25 ADL24 ADL23 ADL22 ADL21 ADL20
ADL17 ADL16 ADL15 ADL14 ADL13 ADL12 ADL11 ADL10
0
0
RCR1 RCR0
Note: Only M37221M8-XXXSP and M37221MA-XXXSP have this area.
Fig. 6.6.3 Memory map of 2 page register (including internal state immediately after reset and access characteristics) (3)
(only M37221M8-XXXSP and M37221MA-XXXSP)
6-24
7220 Group User’s Manual
APPENDIX
6.6 SFR assignment
< State immediately after reset >
0 : “0” immediately after reset
1 : “1” immediately after reset
RW : Read enabled, write enabled
? : Undefined immediately
after reset
RO : Read enabled, write disabled
Access characteristics
State immediately after reset
b0
b7
b0
b7
RW
RW
RW
RW
?
?
?
?
0016
RW
7220 Group User’s Manual
6-25
APPENDIX
6.6 SFR assignment
■SFR Area (addresses C016 to DF16)
< Bit allocation >
:
Function bit
Name
:
: No function bit
0 : Fix this bit to “0”
(do not write “1”)
1 : Fix this bit to “1”
(do not write “0”)
Address
C016
C116
C216
C316
C416
C516
C616
C716
C816
C916
CA16
CB16
CC16
CD16
CE16
CF16
D016
D116
D216
D316
D416
D516
D616
D716
D816
D916
DA16
DB16
DC16
DD16
DE16
DF16
Register
Bit allocation
b7
b0
Port P0 (P0)
Port P0 direction register (D0)
Port P1 (P1)
Port P1 direction register (D1)
Port P2 (P2)
Port P2 direction register (D2)
Port P3 (P3)
Port P3 direction register (D3)
Port P5 (P5)
Port P5 direction register (D5)
DA2S DA1S P31S P30S
Port P3 output mode control register (P3S)
DA-H register (DA-H)
DA-L register (DA-L)
PWM0 register (PWM0)
PWM1 register (PWM1)
PWM2 register (PWM2)
PWM3 register (PWM3)
PWM4 register (PWM4)
PWM output control register 1 (PW)
PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0
PN4 PN3 PN2
PWM output control register 2 (PN)
Serial I/O mode register (SM)
Serial I/O regsiter (SIO)
DA1 conversion register (DA1)
DA2 conversion register (DA2)
SM6 SM5
0
0
0
SM3 SM2 SM1 SM0
DA15 DA14 DA13 DA12 DA11 DA10
DA25 DA24 DA23 DA22 DA21 DA20
Fig. 6.6.4 SFR assignment (including internal state immediately after reset and access characteristics) (4)
(M37220M3-XXXSP/FP)
6-26
7220 Group User’s Manual
APPENDIX
6.6 SFR assignment
< State immediately after reset >
0 : “0” immediately after reset
RW : Read enabled, write enabled
1 : “1” immediately after reset
RO : Read enabled, write disabled
? : Undefined immediately
after reset
State immediately after reset
b7
0
0
0
0
0
0
0
0
0
0
0
?
?
?
?
?
0016
?
0016
?
0016
? ?
0016
?
?
? ?
0016
?
0016
?
? ?
?
?
?
?
?
0016
0016
?
?
?
?
?
0016
?
? ?
? ?
b0
b7
Access characteristics
b0
RW
RW
RW
RW
RW
RW
?
?
RW
?
RW
?
?
RW
RW
?
RW
RW
?
?
RW
?
RW
RW
RW
RW
RW
RW
RW
RW
?
?
?
?
?
?
7220 Group User’s Manual
RW
RW
RW
RW
6-27
APPENDIX
6.6 SFR assignment
■SFR Area (addresses E016 to FF16)
< Bit allocation >
:
Name
Function bit
:
: No function bit
0 : Fix this bit to “0”
(do not write “1”)
1 : Fix this bit to “1”
(do not write “0”)
Address
E016
E116
E216
E316
E416
E516
E616
E716
E816
E916
EA16
EB16
EC16
ED16
EE16
EF16
F016
F116
F216
F316
F416
F516
F616
F716
F816
F916
FA16
FB16
FC16
FD16
FE16
FF16
Register
Bit allocation
b7
b0
Horizontal position register (HR)
HR5 HR4 HR3 HR2 HR1 HR0
Vertical position register 1 (CV1)
Vertical position register 2 (CV2)
CV16 CV15 CV14 CV13 CV12 CV11 CV10
CV26 CV25 CV24 CV23 CV22 CV21 CV20
CS21 CS20 CS11 CS10
Character size register (CS)
Border selection register (MD)
Color register 0 (CO0)
CO05
CO03 CO02 CO01
Color register 1 (CO1)
CO15
CO13 CO12 CO11
Color register 2 (CO2)
CO25
CO23 CO22 CO21
Color register 3 (CO3)
CRT control register (CC)
CO35
CO33 CO32 CO31
CRT port control register (CRTP)
CRT clock selection register (CK)
MD20
MD10
CC2 CC1 CC0
OP7 OP6 OP5 OUT
0
0
0
0
R/G/B VSYC HSYC
0
ADM4
A-D control register 1 (AD1)
A-D control register 2 (AD2)
Timer 1 (TM1)
0
CK1 CK0
ADM2 ADM1 ADM0
ADC5 ADC4 ADC3 ADC2 ADC1 ADC0
Timer 2 (TM2)
Timer 3 (TM3)
Timer 4 (TM4)
Timer 12 mode register (T12M)
0
T12M4 T12M3 T12M2 T12M1 T12M0
T34M5 T34M4 T34M3 T34M2 T34M1 T34M0
Timer 34 mode register (T34M)
PWM5 register (PWM5)
Interrupt input polarity register (RE)
Test register (TEST)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
0
1
RE5 RE4
CK0 RE3
1
IT3R
1
0
0
CM2
0
0
VSCR CRTR TM4R TM3R TM2R TM1R
0
S1R 1T2R 1T1R
MSR
CK0
IT3E
0
0016
1 1
VSCE CRTE TM4E TM3E TM2E TM1E
0
0
MSE
0
S1E 1T2E 1T1E
Fig. 6.6.5 SFR assignment (including internal state immediately after reset and access characteristics) (5)
(M37220M3-XXXSP/FP)
6-28
7220 Group User’s Manual
APPENDIX
6.6 SFR assignment
< State immediately after reset >
0 : “0” immediately after reset
RW : Read enabled, write enabled
1 : “1” immediately after reset
RO : Read enabled, write disabled
? : Undefined immediately
after reset
State immediately after reset
b7
b0
0
0
?
?
?
?
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0016
? ?
? ?
?
0 ?
0 0
0016
0016
0016
0016
0016
?
0016
0016
? 0
0016
FF16
0716
FF16
0716
0016
0016
?
?
?
0 0
0016
1 1
0016
0016
0016
0016
?
?
?
?
?
?
?
?
?
0
?
?
b7
Access characteristics
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
0
b0
RW
RW
RW
0
RW
RW
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
0
0
?
1
0
0
RW
RW
RW
RW
CK0
RW
RW
RW
7220 Group User’s Manual
RW
RW
RW
6-29
APPENDIX
6.7 Control registers
6.7 Control registers
Port Pi Direction Register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (Di) (i=0,1,2) [Addresses 00C116, 00C316, 00C516]
B
0
Name
Functions
After reset R W
0 : Port Pi0 input mode
1 : Port Pi0 output mode
0
R W
1
0 : Port Pi1 input mode
1 : Port Pi1 output mode
0
R W
2
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0
R W
3
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0
R W
4
0 : Port Pi4 input mode
1 : Port Pi4 output mode
0
R W
5
0 : Port Pi5 input mode
1 : Port Pi5 output mode
0
R W
6
0 : Port Pi6 input mode
1 : Port Pi6 output mode
0
R W
7
0 : Port Pi7 input mode
1 : Port Pi7 output mode
0
R W
Port Pi direction register
Fig. 6.7.1 Port Pi direction register
Addresses 00C116, 00C316, 00C516
Port P3 Direction Register
b7 b6 b5 b4 b3 b2 b1 b0
Port P3 direction register (D3) [Address 00C716]
B
Name
Functions
After reset R W
0 : Port P30 input mode
1 : Port P30 output mode
0
R W
1
0 : Port P31 input mode
1 : Port P31 output mode
0
R W
2
0 : Port P32 input mode
1 : Port P32 output mode
0
R W
0
R —
0
3
to
7
Port P3 direction register
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
Fig. 6.7.2 Port P3 direction register
Address 00C716
6-30
7220 Group User’s Manual
APPENDIX
6.7 Control registers
Port P5 Direction Register
b7 b6 b5 b4 b3 b2 b1 b0
Port P5 direction register (D5) [Address 00CB16 ]
B
Name
Functions
0, 1 Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
After reset R W
0
R —
0 : CRT output (R)
1 : Output port P5 2
0
R W
0 : CRT output (G)
1 : Output port P5 3
0
R W
0 : CRT output (B)
1 : Output port P5 4
0
R W
0 : CRT output (OUT1)
1 : Output port P5 5
0
R W
6, 7 Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
0
R —
2
to
5
Port P5 direction register
Fig. 6.7.3 Port P5 direction register
Address 00CB 16
Port P3 output mode control register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Port P3 output mode control register (P3S) [address 00CD16]
B
Name
Functions
After reset R W
0
P30 output structure
selection bit (P30S)
0 : CMOS output
1 : N-channel open-drain output
0
R W
1
P31 output structure
selection bit (P31S)
0 : CMOS output
1 : N-channel open-drain output
0
R W
0
R W
0
R —
2, 3 Fix thes bits to “0.”
4
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
(See note)
Note: M37220M3-XXXSP/FP
2
DA1 output enable bit
0 : P3 0 input/output
1 : DA1 output
0
R W
3
DA2 output enable bit
0 : P3 1 input/output
1 : DA2 output
0
R W
Fig. 6.7.4 Port P3 output mode control register
Address 00CD 16
7220 Group User’s Manual
6-31
APPENDIX
6.7 Control registers
PWM Output Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
PWM output control register 1 (PW) [Address 00D516]
B
Name
Functions
0 DA, PWM count source 0 : Count source supply
1 : Count source stop
selection bit (PW0)
After reset R W
R W
0
1
DA/PN4 output
selection bit (PW1)
0 : DA output
1 : PN4 output
0
R W
2
P00/PWM0 output
selection bit (PW2)
0: P00 output
1: PWM0 output
0
R W
3
P01/PWM1 output
selection bit (PW3)
0: P01 output
1: PWM1 output
0
R W
4
P02/PWM2 output
selection bit (PW4)
0: P02 output
1: PWM2 output
0
R W
5
P03/PWM3 output
selection bit (PW5)
0: P03 output
1: PWM3 output
0
R W
6
P04/PWM4 output
selection bit (PW6)
0: P04 output
1: PWM4 output
0
R W
7
P05/PWM5 output
selection bit (PW7)
0: P05 output
1: PWM5 output
0
R W
Fig. 6.7.5 PWM output control register 1
Address 00D516
PWM Output Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
PWM output control register 2 (PN) [Address 00D6 16]
B
Name
Functions
After reset R W
0, 1 Nothing is assigned. These bits are write disable bits.
0
R —
When these bits are read out, the values are “0.”
2
DA output polarity
selection bit (PN3)
0 : Positive polarity
1 : Negative polarity
0
R W
3
PWM output polarity
selection bit (PN4)
0 : Positive polarity
1 : Negative polarity
0
R W
4
DA general-purpose
output bit (PN5)
0 : Output LOW
1 : Output HIGH
0
R W
0
R —
5 Nothing is assigned. These bits are write disable bits.
to When these bits are read out, the values are “0.”
7
Fig. 6.7.6 PWM output control register 2
Address 00D616
6-32
7220 Group User’s Manual
APPENDIX
6.7 Control registers
I2C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
2
I C data shift register (S0) [Address 00D716]
B
0
to
7
Name
Functions
D0 to D7
This is an 8-bit shift register to store
receive data and write transmit data.
After reset
R W
Indeterminate R W
Note: To write data into the I2C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
Fig. 6.7.7 I 2C data shift register
Address 00D716
I2C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C address register (S0D) [Address 00D816]
B
Name
Functions
After reset R W
0
Read/write bit
(RBW)
0: Read
1: Write
0
R W
1
to
7
Slave address
(SAD0 to SAD6)
The address data transmitted from
the master is compared with the
contents of these bits.
0
R W
Fig. 6.7.8 I2C address register
Address 00D816
7220 Group User’s Manual
6-33
APPENDIX
6.7 Control registers
I2C Status Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address 00D916]
B
Name
Functions
0
Last receive bit (LRB)
(See note)
0 : Last bit = “0 ”
1 : Last bit = “1 ”
1
General call detecting flag
(AD0) (See note)
2
After reset R W
Indeterminate
R —
0 : No general call detected
1 : General call detected
0
R —
Slave address comparison
flag (AAS) (See note)
0 : Address mismatch
1 : Address match
0
R —
3
Arbitration lost detecting flag
(AL) (See note)
0 : Not detected
1 : Detected
0
R —
4
I2C-BUS interface interrupt
request bit (PIN)
0 : Interrupt request issued
1 : No interrupt request issued
1
R W
5
Bus busy flag (BB)
0 : Bus free
1 : Bus busy
0
R W
b7
0
0
1
1
0
R W
6, 7 Communication mode
specification bits
(TRX, MST)
b6
0 : Slave recieve mode
1 : Slave transmit mode
0 : Master recieve mode
1 : Master transmit mode
Note : These bits and flags can be read out, but cannnot be written.
Fig. 6.7.9 I2C status register
Address 00D916
6-34
7220 Group User’s Manual
APPENDIX
6.7 Control registers
I2C Control Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C control register (S1D : address 00DA 16)
B
Name
Functions
0
to
2
Bit counter
(Number of transmit/recieve
bits)
(BC0 to BC2)
b2
0
0
0
0
1
1
1
1
3
I2 C-BUS interface use
enable bit (ESO)
4
5
0
R W
0 : Disabled
1 : Enabled
0
R W
Data format selection bit
(ALS)
0 : Addressing mode
1 : Free data format
0
R W
Addressing format selection
bit (10BIT SAD)
0 : 7-bit addressing format
1 : 10-bit addressing format
0
R W
b7 b6 Connection port
0 0 : None
0 1 : SCL1, SDA1
1 0 : SCL2, SDA2
1 1 : SCL1, SDA1
SCL2, SDA2
0
R W
6, 7 Connection control bits
between I2C-BUS interface
and ports
(BSEL0, BSEL1)
b1
0
0
1
1
0
0
1
1
b0
0:
1:
0:
1:
0:
1:
0:
1:
After reset R W
8
7
6
5
4
3
2
1
Note: When using ports P1 1 -P14 as I2C-BUS interface, the output structure changes
automatically from CMOS output to N-channel open-drain output. However, set
the port direction register to “1” (output mode).
Fig. 6.7.10 I 2C control register
Address 00DA 16
7220 Group User’s Manual
6-35
APPENDIX
6.7 Control registers
I2C Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0
I2 C clock control register (S2 : address 00DB 16)
B
0
to
4
Name
Functions
SCL frequency control bits Setup value of Standard clock
(CCR0 to CCR4)
CCR4–CCR0
mode
00 to 02
After reset R W
High speed
clock mode
0
R W
Setup disabled Setup disabled
03
Setup disabled
04
Setup disabled
333
250
05
100
400 (See note)
06
83.3
166
...
500/CCR value
1000/CCR value
1D
17.2
34.5
1E
16.6
33.3
1F
16.1
32.3
(at φ = 4 MHz, unit : kHz)
5
SCL mode
specification bit
(FAST MODE)
0 : Standard clock mode
1 : High-speed clock mode
0
R W
6
ACK bit
(ACK BIT)
0 : ACK is returned.
1 : ACK is not returned.
0
R W
7
ACK clock bit
(ACK)
0 : No ACK clock
1 : ACK clock
0
R W
Note: At 4000kHz in the high-speed clock mode, the duty is as below .
“0” period : “1” period = 3 : 2
In the other cases, the duty is as below.
“0” period : “1” period = 1 : 1
Fig. 6.7.11 I 2C clock contorol register
Address 00DB 16
6-36
7220 Group User’s Manual
APPENDIX
6.7 Control registers
Serial I/O Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Serial I/O mode register (SM) [Address 00DC 16]
B
Name
0, 1 Internal synchronous
clock selection bits
(SM0, SM1)
Functions
b1
0
0
1
1
b0
0: f(X IN)/4
1: f(X IN)/16
0: f(X IN)/32
1: f(X IN)/64
After reset R W
R W
0
2
Synchronous clock
selection bit (SM2)
0: External clock
1: Internal clock
0
R W
3
Serial I/O port
selection bit (SM3)
0: P2 0, P2 1 functions
as port
1: S CLK, SOUT
0
R W
4
Fix this bit to “0.”
0
R W
5
Transfer direction
selection bit (SM5)
0: LSB first
1: MSB first
0
R W
6
Serial input pin
selection bit (SM6)
0: Input signal from S IN pin
1: Input signal from S OUT pin
0
R W
7
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
0
R —
Fig. 6.7.12 Serial I/O mode register
Address 00DC 16
7220 Group User’s Manual
6-37
APPENDIX
6.7 Control registers
DA n Conversion Register
b7 b6 b5 b4 b3 b2 b1 b0
0
DA n conversion register (DAn) (n = 1 and 2) [Address 00DE16, 00DF 16]
B
Name
0 DA conversion set
to bits
5 (DAn0–DAn5)
Functions
b5
0
0
0
b4
0
0
0
b3
0
0
0
b2
0
0
0
b1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
After reset
b0
0 : 0/64Vcc
1 : 1/64Vcc
0 : 2/64Vcc
R W
Indeterminate R W
1 : 61/64Vcc
0 : 62/64Vcc
1 : 63/64Vcc
6 Fix this bit to “0.”
0
R —
7
0
R —
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “ 0.”
Fig. 6.7.13 DA n conversion register (only M37220M3-XXXSP/FP)
Addresses 00DE16, 00DF 16
Horizontal Position Register
b7 b6 b5 b4 b3 b2 b1 b0
Horizontal position register (HR) [Address 00E016 ]
B
0
to
5
Name
Horizontal display start
positions (HR0 to HR5)
Functions
64 steps (0016 to 3F16)
6, 7 Nothing is assigned. These bits are write disable bits.
When thses bits are read out, the values are “0.”
After reset
R W
0
R W
0
R —
Fig. 6.7.14 Horizontal position register
Address 00E0 16
6-38
7220 Group User’s Manual
APPENDIX
6.7 Control registers
Vertical Position Register n
b7 b6 b5 b4 b3 b2 b1 b0
Vertical position register n (CV1,CV2) (n = 1 and 2) [Addresses 00E1 16, 00E216]
B
Name
Functions
0
to
6
Vertical display start positions
(CV1 : CV10 to CV16)
(CV2 : CV20 to CV26)
7
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
After reset
128 steps (00 16 to 7F16 )
R W
Indeterminate R W
0
R —
Fig. 6.7.15 Vertical position register n
Addresses 00E1 16, 00E216
Character Size Register
b7 b6 b5 b4 b3 b2 b1 b0
Character size register (CS) [Address 00E416]
B
Name
Functions
After reset
R W
0, 1 Character size of block 1
selection bits
(CS10, CS11)
00 : Minimum size
01 : Medium size
10 : Large size
11 : Do not set.
Indeterminate R W
2,3 Character size of block 2
selection bits
(CS20,CS21)
00 : Minimum size
01 : Medium size
10 : Large size
11 : Do not set.
Indeterminate R W
4
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
0
R —
Fig. 6.7.16 Character size register
Address 00E416
7220 Group User’s Manual
6-39
APPENDIX
6.7 Control registers
Border Selection Register
b7 b6 b5 b4 b3 b2 b1 b0
Border selection register (MD) [Address 00E5 16]
B
Name
Functions
0
Block 1 OUT1 output
0 : Same output as character output
border selection bit (MD10) 1 : Border output
1
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
2
Block 1 OUT1 output
0 : Same output as character output
border selection bit (MD20) 1 : Border output
3
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
After reset
R W
Indeterminate R W
0
R —
Indeterminate R W
0
(See note)
(See note)
R —
Note : M37220M3-XXXSP/FP
0
Block 1 OUT output
0 : Same output as character output
border selection bit (MD10) 1 : Border output
Indeterminate R W
2
0 : Same output as character output
Block 2 OUT output
border selection bit (MD20) 1 : Border output
Indeterminate R W
Fig. 6.7.17 Border selection register
Address 00E5 16
6-40
7220 Group User’s Manual
APPENDIX
6.7 Control registers
Color Register n
b7 b6 b5 b4 b3 b2 b1 b0
Color register n (CO0 to CO3) (n = 0 to 3) [Addresses 00E616 to 00E9 16]
B
Name
Functions
After reset R W
0
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
0
R —
1
B signal output
selection bit (COn1)
0 : No character is output
1 : Character is output
0
R W
2
G signal output
selection bit (COn2)
0 : No character is output
1 : Character is output
0
R W
3
R signal output
selection bit (COn3)
0 : No character is output
1 : Character is output
0
R W
4
B signal output (background) 0 : No background color is output
1 : Background color is output (See note 1)
selection bit (COn4)
0
R W
5
OUT1 signal output
control bit (COn5)
0
R W
0 : Character is output
1 : Blank is output
(See notes 1, 2)
6
G signal output (background) 0 : No background color is output
selection bit (COn6)
1 : Background color is output
0
R W
7
R signal output (background) 0 : No background color is output
1 : Background color is output (See note 2)
selection bit (COn7)
0
R W
(See note 3)
Notes 1: When bit 5 = “0” and bit 4 = “1,” there is output same as a character or border output
from the OUT1 pin.
Do not set bit 5 = “0” and bit 4 = “0.”
2: When only bit 7 = “1” and bit 5 = “0,” there is output from the OUT2 pin.
3: M37220M3-XXXSP/FP
4
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
0
R —
5
OUT signal output
control bit (COn5)
0
R W
0
R —
0 : Character is output
1 : Blank is output
6, 7 Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
Fig. 6.7.18 Color register n
Addresses 00E6 16 to 00E916
7220 Group User’s Manual
6-41
APPENDIX
6.7 Control registers
CRT Control Register
b7 b6 b5 b4 b3 b2 b1 b0
CRT control register (CC) [Address 00EA16]
B
Functions
Name
After reset R W
0
R W
0
All-blocks display control
bit (Note 1) (CC0)
0 : All-blocks display off
1 : All-blocks display on
1
Block 1 display control bit
(CC1)
0 : Block 1 display off
1 : Block 1 display on
0
R W
2
Block 2 display control bit
(CC2)
0 : Block 2 display off
1 : Block 2 display on
0
R W
3
to
6
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
0
R —
7
P10 /OUT2 pin switch bit
(CC7)
0
R W
0 : P10
1 : OUT2
(See note 2)
Notes 1: Display is controlled by logical product (AND) between the all-blocks display
control bit and each block control bit.
2 : M37220M3-XXXSP/FP
7
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
0
R —
Fig. 6.7.19 CRT control register
Address 00EA 16
6-42
7220 Group User’s Manual
APPENDIX
6.7 Control registers
CRT Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0
CRT port control register (CRTP) [Address 00EC16]
B
Name
Functions
After reset R W
0
HSYNC input polarity
switch bit (HSYC)
0 : Positive polarity
1 : Negative polarity
0
R W
1
VSYNC input polarity
switch bit (VSYC)
0 : Positive polarity
1 : Negative polarity
0
R W
2
R, G, B output polarity
switch bit (R/G/B)
0 : Positive polarity
1 : Negative polarity
0
R W
3
OUT2 output polarity
switch bit (OUT2)
0 : Positive polarity
1 : Negative polarity
0
R W
4
OUT1 output polarity
switch bit (OUT1)
0 : Positive polarity
1 : Negative polarity
0
R W
5
R signal output switch bit
(OP5)
0 : R signal output
1 : MUTE signal output
0
R W
6
G signal output switch bit
(OP6)
0 : G signal output
1 : MUTE signal output
0
R W
7
B signal output switch bit
(OP7)
0 : B signal output
1 : MUTE signal output
0
R W
(See note)
Note : M37220M3-XXXSP/FP
3
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
0
R —
4
OUT output polarity
switch bit (OUT)
0
R W
0 : Positive polarity
1 : Negative polarity
Fig. 6.7.20 CRT port control register
Address 00EC16
7220 Group User’s Manual
6-43
APPENDIX
6.7 Control registers
CRT Clock Selection Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
0
0
CRT clock selection register (CK) [Address 00ED16 ]
B
Name
0, 1 CRT clock
selection bits
(CK0,CK1)
Functions
b1 b0
1
0 The clock for display is supplied by connecting RC
or LC across the pins OSC1 and OSC2.
0
1 Since the main clock is used as the clock for CRT oscillation
display, the oscillation frequency is limited.
frequency
Because of this, the character size in width = f(X IN)
(horizontal) direction is also limited. In this
0 case, pins OSC1 and OSC2 are also used
CRT oscillation
frequency
as input ports P33 and P34 respectively.
= f(XIN )/1.5
1
1
2
to
7
Functions
After reset R W
0
R W
0
R W
1 The clock for display is supplied by connecting the
following across the pins OSC1 and OSC2.
• a ceramic resonator only for CRT display and a feedback resistor
• a quartz-crystal oscillator only for CRT display and a feedback
resistor (Note)
Fix these bits to “0.”
Note: It is necessary to connect other ceramic resonator or quartz-crystal oscillator across the pins XIN and X OUT .
Fig. 6.7.21 CRT clock selection register
Address 00ED 16
6-44
7220 Group User’s Manual
APPENDIX
6.7 Control registers
A-D Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 1 (AD1) [Address 00EE 16]
B
Name
Functions
0
to
2
Analog input pin selection
bits
(ADM0, ADM1, ADM2)
b2
0
0
0
0
1
1
1
1
b1
0
0
1
1
0
0
1
1
3
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
4
Storage bit of comparison
result (ADM4)
5
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
After reset R W
b0
0 : A-D1
1 : A-D2
0 : A-D3
1 : A-D4
0 : A-D5
1 : A-D6
0 : Do not set.
1:
0: Input voltage < reference voltage
1: Input voltage > reference voltage
0
R W
0
R —
Indeterminate
R W
0
R —
Fig. 6.7.22 A-D control register 1
Address 00EE 16
A-D Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 2(AD2) [Address 00EF 16]
B
0
to
5
Name
D-A converter set bits
(ADC0, ADC1, ADC2,
ADC3, ADC4, ADC5)
Functions
b5
0
0
0
b4
0
0
0
b3
0
0
0
b2
0
0
0
b1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
b0
0 : 1/128Vcc
1 : 3/128Vcc
0 : 5/128Vcc
After reset
R W
0
R W
0
R —
1 : 123/128Vcc
0 : 125/128Vcc
1 : 127/128Vcc
6, 7 Nothing is assigned. These bits are write disable bits.
When these bits are reed out, the values are “ 0.”
Fig. 6.7.23 A-D control register 2
Address 00EF 16
7220 Group User’s Manual
6-45
APPENDIX
6.7 Control registers
Timer 12 Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Timer 12 mode register (T12M) [Address 00F4 16]
After reset R W
0
R W
B
Name
0 Timer 1 count source
selection bit (T12M0)
Functions
0: f(XIN)/16
1: f(XIN)/4096
1
Timer 2 count source
selection bit
(T12M1)
0: Internal clock
1: External clock from
P24/TIM2 pin
0
R W
2
Timer 1 count
stop bit (T12M2)
Timer 2 count stop
bit (T12M3)
0: Count start
1: Count stop
0: Count start
1: Count stop
0: f(XIN)/16
1: Timer 1 overflow
0
R W
0
R W
0
R W
0
R W
0
R —
3
4
Timer 2 internal count
source selection bit
(T12M4)
5
Fix this bit to “0.”
6,7 Nothing is assigned. These bits are write disable
bits. When these bits are read out, the values are
“0.”
Fig. 6.7.24 Timer 12 mode register
Address 00F416
6-46
7220 Group User’s Manual
APPENDIX
6.7 Control registers
Timer 34 Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 34 mode register (T34M) [Address 00F516]
B
Name
0 Timer 3 count source
selection bit (T34M0)
Functions
0: f(XIN)/16
1: External clock
After reset R W
0
R W
1
Timer 4 internal count
source selection bit
(T34M1)
0: Timer 3 overflow
1: f(X IN)/16
0
R W
2
Timer 3 count
stop bit (T34M2)
0: Count start
1: Count stop
0
R W
3
Timer 4 count stop
bit (T34M3)
0: Count start
1: Count stop
0
R W
4
Timer 4 count source
selection bit (T34M4)
0: Internal clock
1: f(XIN)/2
0
R W
5
Timer 3 external count
0: External clock from P2 3/TIM3 pin
source selection bit (T34M5) 1: External clock from H SYNC pin
0
R W
0
R —
6,7 Nothing is assigned. These bits are write disable
bits. When these bits are read out, the values are
“0.”
Fig. 6.7.25 Timer 34 mode register
Address 00F516
Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
Interrupt input polarity register(RE) [Address 00F9 16 ]
b
0
Name
Functions
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
1, 2 Fix these bits to “0.”
After reset
R W
Indeterminate
R —
0
R W
3
INT1 polarity switch bit
(RE3)
0 : Positive polarity
1 : Negative polarity
0
R W
4
INT2 polarity switch bit
(RE4)
0 : Positive polarity
1 : Negative polarity
0
R W
5
INT3 polarity switch bit
(RE5)
0 : Positive polarity
1 : Negative polarity
0
R W
6
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
0
R —
7
Fix this bit to “0.”
0
R W
Fig. 6.7.26 Interrupt input polarity register
Address 00F916
7220 Group User’s Manual
6-47
APPENDIX
6.7 Control registers
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1 1 1 1 1
0 0
CPU mode register (CPUM) (CM) [Address 00FB16]
B
Name
0, 1 Fix these bits to “0.”
2
Stack page selection
bit (CM2)
Functions
0: 0 page
1: 1 page
(Note)
3 Fix these bits to “1.”
to
5
After reset
R W
0
R W
1
R W
1
R W
Indeterminate R W
6, 7
Note: This bit is set to “1” after reset release.
Fig. 6.7.27 CPU mode register
Address 00FB16
Interrupt Request Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address 00FC16]
B
0
1
2
3
4
5
6
7
Name
Functions
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
Multi-master I 2C-BUS interface 0 : No interrupt request issued
interrupt request bit (IICR) 1 : Interrupt request issued
INT3 interrupt
0 : No interrupt request issued
request bit (IT3R)
1 : Interrupt request issued
Timer 1 interrupt
request bit (TM1R)
Timer 2 interrupt
request bit (TM2R)
Timer 3 interrupt
request bit (TM3R)
Timer 4 interrupt
request bit (TM4R)
CRT interrupt
request bit (CRTR)
V SYNC interrupt
request bit (VSCR)
After reset R W
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R ✽
0
R —
(See note)
✽: “0” can be set by software, but “1” cannot be set.
Note : M37220M3-XXXSP/FP
6
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
Fig. 6.7.28 Interrupt request register 1
Address 00FC16
6-48
7220 Group User’s Manual
APPENDIX
6.7 Control registers
Interrupt Request Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt request register 2 (IREQ2) [Address 00FD16]
B
Name
Functions
After reset R W
INT1 interrupt
0 : No interrupt request issued
request bit (ITIR)
1 : Interrupt request issued
1 INT2 interrupt
0 : No interrupt request issued
request bit (IT2R)
1 : Interrupt request issued
0 : No interrupt request issued
2 Serial I/O interrupt
request bit (S1R)
1 : Interrupt request issued
3 Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
4 f(XIN)/4096 interrupt 0 : No interrupt request issued
request bit (MSR)
1 : Interrupt request issued
5, 6 Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
7 Fix this bit to “0.”
0
0
R ✽
0
R ✽
0
R ✽
0
R —
0
R ✽
0
R —
0
R W
✽: “0” can be set by software, but “1” cannot be set.
Fig. 6.7.29 Interrupt request register 2
Address 00FD16
Interrupt Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address 00FE16]
B
Name
0
Timer 1 interrupt
enable bit (TM1E)
1
Timer 2 interrupt
enable bit (TM2E)
Timer 3 interrupt
enable bit (TM3E)
Timer 4 interrupt
enable bit (TM4E)
2
3
4
5
6
7
CRT interrupt enable
bit (CRTE)
VSYNC interrupt
enable bit (VSCE)
Multi-master I 2C-BUS interface
interrupt enable bit (IICE)
INT3 interrupt
enable bit (IT3E)
Functions
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
After reset R W
0
R W
0
R W
0
R W
0
R W
0
R W
0
R W
0
R W
0
R W
0
R —
(See note)
Note : M37220M3-XXXSP/FP
6
Nothing is assigned. This bit is a write disable
bit. When this bit is read out, the value is “0.”
Fig. 6.7.30 Interrupt control register 1
Address 00FE16
7220 Group User’s Manual
6-49
APPENDIX
6.7 Control registers
Interrupt Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
0
Interrupt control register 2 (ICON2) [Address 00FF 16]
B
Name
0
INT1 interrupt
enable bit (IT1E)
INT2 interrupt enable
bit (IT2E)
Serial I/O interrupt
enable bit (S1E)
Fix this bit to “0.”
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
f(XIN)/4096 interrupt
enable bit (MSE)
Fix these bits to “0.”
0 : Interrupt disabled
1 : Interrupt enabled
1
2
3
4
5
to
Functions
After reset R W
0
R W
0
R W
0
R W
0
R W
0
R W
0
R W
7
Fig. 6.7.31 Interrupt control register 2
Address 00FF 16
ROM correction enable register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
ROM correction enable register (RCR) [Address 021216]
B
Name
0
Block 1 enable bit (RCR0)
1
Block 2 enable bit (RCR1)
Functions
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
2, 3 Fix these bits to “0.”
4
to
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
After reset R W
0
0
0
✕
0
✕
7
Fig. 6.7.32 ROM correction enable register
Address 0212 16
6-50
7220 Group User’s Manual
APPENDIX
6.8 Ports
6.8 Ports
P00/PWM0–P0 5/PWM5, P3 2
N-channel open-drain output
Data bus
Direction register
Port latch
●M37221M4-XXXSP, M37221M6-XXXSP/FP, M37221M8-XXXSP, M37221MA-XXXSP
P10/OUT2, P1 1/SCL1, P1 2/SCL2, P1 3/SDA1, P1 4/SDA2, P1 5/A-D1/INT3, P1 6/A-D2, P1 7/A-D3,
P20/S CLK, P21/S OUT, P22/SIN, P23/TIM3, P2 4/TIM2, P2 5–P27, P30/A-D5, P3 1/A-D6 (See notes 1, 2)
●M37220M3-XXXSP/FP
P10–P1 4, P15/A-D/INT3, P1 6/A-D2, P1 7/A-D3, P2 0/SCLK, P21/SOUT , P22/S IN,
P23/TIM3, P2 4/TIM2, P2 5–P27, P30/A-D5/DA1, P3 1/A-D6/DA2 (See note 2)
Direction register
CMOS output
Data bus
Port latch
Notes 1 : When ports P1 1–P14 are used as multi-master I 2 C-BUS interface pin and when ports P2 0, P21 are used as
serial I/O output pins, their output structure is N-channel open-drain output.
2 : For the output structure of ports P3 0, P31, either CMOS output or N-channel open-drain output is selected
(In the case of N-channel open-drain output, the block diagram is the same as below).
P06/INT2/A-D4, P0 7/INT1
N-channel open-drain output
Data bus
Direction register
Port latch
indicates a pin.
Fig. 6.8.1 I/O pin block diagram (1)
7220 Group User’s Manual
6-51
APPENDIX
6.8 Ports
P33/OSC1, P3 4
Input
Internal circuit
●M37221M4-XXXSP, M37221M6-XXXSP/FP, M37221M8-XXXSP, M37221MA-XXXSP
D-A, P5 2/R, P5 3/G, P5 4/B, P5 5/OUT1
●M37220M3-XXXSP/FP
D-A, P5 2/R, P5 3/G, P5 4/B, P5 5/OUT
CMOS output
Internal circuit
HSYNC , VSYNC
Schmidt input
H SYNC or
VSYNC
indicates a pin.
Fig. 6.8.2 I/O pin block diagram (2)
6-52
7220 Group User’s Manual
APPENDIX
6.9 Machine instruction table
6.9 Machine instruction table
Machine instructions
7220 Group User’s Manual
6-53
APPENDIX
6.9 Machine instruction table
6-54
7220 Group User’s Manual
APPENDIX
6.9 Machine instruction table
7220 Group User’s Manual
6-55
APPENDIX
6.9 Machine instruction table
6-56
7220 Group User’s Manual
APPENDIX
6.9 Machine instruction table
7220 Group User’s Manual
6-57
APPENDIX
6.9 Machine instruction table
6-58
7220 Group User’s Manual
APPENDIX
6.9 Machine instruction table
7220 Group User’s Manual
6-59
APPENDIX
6.9 Machine instruction table
6-60
7220 Group User’s Manual
APPENDIX
6.9 Machine instruction table
7220 Group User’s Manual
6-61
APPENDIX
6.9 Machine instruction table
6-62
7220 Group User’s Manual
APPENDIX
6.10 Instruction code table
6.10 Instruction code table
D3–D0
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
D7 Hexadecimal 0
notation
–D4
0 BRK
0000
1
2
3
4
ORA
6
7
ORA ASL BBS
ORA JSR BBS
IND,X ZP,IND
IND,X
5
0,A
ZP
ZP
0,ZP
ORA ASL BBC
BBC
0001
1
BPL
0010
2
JSR AND JSR BBS
BIT
ABS
ZP
0011
3
BMI
0100
4
RTI
0101
5
BVC
0110
6
RTS
0111
7
BVS
1000
8
BRA
1001
9
BCC
1010
A
LDY LDA LDX BBS LDY LDA LDX BBS
1011
B
BCS
IMM
IND,Y
IND,X
AND
IND,Y
EOR
IND,X
CLT
SP
SET
STP
0,A
1,A
1,A
2,A
EOR
BBC
2,A
3,A
ADC
BBC
IND,Y
3,A
ZP
ZP
1,ZP
ZP,X
ZP,X
1,ZP
ZP
ZP
ZP
2,ZP
EOR LSR BBC
ZP,X
ZP,X
2,ZP
ZP
ZP
ZP
3,ZP
ADC ROR BBC
ZP,X
ZP,X
3,ZP
STA RRF BBS STY STA STX BBS
IND,X
ZP
STA
ZP
ZP
ZP
4,ZP
BBC STY STA STX BBC
IND,Y
IND,X
4,A
4,A
IMM
5,A
ZP,X
ZP
ZP,X
ZP
ZP,X
ZP
4,ZP
5,ZP
LDA JMP BBC LDY LDA LDX BBC
IND,Y ZP,IND
5,A
1101
D
BNE
BBC
IND,Y
6,A
1110
E
CPX SBC
1111
F
BEQ
IND,X
WIT
ZP,X
ZP,X
ZP,Y
5,ZP
BBS CPY CMP DEC BBS
CMP
IMM
AND ROL BBS
BBS TST ADC ROR BBS
IND,X
CPY CMP
IMM
0,ZP
BBS COM EOR LSR BBS
C
1100
ZP,X
AND ROL BBC
BBC
IND,Y
ADC
ZP,X
6,A
ZP
ZP
ZP
6,ZP
CMP DEC BBC
ZP,X
ZP,X
6,ZP
BBS CPX SBC
INC
BBS
ZP
7,ZP
IND,X
7,A
ZP
ZP
SBC
BBC
SBC
INC
BBC
IND,Y
7,A
ZP,X
ZP,X
7,ZP
8
PHP
CLC
PLP
SEC
PHA
CLI
PLA
SEI
9
TAY
CLV
INY
CLD
INX
SED
7220 Group User’s Manual
B
C
D
E
F
ORA ASL SEB
ORA ASL SEB
IMM
ABS
A
0,A
ABS
0,ZP
ORA DEC CLB
ORA ASL CLB
ABS,Y
ABS,X ABS,X 0,ZP
A
0,A
AND ROL SEB
BIT
AND ROL SEB
IMM
ABS
ABS
A
AND INC
ABS,Y
A
1,A
ABS
1,ZP
CLB LDM AND ROL CLB
1,A
ZP
ABS,X ABS,X 1,ZP
EOR LSR SEB JMP EOR LSR SEB
IMM
A
2,A
ABS
ABS
ABS
2,ZP
EOR
CLB
EOR LSR CLB
ABS,Y
2,A
ABS,X ABS,X 2,ZP
ADC ROR SEB JMP ADC ROR SEB
IMM
A
3,A
IND
ABS
ABS
3,ZP
ADC
CLB
ADC ROR CLB
ABS,Y
3,A
ABS,X ABS,X 3,ZP
TXA
DEY
TYA
A
STA
ABS,Y
LDA
IMM
LDA
ABS,Y
CMP
IMM
TXS
TAX
TSX
DEX
SEB STY STA STX SEB
4,A
ABS
ABS
ABS
4,ZP
CLB
STA
CLB
4,A
ABS,X
4,ZP
SEB LDY LDA LDX SEB
5,A
ABS
ABS
ABS
5,ZP
CLB LDY LDA LDX CLB
5,A
ABS,X ABS,X ABS,Y 5,ZP
SEB CPY CMP DEC SEB
6,A
ABS
ABS
ABS
6,ZP
CMP
CLB
CMP DEC CLB
ABS,Y
6,A
ABS,X ABS,X 6,ZP
SBC
IMM
NOP
INC
SEB
ABS
ABS
7,ZP
SBC
INC
CLB
SEB CPX SBC
7,A
SBC
CLB
ABS,Y
7,A
ABS
ABS,X ABS,X 7,ZP
6-63
APPENDIX
6.11 Mask ROM ordering method
6.11 Mask ROM ordering method
When placing an order, please submit the information described below.
➀ M37221M4-XXXSP Mask ROM Ordering Confirmation Form.........1 set
(Please use the pages P6-65 to P6-67)
M27221M8-XXXSP Mask ROM Ordering Confirmation Form.........1 set
(Please use the pages P6-68 to P6-70)
M37221M6-XXXSP/FP Mask ROM Ordering Confirmation Form.........1 set
(Please use the pages P6-71 to P6-73)
M27221MA-XXXSP Mask ROM Ordering Confirmation From.........1 set
(Please use the pages P6-74 to P6-76)
M27220M3-XXXSP/FP Mask ROM Ordering Confirmation From.........1 set
(Please use the pages P6-77 to P6-79)
➁Data to be written to mask ROM.........EPROM (DIP Type 27C101)
(Please provide 3 sets containing the identical data)
➂Mark Specification Form.........1 set
(Please use the pages P6-80 and P6-81)
6-64
7220 Group User’s Manual
APPENDIX
6.11 Mask ROM ordering method
GZZ–SH10–10B < 59B0 >
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37221M4-XXXSP
MITSUBISHI ELECTRIC
Receipt
Date :
Section head
signature
Supervisor
signature
Note : Please fill in all items marked ❈.
Date
issued
Date :
)
Issuance
(
Customer
Supervisor
signature
❈
Submitted by
TEL
Company
name
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on
this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce
differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27C101
EPROM address
000016
Product name
ASCII code :
‘M37221M4 –’
000F16
C000 16
FFFF 16
10000 16
107FF 16
10800 16
10FFF16
11000 16
117FF 16
11800 16
11FFF16
data
ROM 16 K bytes
Character ROM 1-a
Character ROM 2-a
Character ROM 1-b
Character ROM 1-b
1FFFF 16
(1)
(2)
Set “FF 16” in the shaded area.
Write the ASCII codes that indicates the product name of “M37221M4–” to addresses 0000 16 to 000F 16.
EPROM data check item (Refer the EPROM data and check “ ✓” in the appropriate box)
→ Yes
● Do you set “FF 16” in the shaded area ?
● Do you write the ASCII codes that indicates the product
→ Yes
name of “M37221M4–” to addresses 0000 16 to 000F 16 ?
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate
mark specification form (42P4B for M37221M4-XXXSP) and attach to the mask ROM confirmation form.
❈ 3. Comments
(1/3)
7220 Group User’s Manual
6-65
APPENDIX
6.11 Mask ROM ordering method
GZZ–SH10–10B <59B0 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37221M4-XXXSP
MITSUBISHI ELECTRIC
Writing the product name and character ROM data onto EPROMs
Addresses 0000 16 to 000F 16 store the product name, and addresses 10000 16 to 11FFF 16 store the character pattern.
If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form, the
ROM processing is disabled. Write the data correctly.
1. Inputting the name of the product with the ASCII code
ASCII codes ‘M37221M4-’ are listed on the right.
The addresses and data are in hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ =
‘3’ =
‘7’ =
‘2’ =
‘2’ =
‘1’ =
‘M’ =
‘4’ =
4D
33
37
32
32
31
4D
34
16
16
16
16
16
16
16
16
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘–’ = 2 D
FF
FF
FF
FF
FF
FF
FF
16
16
16
16
16
16
16
16
2. Inputting the character ROM
Input the character ROM data by dividing it into character ROM1 and character ROM2. For the character ROM data,
see the next page and on.
(2/3)
6-66
7220 Group User’s Manual
APPENDIX
6.11 Mask ROM ordering method
GZZ–SH10–10B< 59B0 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37221M4-XXXSP
MITSUBISHI ELECTRIC
The structure of character ROM (divided of 12 ✕16 dots font)
Example
(Note)
Write the character code “00 16” to “7F 16”
to addreses 10000 16 to 10FFF 16.
Write the character code “80 16” to “FF 16”
to addreses 11000 16 to 11FFF 16.
Character code
“1A16”
Character
ROM1
Example
101A016
0
to
1
101AF16
2
3
4
5
6
7
8
9
A
B
C
D
E
F
⇐
⇐
Character
ROM2
b7 b6 b5 b4 b3 b2 b1 b0
0016
0416
0416
0A16
0A16
1116
1116
1116
2016
2016
3F16
4016
4016
4016
0016
0016
Example
109A016
0
to
1
109AF16
2
3
4
5
6
7
8
9
A
B
C
D
E
F
b7 b6 b5 b4 b3 b2 b1 b0
F16
F016
F016
F016
F016
F016
F016
F016
F016
F816
F816
F816
F416
F416
F416
F016
F016
(3/3)
7220 Group User’s Manual
6-67
APPENDIX
6.11 Mask ROM ordering method
GZZ–SH11–58B < 72A0 >
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37221M8-XXXSP
MITSUBISHI ELECTRIC
Receipt
Date :
Section head
signature
Supervisor
signature
Note : Please fill in all items marked ❈.
Date
issued
Date :
)
Issuance
(
Customer
Supervisor
signature
❈
Submitted by
TEL
Company
name
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on
this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce
differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27C101
EPROM address
000016
Product name
ASCII code :
‘M37221M8 –’
000F16
800016
FFFF 16
10000 16
107FF 16
10800 16
10FFF16
11000 16
117FF 16
11800 16
11FFF16
data
ROM 32 K bytes
Character ROM 1-a
Character ROM 2-a
Character ROM 1-b
Character ROM 1-b
1FFFF 16
(1)
(2)
Set “FF 16” in the shaded area.
Write the ASCII codes that indicates the product name of “M37221M8–” to addresses 0000 16 to 000F 16.
EPROM data check item (Refer the EPROM data and check “ ✓” in the appropriate box)
→ Yes
● Do you set “FF 16” in the shaded area ?
● Do you write the ASCII codes that indicates the product
→ Yes
name of “M37221M8–” to addresses 0000 16 to 000F 16 ?
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate
mark specification form (42P4B for M37221M8-XXXSP) and attach to the mask ROM confirmation form.
❈ 3. Comments
(1/3)
6-68
7220 Group User’s Manual
APPENDIX
6.11 Mask ROM ordering method
GZZ–SH11–58B <72A0 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37221M8-XXXSP
MITSUBISHI ELECTRIC
Writing the product name and character ROM data onto EPROMs
Addresses 0000 16 to 000F 16 store the product name, and addresses 10000 16 to 11FFF 16 store the character pattern.
If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form, the
ROM processing is disabled. Write the data correctly.
1. Inputting the name of the product with the ASCII code
ASCII codes ‘M37221M8-’ are listed on the right.
The addresses and data are in hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ =
‘3’ =
‘7’ =
‘2’ =
‘2’ =
‘1’ =
‘M’ =
‘8’ =
4D
33
37
32
32
31
4D
38
16
16
16
16
16
16
16
16
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘–’ = 2 D
FF
FF
FF
FF
FF
FF
FF
16
16
16
16
16
16
16
16
2. Inputting the character ROM
Input the character ROM data by dividing it into character ROM1 and character ROM2. For the character ROM data,
see the next page and on.
(2/3)
7220 Group User’s Manual
6-69
APPENDIX
6.11 Mask ROM ordering method
GZZ–SH11–58B< 72A0 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37221M8-XXXSP
MITSUBISHI ELECTRIC
The structure of character ROM (divided of 12 ✕16 dots font)
Example
(Note)
Write the character code “00 16” to “7F 16”
to addreses 10000 16 to 10FFF 16.
Write the character code “80 16” to “FF 16”
to addreses 11000 16 to 11FFF 16.
Character code
“1A16”
Character
ROM1
Example
101A016
0
to
1
101AF16
2
3
4
5
6
7
8
9
A
B
C
D
E
F
⇐
⇐
Character
ROM2
b7 b6 b5 b4 b3 b2 b1 b0
0016
0416
0416
0A16
0A16
1116
1116
1116
2016
2016
3F16
4016
4016
4016
0016
0016
Example
109A016
0
to
1
109AF16
2
3
4
5
6
7
8
9
A
B
C
D
E
F
(3/3)
6-70
7220 Group User’s Manual
b7 b6 b5 b4 b3 b2 b1 b0
F16
F016
F016
F016
F016
F016
F016
F016
F016
F816
F816
F816
F416
F416
F416
F016
F016
APPENDIX
6.11 Mask ROM ordering method
GZZ–SH09–46B < 52C0 >
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37221M6-XXXSP/FP
MITSUBISHI ELECTRIC
Receipt
Date :
Section head
signature
Supervisor
signature
Note : Please fill in all items marked ❈.
Customer
Date
issued
Date :
)
Issuance
(
Supervisor
signature
Company
name
❈
Submitted by
TEL
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on
this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce
differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27C101
EPROM address
000016
Product name
ASCII code :
‘M37221M6 –’
000F16
A00016
FFFF 16
10000 16
107FF 16
10800 16
10FFF16
11000 16
117FF 16
11800 16
11FFF16
data
ROM 24 K bytes
Character ROM 1-a
Character ROM 2-a
Character ROM 1-b
Character ROM 1-b
1FFFF 16
(1)
(2)
Set “FF 16” in the shaded area.
Write the ASCII codes that indicates the product name of “M37221M6–” to addresses 0000 16 to 000F 16.
EPROM data check item (Refer the EPROM data and check “ ✓” in the appropriate box)
→ Yes
● Do you set “FF 16” in the shaded area ?
● Do you write the ASCII codes that indicates the product
→ Yes
name of “M37221M6–” to addresses 0000 16 to 000F 16 ?
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate
mark specification form (42P4B for M37221M6-XXXSP, 42P2R-A for M37221M6-XXXFP) and attach to the mask
ROM confirmation form.
❈ 3. Comments
(1/3)
7220 Group User’s Manual
6-71
APPENDIX
6.11 Mask ROM ordering method
GZZ–SH09–46B <52C0 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37221M6-XXXSP/FP
MITSUBISHI ELECTRIC
Writing the product name and character ROM data onto EPROMs
Addresses 0000 16 to 000F 16 store the product name, and addresses 10000 16 to 11FFF 16 store the character pattern.
If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form, the
ROM processing is disabled. Write the data correctly.
1. Inputting the name of the product with the ASCII code
ASCII codes ‘M37221M6-’ are listed on the right.
The addresses and data are in hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ =
‘3’ =
‘7’ =
‘2’ =
‘2’ =
‘1’ =
‘M’ =
‘6’ =
4D
33
37
32
32
31
4D
36
16
16
16
16
16
16
16
16
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘–’ = 2 D
FF
FF
FF
FF
FF
FF
FF
16
16
16
16
16
16
16
16
2. Inputting the character ROM
Input the character ROM data by dividing it into character ROM1 and character ROM2. For the character ROM data,
see the next page and on.
(2/3)
6-72
7220 Group User’s Manual
APPENDIX
6.11 Mask ROM ordering method
GZZ–SH09–46B< 52C0 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37221M6-XXXSP/FP
MITSUBISHI ELECTRIC
The structure of character ROM (divided of 12 ✕16 dots font)
Example
(Note)
Write the character code “00 16” to “7F 16”
to addreses 10000 16 to 10FFF 16.
Write the character code “80 16” to “FF 16”
to addreses 11000 16 to 11FFF 16.
Character code
“1A16”
Character
ROM1
Example
101A016
0
to
1
101AF16
2
3
4
5
6
7
8
9
A
B
C
D
E
F
⇐
⇐
Character
ROM2
b7 b6 b5 b4 b3 b2 b1 b0
0016
0416
0416
0A16
0A16
1116
1116
1116
2016
2016
3F16
4016
4016
4016
0016
0016
Example
109A016
0
to
1
109AF16
2
3
4
5
6
7
8
9
A
B
C
D
E
F
b7 b6 b5 b4 b3 b2 b1 b0
F16
F016
F016
F016
F016
F016
F016
F016
F016
F816
F816
F816
F416
F416
F416
F016
F016
(3/3)
7220 Group User’s Manual
6-73
APPENDIX
6.11 Mask ROM ordering method
GZZ–SH10–46B < 5ZA0 >
Mask ROM number
SERIES MELPS 740 MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37221MA-XXXSP
MITSUBISHI ELECTRIC
Receipt
Date :
Section head
signature
Supervisor
signature
Note : Please fill in all items marked ❈.
Customer
Date
issued
Date :
)
Issuance
(
Supervisor
signature
Company
name
❈
Submitted by
TEL
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on
this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce
differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27C101
EPROM address
000016
Product name
ASCII code :
‘M37221MA –’
000F16
600016
FFFF 16
10000 16
107FF 16
10800 16
10FFF16
11000 16
117FF 16
11800 16
11FFF16
data
ROM 40 K bytes
Character ROM 1-a
Character ROM 2-a
Character ROM 1-b
Character ROM 2-b
1FFFF 16
(1)
(2)
Set “FF 16” in the shaded area.
Write the ASCII codes that indicates the product name of “M37221MA–” to addresses 0000 16 to 000F 16.
EPROM data check item (Refer the EPROM data and check “ ✓” in the appropriate box)
→ Yes
● Do you set “FF 16” in the shaded area ?
● Do you write the ASCII codes that indicates the product
→ Yes
name of “M37221MA–” to addresses 0000 16 to 000F 16 ?
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate
mark specification form (42P4B for M37221MA-XXXSP) and attach to the mask ROM confirmation form.
❈ 3. Comments
6-74
(1/3)
7220 Group User’s Manual
APPENDIX
6.11 Mask ROM ordering method
GZZ–SH10–46B <5ZA0 >
SERIES MELPS 740 MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37221MA-XXXSP
MITSUBISHI ELECTRIC
Writing the product name and character ROM data onto EPROMs
Addresses 0000 16 to 000F 16 store the product name, and addresses 10000 16 to 11FFF 16 store the character pattern.
If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form,
the ROM processing is disabled. Write the data correctly.
1. Inputting the name of the product with the ASCII code
ASCII codes ‘M37221MA-’ are listed on the right.
The addresses and data are in hexadecimal notation.
Address
0000 16
0001 16
0002 16
0003 16
0004 16
0005 16
0006 16
0007 16
‘M’ =
‘3’ =
‘7’ =
‘2’ =
‘2’ =
‘1’ =
‘M’ =
‘A’ =
4 D 16
3 3 16
3 7 16
3 2 16
3 2 16
3 1 16
4 D 16
4 1 16
Address
000816
000916
000A 16
000B 16
000C 16
000D 16
000E 16
000F 16
‘–’ = 2 D 16
F F 16
F F 16
F F 16
F F 16
F F 16
F F 16
F F 16
2. Inputting the character ROM
Input the character ROM data by dividing it into character ROM1 and character ROM2. For the character ROM data,
see the next page and on.
(2/3)
7220 Group User’s Manual
6-75
APPENDIX
6.11 Mask ROM ordering method
GZZ–SH10–46B< 5ZA0 >
SERIES MELPS 740 MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37221MA-XXXSP
MITSUBISHI ELECTRIC
The structure of character ROM (divided of 12 ✕16 dots font)
Example
(Note)
Write the character code “00 16” to “7F 16”
to addresses 10000 16 to 10FFF 16.
Write the character code “80 16” to “FF 16”
to addresses 11000 16 to 11FFF 16.
Character code
“1A16”
Character
ROM1
Example
101A0 16
0
to
1
101AF 16
2
3
4
5
6
7
8
9
A
B
C
D
E
F
⇐
⇐
Character
ROM2
b7 b6 b5 b4 b3 b2 b1 b0
0 016
0 416
0416
0A16
0A16
1 116
1 116
1 116
2 016
2 016
3 F16
4 016
4 016
4 016
0 016
0 016
Example
109A0 16
0
to
1
109AF 16
2
3
4
5
6
7
8
9
A
B
C
D
E
F
(3/3)
6-76
7220 Group User’s Manual
b7 b6 b5 b4 b3 b2 b1 b0
F16
F016
F016
F016
F016
F016
F016
F016
F016
F816
F816
F816
F416
F416
F416
F016
F016
APPENDIX
6.11 Mask ROM ordering method
GZZ–SH09–72B < 56B0 >
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37220M3-XXXSP
MITSUBISHI ELECTRIC
Receipt
Date :
Section head
signature
Supervisor
signature
Note : Please fill in all items marked ❈.
Customer
Date
issued
Date :
)
Issuance
(
Supervisor
signature
Company
name
❈
Submitted by
TEL
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on
this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce
differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27C101
EPROM address
000016
Product name
000F16
D000 16
FFFF 16
10000 16
ASCII code :
‘M37220M3 –’
data
ROM 12 K bytes
Character ROM 1
107FF 16
10800 16
Character ROM 2
10FFF16
11000 16
1FFFF 16
(1)
(2)
Set “FF 16” in the shaded area.
Write the ASCII codes that indicates the product name of “M37220M3–” to addresses 0000 16 to 000F 16.
EPROM data check item (Refer the EPROM data and check “ ✓” in the appropriate box)
→ Yes
● Do you set “FF 16” in the shaded area ?
● Do you write the ASCII codes that indicates the product
→ Yes
name of “M37220M3–” to addresses 0000 16 to 000F 16 ?
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate
mark specification form (42P4B for M37220M3-XXXSP) and attach to the mask ROM confirmation form.
❈ 3. Comments
(1/3)
7220 Group User’s Manual
6-77
APPENDIX
6.11 Mask ROM ordering method
GZZ–SH09–72B <56B0 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37220M3-XXXSP
MITSUBISHI ELECTRIC
Writing the product name and character ROM data onto EPROMs
Addresses 0000 16 to 000F 16 store the product name, and addresses 10000 16 to 10FFF 16 store the character pattern.
If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form,
the ROM processing is disabled. Write the data correctly.
1. Inputting the name of the product with the ASCII code
ASCII codes ‘M37220M3-’ are listed on the right.
The addresses and data are in hexadecimal notation.
Address
0000 16
0001 16
0002 16
0003 16
0004 16
0005 16
0006 16
0007 16
‘M’ =
‘3’ =
‘7’ =
‘2’ =
‘2’ =
‘0’ =
‘M’ =
‘3’ =
4 D 16
3 3 16
3 7 16
3 2 16
3 2 16
3 0 16
4 D 16
3 3 16
Address
0008 16
0009 16
000A 16
000B 16
000C 16
000D 16
000E 16
000F 16
‘–’ = 2 D 16
F F 16
F F 16
F F 16
F F 16
F F 16
F F 16
F F 16
2. Inputting the character ROM
Input the character ROM data by dividing it into character ROM1 and character ROM2. For the character ROM data,
see the next page and on.
(2/3)
6-78
7220 Group User’s Manual
APPENDIX
6.11 Mask ROM ordering method
GZZ–SH09–72B< 56B0 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37220M3-XXXSP
MITSUBISHI ELECTRIC
The structure of character ROM (divided of 12 ✕16 dots font)
Example
Character code
“1A16”
Character
ROM1
Example
101A0 16
0
to
1
101AF 16
2
3
4
5
6
7
8
9
A
B
C
D
E
F
⇐
⇐
Character
ROM2
b7 b6 b5 b4 b3 b2 b1 b0
0 016
0 416
0416
0A16
0A16
1 116
1 116
1 116
2 016
2 016
3 F16
4 016
4 016
4 016
0 016
0 016
Example
109A0 16
0
to
1
109AF 16
2
3
4
5
6
7
8
9
A
B
C
D
E
F
b7 b6 b5 b4 b3 b2 b1 b0
F16
F016
F016
F016
F016
F016
F016
F016
F016
F816
F816
F816
F416
F416
F416
F016
F016
(3/3)
7220 Group User’s Manual
6-79
APPENDIX
6.12 Mark specification form
6.12 Mark specification form
42P4B (42-PIN SHRINK DIP) MARK SPECIFICATION FORM
6-80
7220 Group User’s Manual
APPENDIX
6.12 Mark specification form
42P2R-A (42-PIN SHRINK SOP) MARK SPECIFICATION FORM
7220 Group User’s Manual
6-81
MITSUBISHI SEMICONDUCTORS
USER’S MANUAL
7220 Group
Jul. First Edition 1997
Editioned by
Committee of editing of Mitsubishi Semiconductor USER’S MANUAL
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©1997 MITSUBISHI ELECTRIC CORPORATION
User’s Manual
7220 Group
© 1997 MITSUBISHI ELECTRIC CORPORATION.
New publication, effective Jul. 1997.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev.
No.
7220 GROUP USER'S MANUAL
Revision Description
Rev.
date
1.0
First Edition
9708
2.0
Information about copywright note, revision number, release date added (last page).
971130
(1/1)