FAIRCHILD 74ACTQ273SJX

Revised August 2001
74ACTQ273
Quiet Series Octal D-Type Flip-Flop
General Description
Features
The ACTQ273 has eight edge-triggered D-type flip-flops
with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and
reset (clear) all flip-flops simultaneously.
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
The register is fully edge-triggered. The state of each Dtype input, one setup time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s Q
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
■ ICC reduced by 50%
■ Guaranteed pin-to-pin skew AC performance
■ Improved latch-up immunity
■ Buffered common clock and asynchronous master reset
■ Outputs source/sink 24 mA
■ 4 kV minimum ESD immunity
The ACTQ utilizes Fairchild Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series features
GTO output control and undershoot corrector in addition
to a split ground bus for superior performance.
Ordering Code:
Order Number
74ACTQ273SC
74ACTQ273SJ
74ACTQ273MTC
74ACTQ273PC
Package Number
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Description
D0–D7
Data Inputs
MR
Master Reset
CP
Clock Pulse Input
Q0–Q7
Data Outputs
FACT, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
© 2001 Fairchild Semiconductor Corporation
DS010585
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74ACTQ273 Quiet Series Octal D-Type Flip-Flop
August 1989
74ACTQ273
Logic Symbols
IEEE/IEC
Mode Select-Function Table
Inputs
Outputs
Operating Mode
MR
CP
Dn
Qn
Reset (Clear)
L
X
X
L
Load “1”
H
H
H
Load “0”
H
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Recommended Operating
Conditions
−0.5V to +7.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
−20 mA
VI = VCC + 0.5V
+20 mA
Supply Voltage (VCC)
−0.5V to VCC + 0.5V
DC Input Voltage (VI)
0V to VCC
Output Voltage (VO)
0V to VCC
−40°C to +85°C
Operating Temperature (TA)
Minimum Input Edge Rate ∆V/∆t
DC Output Diode Current (IOK)
VO = −0.5V
−20 mA
VO = VCC + 0.5V
+20 mA
DC Output Voltage (VO)
4.5V to 5.5V
Input Voltage (VI)
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
−0.5V to VCC + 0.5V
125 mV/ns
DC Output Source
±50 mA
or Sink Current (IO)
DC VCC or Ground Current
±50 mA
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
−65°C to +150°C
DC Latch-up Source or
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
±300 mA
Sink Current
Junction Temperature (TJ)
140°C
PDIP
DC Electrical Characteristics
Symbol
Parameter
V CC
TA = +25°C
(V)
Typ
4.5
1.5
TA = −40°C to +85°C
Guaranteed Limits
VIH
Minimum HIGH Level
2.0
2.0
Input Voltage
5.5
1.5
2.0
2.0
VIL
Maximum LOW Level
4.5
1.5
0.8
0.8
Input Voltage
5.5
1.5
0.8
0.8
VOH
Minimum HIGH Level
4.5
4.49
4.4
4.4
Output Voltage
5.5
5.49
5.4
5.4
Units
V
V
V
Conditions
VOUT = 0.1V
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
IOUT = −50 µA
VIN = VIL or VIH
VOL
4.5
3.86
3.76
5.5
4.86
4.76
Maximum LOW Level
4.5
0.001
0.1
0.1
Output Voltage
5.5
0.001
0.1
0.1
4.5
0.36
0.44
V
IOH = −24 mA
IOH = −24 mA (Note 2)
V
IOUT = 50 µA
V
IOL = 24 mA
VIN = VIL or VIH
IOL = 24 mA (Note 2)
5.5
0.36
0.44
IIN
Maximum Input Leakage Current
5.5
±0.1
± 1.0
µA
ICCT
Maximum ICC/Input
5.5
1.5
mA
VI = VCC − 2.1V
IOLD
Minimum Dynamic
5.5
75
mA
VOLD = 1.65V Max
IOHD
Output Current (Note 3)
5.5
−75
mA
VOHD = 3.85V Min
ICC
Maximum Quiescent Supply Current
5.5
40.0
µA
VOLP
Quiet Output
Maximum Dynamic VOL
VOLV
Quiet Output
Minimum Dynamic VOL
0.6
4.0
5.0
1.1
1.5
V
5.0
−0.6
−1.2
V
VI = VCC, GND
VIN = VCC or GND
Figures 1, 2
(Note 4)
Figures 1, 2
(Note 4)
VIHD
Minimum HIGH Level Dynamic Input Voltage
5.0
1.9
2.2
V
(Note 5)
VILD
Maximum LOW Level Dynamic Input Voltage
5.0
1.2
0.8
V
(Note 5)
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: Max number of outputs defined as (n). n − 1 Data inputs are driven 0V to 3V; one output @ GND.
Note 5: Max number of Data Inputs (n) switching. (n − 1) Inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD) f = 1 MHz.
3
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74ACTQ273
Absolute Maximum Ratings(Note 1)
74ACTQ273
AC Electrical Characteristics
Symbol
Parameter
Maximum Clock
fMAX
Frequency
tPLH
Propagation Delay
tPHL
CP to Qn
tPHL
Propagation Delay
MR to Qn
tOSHL,
Output to Output
tOSLH
Skew (Note 7)
VCC
TA = +25°C
(V)
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
Min
Typ
5.0
125
189
5.0
1.5
6.5
8.5
1.5
9.0
ns
5.0
1.5
7.0
9.0
1.5
9.5
ns
0.5
1.0
1.0
ns
5.0
Max
Min
Units
(Note 6)
Max
110
MHz
Note 6: Voltage Range 5.0 is 5.0V ± 0.5V
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device.
The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by
design. Not tested.
AC Operating Requirements
Symbol
tS
Parameter
Setup Time, HIGH or LOW
Dn to CP
tH
Hold Time, HIGH or LOW
Dn to CP
tW
Clock Pulse Width
HIGH or LOW
tW
MR Pulse Width
HIGH or LOW
tW
Recovery Time
MR to CP
VCC
TA = +25°C
(V)
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
Typ
Guaranteed Minimum
5.0
1.0
3.5
3.5
ns
5.0
−0.5
1.5
1.5
ns
5.0
2.0
4.0
4.0
ns
5.0
1.5
4.0
4.0
ns
5.0
0.5
3.0
3.0
ns
Note 8: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Typ
Units
CIN
Input Capacitance
Parameter
4.5
pF
VCC = OPEN
CPD
Power Dissipation Capacitance
40.0
pF
VCC = 5.0V
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Units
(Note 8)
4
Conditions
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
VOLP/VOLV and VOHP/V OHV:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
• Measure VOLP and VOLV on the quiet output during the
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
case active and enable transition.
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500Ω.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
VILD and VIHD:
• Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the
correct voltage.
• First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measurement.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
• Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as VIHD.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
FIGURE 1. Quiet Output Noise Voltage Waveforms
Note 9: VOHV and VOLP are measured with respect to ground reference.
Note 10: Input pulses have the following characteristics: f = 1 MHz, tr =
3 ns, tf = 3 ns, skew < 150 ps.
FIGURE 2. Simultaneous Switching Test Circuit
5
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74ACTQ273
FACT Noise Characteristics
74ACTQ273
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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74ACTQ273
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
7
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74ACTQ273
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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8
74ACTQ273 Quiet Series Octal D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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