INTEGRATED CIRCUITS DATA SHEET 74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state Product specification File under Integrated Circuits, IC06 1999 Jun 16 Philips Semiconductors Product specification 74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state FEATURES DESCRIPTION • 3-state non-inverting outputs for bus oriented applications The 74AHC/AHCT574 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. • 8-bit positive, edge-triggered register • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V • Independent register and 3-state buffer operation • Common 3-state output enable input • Output capability; bus driver The 74AHC/AHCT574 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The ‘574’ is functionally identical to the ‘564’, but has non-inverting outputs. The ‘574’ is functionally identical to the ‘374’, but has a different pinning. • ICC category: MSI • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Specified from −40 to +85 and +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. TYPICAL SYMBOL PARAMETER CONDITIONS UNIT AHC tPHL/tPLH propagation delay AHCT CL = 15 pF; VCC = 5 V 4.4 4.4 ns CP to Qn fmax maximum clock frequency CL = 15 pF; VCC = 5 V 130 130 MHz CI input capacitance VI = VCC or GND 4.0 4.0 pF CO output capacitance 4.0 4.0 pF CPD power dissipation capacitance 10 12 pF CL = 50 pF; f = 1 MHz; notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. 1999 Jun 16 2 Philips Semiconductors Product specification 74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state FUNCTION TABLE See note 1. INPUTS OUTPUTS OE CP Dn INTERNAL FLIP-FLOPS L ↑ I L L L ↑ h H H H ↑ l L Z H ↑ h H Z OPERATING MODES Load and read register Load register and disable outputs Q0 to Q7 Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; Z = high-impedance OFF-state; ↑ = LOW-to-HIGH CP transition. ORDERING INFORMATION PACKAGES OUTSIDE NORTH AMERICA NORTH AMERICA PINS PACKAGE MATERIAL CODE 74AHC574D 74AHC574D 20 SO plastic SOT163-1 74AHC574PW 74AHC574PW DH 20 TSSOP plastic SOT360-1 74AHCT574D 74AHCT574D 20 SO plastic SOT163-1 74AHCT574PW 74AHCT574PW DH 20 TSSOP plastic SOT360-1 PINNING PIN 1 SYMBOL DESCRIPTION OE 3-state output enable input (active LOW) 2, 3, 4, 5, 6, 7, 8 and 9 D0 to D7 data inputs 10 GND ground (0 V) 11 CP clock input (LOW-to-HIGH, edge triggered) 19, 18, 17, 16, 15, 14, 13 and 12 Q0 to Q7 3-state flip-flop outputs 20 VCC DC supply voltage 1999 Jun 16 3 Philips Semiconductors Product specification 74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state handbook, halfpage OE 1 20 VCC D0 2 19 Q0 11 handbook, halfpage 2 18 Q1 D1 3 3 D2 4 17 Q2 D3 5 16 Q3 5 15 Q4 6 574 D4 6 D5 7 14 Q5 D6 8 13 Q6 D7 9 12 Q7 GND 10 11 CP 4 7 8 9 CP D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 OE 1 Q7 19 18 17 16 15 14 13 12 MNA445 MNA444 Fig.1 Pin configuration. handbook, halfpage 11 1 2 Fig.2 Logic symbol. handbook, halfpage C1 EN 19 1D 3 18 4 17 5 16 6 15 7 14 8 13 9 12 D0 3 D1 Q0 19 Q1 18 4 D2 Q2 17 5 D3 6 D4 7 D5 Q5 14 8 D6 Q6 13 9 D7 Q7 12 FF1 to FF8 3-STATE OUTPUTS Q3 16 Q4 15 11 CP 1 OE MNA447 MNA446 Fig.3 IEC logic symbol. 1999 Jun 16 2 Fig.4 Functional diagram. 4 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... D D2 D Q Q D FF2 FF1 Q D4 D FF3 CP CP D3 Q D FF4 CP D5 Q D FF5 CP D6 Q D FF6 CP D7 Q D FF7 CP Q FF8 CP CP 5 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Philips Semiconductors D1 Octal D-type flip-flop; positive edge-trigger; 3-state handbook, full pagewidth 1999 Jun 16 D0 MNA449 Product specification 74AHC574; 74AHCT574 Fig.5 Logic diagram. Philips Semiconductors Product specification 74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state RECOMMENDED OPERATING CONDITIONS 74AHC SYMBOL PARAMETER 74AHCT CONDITIONS UNIT MIN. TYP. MAX. MIN. TYP. MAX. VCC DC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V VI input voltage 0 − 5.5 0 − 5.5 V VO output voltage Tamb operating ambient temperature range see DC and AC characteristics per device input rise and fall times except for Schmitt-trigger inputs VCC = 3.3 V ±0.3 V − − 100 − VCC = 5 V ±0.5 V − − 20 − tr,tf (∆t/∆f) 0 − VCC 0 − VCC V −40 +25 +85 −40 +25 +85 °C −40 +25 +125 −40 +25 +125 °C − − ns/V − 20 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. −0.5 MAX. UNIT VCC DC supply voltage VI input voltage range −0.5 +7.0 V IIK DC input diode current VI < −0.5 V; note 1 − −20 mA IOK DC output diode current VO < −0.5 V or VO > VCC + 0.5 V; note 1 − ±20 mA −0.5 V < VO < VCC + 0.5 V +7.0 V IO DC output source or sink current − ±25 mA ICC DC VCC or GND current − ±75 mA Tstg storage temperature range −65 +150 °C PD power dissipation per package − 500 mW for temperature range: −40 to +125 °C; note 2 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO-packages: above 70 °C the value of PD derates linearly with 8 mW/K. For TSSOP-packages: above 60 °C the value of PD derates linearly with 5.5 mW/K. 1999 Jun 16 6 Philips Semiconductors Product specification 74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state DC CHARACTERISTICS Family 74AHC Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER VIL VOH VOL −40 to +85 +25 OTHER VIH Tamb (°C) VCC (V) −40 to +125 UNIT MIN. TYP. MAX. MIN. MAX. MIN. MAX. HIGH-level input voltage 2.0 1.5 − − 1.5 − 1.5 − 3.0 2.1 − − 2.1 − 2.1 − 5.5 3.85 − − 3.85 − 3.85 − LOW-level input voltage 2.0 − − 0.5 − 0.5 − 0.5 3.0 − − 0.9 − 0.9 − 0.9 V V 5.5 − − 1.65 − 1.65 − 1.65 2.0 1.9 2.0 − 1.9 − 1.9 − 3.0 2.9 3.0 − 2.9 − 2.9 − 4.5 4.4 4.5 − 4.4 − 4.4 − 3.0 2.58 − − 2.48 − 2.40 − VI = VIH or VIL; IO = −8.0 mA 4.5 3.94 − − 3.8 − 3.70 − LOW-level output voltage; all outputs VI = VIH or VIL; IO = 50 µA 2.0 − 0 0.1 − 0.1 − 0.1 3.0 − 0 0.1 − 0.1 − 0.1 4.5 − 0 0.1 − 0.1 − 0.1 LOW-level output voltage VI = VIH or VIL; IO = 4.0 mA 3.0 − − 0.36 − 0.44 − 0.55 VI = VIH or VIL; IO = 8.0 mA 4.5 − − 0.36 − 0.44 − 0.55 − 1.0 − 2.0 ±2.5 − ±10.0 µA HIGH-level output voltage; all outputs VI = VIH or VIL; IO = −50 µA HIGH-level output voltage VI = VIH or VIL; IO = −4.0 mA V V V V II input leakage current VI = VCC or GND 5.5 − − 0.1 IOZ 3-state output OFF current VI = VIH or VIL; 5.5 VO = VCC or GND − − ±0.25 − ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 4.0 − 40 − 80 µA CI input capacitance − − 3 10 − 10 − 10 pF 1999 Jun 16 7 µA Philips Semiconductors Product specification 74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state Family 74AHCT Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL Tamb (°C) PARAMETER −40 to +85 +25 OTHER VCC (V) −40 to +125 UNIT MIN. TYP. MAX. MIN. MAX. MIN. MAX. VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − 2.0 − 2.0 − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 − 0.8 − 0.8 V VOH HIGH-level output voltage; all outputs VI = VIH or VIL; IO = −50 µA 4.5 4.4 4.5 − 4.4 − 4.4 − V HIGH-level output voltage VI = VIH or VIL; IO = −8.0 mA 4.5 3.94 − − 3.8 − 3.70 − V LOW-level output voltage; all outputs VI = VIH or VIL; IO = 50 µA 4.5 − 0 0.1 − 0.1 − 0.1 V LOW-level output voltage VI = VIH or VIL; IO = 8.0 mA 4.5 − − 0.36 − 0.44 − 0.55 V II input leakage current VI = VIH or VIL 5.5 − − 0.1 − 1.0 − 2.0 µA IOZ 3-state output OFF current VI = VIH or VIL; VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 5.5 − − ±0.25 − ±2.5 − ±10.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 4.0 − 40 − 80 µA ∆ICC additional quiescent supply current per input pin VI = VCC − 2.1 V other inputs at VCC or GND; IO = 0 4.5 to 5.5 − − 1.35 − 1.5 − 1.5 mA CI input capacitance − 3 10 − 10 − 10 pF VOL 1999 Jun 16 − 8 Philips Semiconductors Product specification 74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state AC CHARACTERISTICS Type 74AHC574 GND = 0 V; tr = tf ≤ 3.0 ns. TEST CONDITIONS Tamb (°C) SYMBOL PARAMETER tPHL/tPLH propagation delay CP to Qn see Figs 6, 8 and 9 tPZH/tPZL 3-state output enable time OE to Qn see Figs 7 and 9 tPHZ/tPLZ 3-state output disable time OE to Qn tPHL/tPLH propagation delay CP to Qn see Figs 6, 8 and 9 tPZH/tPZL 3-state output enable time OE to Qn see Figs 7 and 9 tPHZ/tPLZ 3-state output disable time OE to Qn tPHL/tPLH propagation delay CP to Qn see Figs 6, 8 and 9 tPZH/tPZL 3-state output enable time OE to Qn see Figs 7 and 9 tPHZ/tPLZ 3-state output disable time OE to Qn tPHL/tPLH propagation delay CP to Qn see Figs 6, 8 and 9 tPZH/tPZL 3-state output enable time OE to Qn see Figs 7 and 9 tPHZ/tPLZ 3-state output disable time OE to Qn 1999 Jun 16 −40 to +85 +25 WAVEFORMS CL VCC (V) MIN. TYP. −40 to +125 UNIT MAX. MIN. MAX. MIN. MAX. 15 pF 3.0 to 3.6 − 6.5(1) 13.2 1.0 15.5 1.0 16.5 ns − 5.7(1) 12.8 1.0 15.0 1.0 16.0 ns − 6.3(1) 13.0 1.0 15.0 1.0 16.5 ns − 9.3(1) 16.7 1.0 19.0 1.0 21.0 ns − 8.2(1) 16.3 1.0 18.5 1.0 20.5 ns − 9.1(1) 15.0 1.0 17.0 1.0 19.0 ns 15 pF 4.5 to 5.5 − 4.4(2) 8.6 1.0 10.0 1.0 11.0 ns − 4.2(2) 9.0 1.0 10.5 1.0 11.5 ns − 4.3(2) 9.0 1.0 10.5 1.0 11.5 ns − 6.2(2) 10.6 1.0 12.0 1.0 13.5 ns − 5.9(2) 11.0 1.0 12.5 1.0 14.0 ns − 6.9(2) 10.1 1.0 11.5 1.0 13.0 ns 50 pF 50 pF 9 Philips Semiconductors Product specification 74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state Tamb (°C) TEST CONDITIONS WAVEFORMS tW clock pulse see Figs 6 width and 9 HIGH or LOW tsu setup time Dn to CP th hold time Dn to CP fmax maximum clock pulse frequency CL VCC (V) see Figs 6 and 9 clock pulse see Figs 6 width and 9 HIGH or LOW tsu setup time Dn to CP th hold time Dn to CP fmax maximum clock pulse frequency MAX. MIN. MAX. MIN. MAX. − − 5.0 − 5.0 − ns 3.5 − − 3.5 − 3.5 − ns 1.5 − − 1.5 − 1.5 − ns 50 75 − 45 − 45 − MHz 80 125 − 65 − 65 − MHz 50 pF 4.5 to 5.5 5.0 − − 5.0 − 5.0 − ns 3.0 − − 3.0 − 3.0 − ns 1.5 − − 1.5 − 1.5 − ns 85 115 − 75 − 75 − MHz 130 180 − 110 − 110 − MHz 15 pF see Figs 8 and 9 see Figs 6 and 9 MIN. TYP. −40 to +125 UNIT 50 pF 3.0 to 3.6 5.0 see Figs 8 and 9 tW 15 pF Notes 1. Typical values at VCC = 3.3 V. 2. Typical values at VCC = 5.0 V. 1999 Jun 16 −40 to +85 +25 SYMBOL PARAMETER 10 Philips Semiconductors Product specification 74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state Type 74AHCT574 GND = 0 V; tr = tf ≤ 3.0 ns. TEST CONDITIONS Tamb (°C) SYMBOL PARAMETER −40 to +85 +25 WAVEFORMS CL VCC (V) MIN. TYP. −40 to +125 UNIT MAX. MIN. MAX. MIN. MAX. 8.6 1.0 10.0 1.0 11.0 ns tPHL/tPLH propagation delay CP to Qn see Figs 6 and 9 15 pF 4.5 to 5.5 − tPZH/tPZL 3-state output enable time OE to Qn see Figs 7 and 9 − 4.3(1) 9.0 1.0 10.5 1.0 11.5 ns tPHZ/tPLZ 3-state output disable time OE to Qn − 4.3(1) 9.0 1.0 10.5 1.0 11.5 ns tPHL/tPLH propagation delay CP to Qn see Figs 6 and 9 − 6.3(1) 10.6 1.0 12.0 1.0 13.5 ns tPZH/tPZL 3-state output enable time OE to Qn see Figs 7 and 9 − 6.1(1) 11.0 1.0 12.5 1.0 14.0 ns tPHZ/tPLZ 3-state output disable time OE to Qn − 6.2(1) 10.1 1.0 11.5 1.0 13.0 ns tW clock pulse see Figs 6 width and 9 HIGH or LOW 5.0 − − 5.5 − 5.5 − ns tsu setup time Dn to CP 3.0 − − 3.5 − 3.5 − ns th hold time Dn to CP 1.5 − − 1.5 − 1.5 − ns fmax maximum clock pulse frequency 85 115 − 75 − 75 − MHz 130 180 − 110 − 110 − MHz 50 pF see Figs 8 and 9 see Figs 6 and 9 15 pF Note 1. Typical values at VCC = 5.0 V. 1999 Jun 16 11 4.4(1) Philips Semiconductors Product specification 74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state AC WAVEFORMS 1/f max handbook, full pagewidth VI VM(1) CP INPUT GND tW tPHL tPLH VM(1) Qn OUTPUT MNA200 FAMILY VI INPUT REQUIREMENTS VM INPUT VM OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC Fig.6 The clock (CP) to output (Qn) propagation delays. VI handbook, full pagewidth VM(1) OE INPUT GND tPLZ OUTPUT LOW-to-OFF OFF-to-LOW tPZL VCC VM VOL + 0.3 V VOL tPHZ tPZH VOH VOH − 0.3 V OUTPUT HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled MNA450 FAMILY VI INPUT REQUIREMENTS VM INPUT VM OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC Fig.7 The 3-state enable and disable times. 1999 Jun 16 12 Philips Semiconductors Product specification 74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state VI handbook, full pagewidth VM(1) CP INPUT GND t su t su th th VI VM(1) Dn INPUT GND MNA448 VM OUTPUT FAMILY VI INPUT REQUIREMENTS VM INPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC The shaded areas indicate when the input is permitted to change for predicable output performance. Fig.8 The data set-up and hold times for Dn input. S1 handbook, full pagewidth VCC PULSE GENERATOR VI 1000 Ω VO VCC open GND D.U.T. CL RT MNA183 TEST S1 FAMILY VI INPUT REQUIREMENTS VM INPUT VM OUTPUT tPLH/tPHL open tPLZ/tPZL VCC AHC GND to VCC 50% VCC 50% VCC tPHZ/tPZH GND AHCT GND to 3.0 V 1.5 V 50% VCC Fig.9 Load circuitry for switching times. 1999 Jun 16 13 Philips Semiconductors Product specification 74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state PACKAGE OUTLINES SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013AC 1999 Jun 16 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-24 97-05-22 14 Philips Semiconductors Product specification 74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 1999 Jun 16 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-06-16 95-02-04 MO-153AC 15 o Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. SOLDERING Introduction to soldering surface mount packages • For packages with leads on two sides and a pitch (e): This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: 1999 Jun 16 74AHC574; 74AHCT574 16 Philips Semiconductors Product specification 74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable HLQFP, HSQFP, HSOP, SMS not PLCC(3), SO, SOJ suitable suitable(2) suitable suitable suitable LQFP, QFP, TQFP not recommended(3)(4) suitable SSOP, TSSOP, VSO not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Jun 16 17 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state NOTES 1999 Jun 16 18 74AHC574; 74AHCT574 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state NOTES 1999 Jun 16 19 74AHC574; 74AHCT574 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 245002/01/pp20 Date of release: 1999 Jun 16 Document order number: 9397 750 06027