PHILIPS 74AHCT139

INTEGRATED CIRCUITS
DATA SHEET
74AHC139; 74AHCT139
Dual 2-to-4 line
decoder/demultiplexer
Product specification
File under Integrated Circuits, IC06
1999 Sep 01
Philips Semiconductors
Product specification
74AHC139;
74AHCT139
Dual 2-to-4 line decoder/demultiplexer
FEATURES
DESCRIPTION
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
The 74AHC/AHCT139 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
• Balanced propagation delays
The 74AHC/AHCT139 are high-speed, dual 2-to-4 line
decoder/demultiplexers.
• All inputs have Schmitt trigger actions
• Inputs accept voltages higher than VCC
This device has two independent decoders, each
accepting two binary weighted inputs (nA0 and nA1) and
providing four mutually exclusive active LOW outputs
(nY0 to nY3). Each decoder has an active LOW enable
input (nE). When nE is HIGH, every output is forced HIGH.
The enable input can be used as the data input for a 1-to-4
demultiplexer application.
• For AHC only: operates with CMOS input levels
• For AHCT only: operates with TTL input levels
• Specified from −40 to +85 °C and −40 to +125 °C.
The ‘139’ is identical to the HEF4556 of the HE4000B
family.
QUICK REFERENCE DATA
Ground = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
AHC
tPHL/tPLH
propagation delay
CL = 15 pF; VCC = 5 V
nAn to nYn
3.9
4.7
ns
nE to nYn
3.4
3.6
ns
3.0
3.0
pF
4.0
4.0
pF
25.76
22.36
pF
CI
input capacitance
CO
output capacitance
CPD
power dissipation capacitance
VI = VCC or GND
CL = 50 pF; f = 1 MHz;
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
1999 Sep 01
AHCT
2
Philips Semiconductors
Product specification
74AHC139;
74AHCT139
Dual 2-to-4 line decoder/demultiplexer
FUNCTION TABLE
See note 1.
INPUTS
OUTPUTS
nE
nA0
nA1
nY0
nY1
nY2
nY3
H
X
X
H
H
H
H
L
L
L
L
H
H
H
L
H
L
H
L
H
H
L
L
H
H
H
L
H
L
H
H
H
H
H
L
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
PACKAGES
NORTH AMERICA
PINS
PACKAGE
MATERIAL
CODE
16
SO
plastic
SOT109-1
74AHC139D
74AHC139D
74AHC139PW
74AHC139PW DH
16
TSSOP
plastic
SOT403-1
74AHCT139D
74AHCT139D
16
SO
plastic
SOT109-1
74AHCT139PW
74AHCT139PW DH
16
TSSOP
plastic
SOT403-1
PINNING
PIN
SYMBOL
DESCRIPTION
1 and 15
1E and 2E
enable inputs (active LOW)
2 and 3
1A0 and 1A1
address inputs
4, 5, 6 and 7
1Y0, 1Y1, Y2 and 1Y3
outputs (active LOW)
8
GND
ground (0 V)
9, 10, 11 and 12
2Y3, 2Y2, 2Y1 and 2Y0
outputs (active LOW)
13 and 14
2A1 and 2A0
address inputs
16
VCC
DC supply voltage
1999 Sep 01
3
Philips Semiconductors
Product specification
74AHC139;
74AHCT139
Dual 2-to-4 line decoder/demultiplexer
handbook, halfpage
1
handbook, halfpage
16 VCC
1E 1
1E
15 2E
1A0 2
1A1 3
2
14 2A0
1Y0 4
3
13 2A1
139
1Y2 6
11 2Y1
1Y3 7
10 2Y2
GND 8
9 2Y3
14
13
1
3
14
13
15
DX 0
0 1
G
3
1
2
0
3
(a)
1Y2
4
5
6
7
2
3
1
10
9
14
13
15
2A0
2Y1
2A1
2Y2
2Y3
1
1
2
2
EN
3
X/Y 0
1
1
2
2
EN
3
(b)
4
5
6
7
12
11
10
9
MNA466
Fig.2 Logic symbol.
X/Y 0
12
11
2Y0
15
handbook, halfpage
3
1A1
2E
Fig.1 Pin configuration.
2
1Y1
1Y3
MNA465
DX 0
0
0 1
G
3
1
2
1A0
12 2Y0
1Y1 5
handbook, halfpage
1Y0
4
5
1Y0
4
2
1A0
1Y1
5
3
1A1
1Y2
6
1Y3
7
6
7
1
1E
14
2A0
2Y1 11
13
2A1
2Y2 10
12
2Y0 12
11
10
9
2Y3
MNA467
15
9
2E
MNA468
Fig.3 IEC logic symbol.
1999 Sep 01
Fig.4 Functional diagram.
4
Philips Semiconductors
Product specification
74AHC139;
74AHCT139
Dual 2-to-4 line decoder/demultiplexer
RECOMMENDED OPERATING CONDITIONS
74AHC
SYMBOL
PARAMETER
74AHCT
CONDITIONS
UNIT
MIN.
TYP. MAX. MIN.
TYP. MAX.
4.5
5.0
5.5
V
VCC
DC supply voltage
2.0
5.0
5.5
VI
input voltage
0
−
5.5
0
−
5.5
V
VO
output voltage
0
−
VCC
0
−
VCC
V
Tamb
operating ambient
temperature
−40
+25
+85
−40
+25
+85
°C
−40
+25
+125 −40
+25
+125 °C
−
−
100
−
−
−
−
−
20
−
−
20
tr,tf (∆t/∆f)
see DC and AC
characteristics per device
input rise and fall ratio VCC = 3.3 ±0.3 V
VCC = 5 ±0.5 V
ns/V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
MIN. MAX. UNIT
VCC
DC supply voltage
−0.5
+7.0
V
VI
input voltage
−0.5
+7.0
V
IIK
DC input diode current
VI < −0.5 V; note 1
−
−20
mA
IOK
DC output diode current
VO < −0.5 V or VO > VCC + 0.5 V; note 1
−
±20
mA
IO
DC output source or sink current
−0.5 V < VO < VCC + 0.5 V
−
±25
mA
ICC
DC VCC or GND current
−
±75
mA
Tstg
storage temperature
−65
+150 °C
PD
power dissipation per package
−
500
for temperature range: −40 to +125 °C;
note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO package: above 70 °C the value of PD derates linearly with 8 mW/K.
For TSSOP package: above 60 °C the value of PD derates linearly with 5.5 mW/K.
1999 Sep 01
5
mW
Philips Semiconductors
Product specification
74AHC139;
74AHCT139
Dual 2-to-4 line decoder/demultiplexer
DC CHARACTERISTICS
Family 74AHC
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
Tamb (°C)
TEST CONDITIONS
SYMBOL
OTHER
VIH
VIL
VOH
VOL
−40 to +85
25
PARAMETER
HIGH-level input
voltage
LOW-level input
voltage
HIGH-level output
voltage; all
outputs
VI = VIH or VIL;
IO = −50 µA
HIGH-level output
voltage
VCC (V)
MIN.
TYP.
−40 to +125 UNIT
MAX. MIN. MAX. MIN. MAX.
2.0
1.5
−
−
1.5
−
1.5
−
3.0
2.1
−
−
2.1
−
2.1
−
5.5
3.85 −
−
3.85 −
3.85 −
2.0
−
−
0.5
−
0.5
−
0.5
3.0
−
−
0.9
−
0.9
−
0.9
5.5
−
−
1.65
−
1.65
−
1.65
2.0
1.9
2.0
−
1.9
−
1.9
−
V
V
V
3.0
2.9
3.0
−
2.9
−
2.9
−
4.5
4.4
4.5
−
4.4
−
4.4
−
VI = VIH or VIL;
IO = −4.0 mA
3.0
2.58 −
−
2.48 −
2.40 −
VI = VIH or VIL;
IO = −8.0 mA
4.5
3.94 −
−
3.8
−
3.70 −
LOW-level output
voltage; all
outputs
VI = VIH or VIL;
IO = 50 µA
2.0
−
0
0.1
−
0.1
−
0.1
3.0
−
0
0.1
−
0.1
−
0.1
4.5
−
0
0.1
−
0.1
−
0.1
LOW-level output
voltage
VI = VIH or VIL;
IO = 4.0 mA
3.0
−
−
0.36
−
0.44
−
0.55
VI = VIH or VIL;
IO = 8.0 mA
4.5
−
−
0.36
−
0.44
−
0.55
−
1.0
−
2.0
±2.5
−
±10.0 µA
V
V
V
II
input leakage
current
VI = VCC or GND
5.5
−
−
0.1
IOZ
3-state output
OFF current
VI = VIH or VIL;
5.5
VO = VCC or GND
−
−
±0.25 −
ICC
quiescent supply
current
VI = VCC or GND;
IO = 0
5.5
−
−
4.0
−
40
−
80
µA
CI
input capacitance
−
−
3
10
−
10
−
10
pF
1999 Sep 01
6
µA
Philips Semiconductors
Product specification
74AHC139;
74AHCT139
Dual 2-to-4 line decoder/demultiplexer
Family 74AHCT
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
Tamb (°C)
TEST CONDITIONS
SYMBOL
−40 to +85
25
PARAMETER
VCC (V)
OTHER
−40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VIH
HIGH-level input
voltage
4.5 to 5.5
2.0
−
−
2.0
−
2.0
−
V
VIL
LOW-level input
voltage
4.5 to 5.5
−
−
0.8
−
0.8
−
0.8
V
VOH
HIGH-level
output voltage;
all outputs
VI = VIH or VIL;
IO = −50 µA
4.5
4.4
4.5
−
4.4
−
4.4
−
V
HIGH-level
output voltage
VI = VIH or VIL;
IO = −8.0 mA
4.5
3.94
−
−
3.8
−
3.70 −
V
LOW-level
output voltage;
all outputs
VI = VIH or VIL;
IO = 50 µA
4.5
−
0
0.1
−
0.1
−
0.1
V
LOW-level
output voltage
VI = VIH or VIL;
IO = 8.0 mA
4.5
−
−
0.36
−
0.44
−
0.55
V
II
input leakage
current
VI = VIH or VIL
5.5
−
−
0.1
−
1.0
−
2.0
µA
IOZ
3-state output
OFF current
VI = VIH or VIL;
5.5
VO = VCC or GND
per input pin;
other inputs at
VCC or GND;
IO = 0
−
−
±0.25 −
±2.5
−
±10.0 µA
ICC
quiescent supply VI = VCC or GND; 5.5
current
IO = 0
−
−
4.0
−
40
−
80
µA
∆ICC
additional
quiescent supply
current per input
pin
4.5 to 5.5
−
−
1.35
−
1.5
−
1.5
mA
CI
input
capacitance
−
−
3
10
−
10
−
10
pF
VOL
1999 Sep 01
VI = VCC − 2.1 V;
other inputs at
VCC or GND;
IO = 0
7
Philips Semiconductors
Product specification
74AHC139;
74AHCT139
Dual 2-to-4 line decoder/demultiplexer
AC CHARACTERISTICS
Type 74AHC139
Ground = 0 V; tr = tf ≤ 3.0 ns.
Tamb (°C)
TEST CONDITIONS
SYMBOL
−40 to +85
25
PARAMETER
WAVEFORMS
CL
MIN.
−40 to +125 UNIT
TYP.
MAX. MIN. MAX. MIN. MAX.
VCC = 3.0 to 3.6 V; note 1
tPHL/tPLH
propagation delay
nAn to nYn
see Figs 5 and 7
15 pF −
5.5
11.0
1.0
13.0
1.0
14.0
ns
propagation delay
nE to nYn
see Figs 6 and 7
−
4.8
9.2
1.0
11.0
1.0
11.5
ns
propagation delay
nAn to nYn
see Figs 5 and 7
50 pF −
7.9
14.5
1.0
16.5
1.0
18.5
ns
propagation delay
nE to nYn
see Figs 6 and 7
−
6.9
12.7
1.0
14.5
1.0
16.0
ns
propagation delay
nAn to nYn
see Figs 5 and 7
15 pF −
3.9
7.2
1.0
8.5
1.0
9.0
ns
propagation delay
nE to nYn
see Figs 6 and 7
−
3.4
6.3
1.0
7.5
1.0
8.0
ns
propagation delay
nAn to nYn
see Figs 5 and 7
50 pF −
5.6
9.2
1.0
10.5
1.0
11.5
ns
propagation delay
nE to nYn
see Figs 6 and 7
−
4.9
8.3
1.0
9.5
1.0
10.5
ns
VCC = 4.5 to 5.5 V; note 2
tPHL/tPLH
Notes
1. Typical values at VCC = 3.3 V.
2. Typical values at VCC = 5.0 V.
1999 Sep 01
8
Philips Semiconductors
Product specification
74AHC139;
74AHCT139
Dual 2-to-4 line decoder/demultiplexer
Type 74AHCT139
Ground = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
SYMBOL
Tamb (°C)
PARAMETER
−40 to +85
25
WAVEFORMS
CL
−40 to +125
UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC = 4.5 to 5.5 V; note 1
tPHL/tPLH
propagation delay
nAn to nYn
see Figs 5 and 7
15 pF −
4.7
7.2
1.0
8.5
1.0
9.0
ns
propagation delay
nE to nYn
see Figs 6 and 7
−
3.6
6.3
1.0
7.5
1.0
8.0
ns
propagation delay
nAn to nYn
see Figs 5 and 7
50 pF −
6.5
9.2
1.0
10.5
1.0
11.5
ns
propagation delay
nE to nYn
see Figs 6 and 7
−
5.2
8.3
1.0
9.5
1.0
10.5
ns
Note
1. Typical values at VCC = 5.0 V.
1999 Sep 01
9
Philips Semiconductors
Product specification
74AHC139;
74AHCT139
Dual 2-to-4 line decoder/demultiplexer
AC WAVEFORMS
nAn INPUT
VM(1)
nE INPUT
VM(1)
GND
GND
t PHL
t PHL
t PLH
VOL
VOL
MNA469
FAMILY
VI INPUT
REQUIREMENTS
AHC
GND to VCC
AHCT
GND to 3.0 V
VM(1)
nYn OUTPUT
VM(1)
nYn OUTPUT
VM
INPUT
VM
OUTPUT
MNA470
FAMILY
VI INPUT
REQUIREMENTS
50% VCC 50% VCC
AHC
GND to VCC
50% VCC 50% VCC
1.5 V
AHCT
GND to 3.0 V
1.5 V
50% VCC
The address input (nAn) to output (nYn)
propagation delays.
Fig.6
VCC
PULSE
GENERATOR
VI
1000 Ω
VO
VCC
open
GND
D.U.T.
CL
RT
MNA219
TEST
S1
tPLH/tPHL
open
tPLZ/tPZL
VCC
tPHZ/tPZH
GND
Definitions for test circuit:
CL = Load capacitance including jig and probe capacitance.
(See Chapter “AC characteristics” for values).
RT = Termination resistance should be equal to the output
impedance Zo of the pulse generator.
Fig.7 Load circuitry for switching times.
10
VM
INPUT
VM
OUTPUT
50% VCC
The enable input (nE) to output (nYn)
propagation delays.
S1
handbook, full pagewidth
1999 Sep 01
t PLH
VOH
VOH
Fig.5
VI
handbook, halfpage
VI
handbook, halfpage
Philips Semiconductors
Product specification
74AHC139;
74AHCT139
Dual 2-to-4 line decoder/demultiplexer
PACKAGE OUTLINES
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.050
0.039
0.016
0.028
0.020
0.01
0.01
0.004
0.028
0.012
inches
0.244
0.041
0.228
θ
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07S
MS-012AC
1999 Sep 01
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-23
97-05-22
11
o
8
0o
Philips Semiconductors
Product specification
74AHC139;
74AHCT139
Dual 2-to-4 line decoder/demultiplexer
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.10
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1.0
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
1999 Sep 01
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
94-07-12
95-04-04
MO-153
12
o
Philips Semiconductors
Product specification
74AHC139;
74AHCT139
Dual 2-to-4 line decoder/demultiplexer
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Sep 01
13
Philips Semiconductors
Product specification
74AHC139;
74AHCT139
Dual 2-to-4 line decoder/demultiplexer
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
suitable(2)
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Sep 01
14
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
NOTES
1999 Sep 01
15
74AHC139;
74AHCT139
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SCA 67
© Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Printed in The Netherlands
245002/01/pp16
Date of release: 1999
Sep 01
Document order number:
9397 750 06157