INTEGRATED CIRCUITS 74ALVCH16821 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) Product specification IC24 Data Handbook 1998 May 29 Philips Semiconductors Product specification 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ALVCH16821 FEATURES DESCRIPTION • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A • Current drive ± 24 mA at 3.0 V • CMOS low power consumption • Direct interface with TTL levels • MULTIBYTETM flow-through standard pin-out architecture • Low inductance multiple VCC and ground pins for minimum noise The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. Each register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output. When nOE is LOW, the data in the register appears at the outputs. When nOE is HIGH, the outputs are in high impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops. and ground bounce The 74ALVCH16821 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. • All data inputs have bus hold • Output drive capability 50Ω transmission lines @ 85°C QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns PARAMETER SYMBOL CONDITIONS tPHL/tPLH Propagation delay nCP to nQn CI Input capacitance CPD Power dissipation capacitance per buffer VI = GND to VCC1 Fmax Maximum clock frequency VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF TYPICAL UNIT 2.6 2.5 ns 5.0 pF VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF Outputs enabled 33 Outputs disabled 17 250 350 pF MHz NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 56-Pin Plastic SSOP Type III –40°C to +85°C 74ALVCH16821 DL ACH16821 DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVCH16821 DGG ACH16821 DGG SOT364-1 1998 May 29 2 853-2066 19467 Philips Semiconductors Product specification 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ALVCH16821 PIN DESCRIPTION FUNCTION TABLE PIN NUMBER SYMBOL 55, 54, 52, 51, 49, 48, 47, 45, 44, 43 1D0 - 1D9 42, 41, 40, 38, 37, 36, 34, 33, 31, 30 2D0 - 2D9 2, 3, 5, 6, 8, 9, 10, 12, 13, 14 1Q0 - 1Q9 FUNCTION INPUTS nOE CP L ↑ L L L ↑ H H L X Q0 Data in inputs uts Data outputs out uts 15, 16, 17, 19, 20, 21, 23, 24, 26, 27 2Q0 - 2Q9 1, 28 1OE, 2OE Output enable inputs (active-Low) 56, 29 1CP, 2CP Clock pulse inputs (active rising edge) 4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V) 7, 22, 35, 50 VCC Positive supply voltage H L X Z ↑ OUTPUT = = = = = = Dx Q H X X HIGH voltage level LOW voltage level Don’t care High impedance OFF state LOW to HIGH clock transition Not a LOW-to-HIGH clock transition Z LOGIC SYMBOL PIN CONFIGURATION 2 1Q0 3 1 56 1OE 1CP 1D0 55 1Q1 1D1 54 1D2 52 1OE 1 56 1CP 5 1Q2 1Q0 2 55 1D0 6 1Q3 1D3 51 1Q1 3 54 1D1 8 1Q4 1D4 49 GND 4 53 GND 9 1Q5 1D5 48 1Q2 5 52 1D2 1Q3 6 51 1D3 10 1Q6 1D6 47 VCC 7 50 VCC 12 1Q7 1D7 45 1Q4 8 49 1D4 13 1Q8 1D8 44 1Q5 9 48 1D5 14 1Q9 1D9 43 1Q6 10 47 1D6 15 2Q0 2D0 42 GND 11 46 GND 1Q7 12 45 1D7 16 2Q1 2D1 41 1Q8 13 44 1D8 17 2Q2 2D2 40 1Q9 14 43 1D9 19 2Q3 2D3 38 2Q0 15 42 2D0 20 2Q4 2D4 37 2Q1 16 41 2D1 21 2Q5 17 40 2D2 2D5 36 2Q2 23 2Q6 2D6 34 GND 18 39 GND 2Q3 19 38 2D3 24 2Q7 2D7 33 2Q4 20 37 2D4 26 2Q8 2D8 31 2Q5 21 36 2D5 27 2Q9 2D9 30 VCC 22 35 VCC 2Q6 23 34 2D6 2Q7 24 33 2D7 GND 25 32 GND 2Q8 26 31 2D8 2Q9 27 30 2D9 2OE 28 29 2CP 2OE 2CP 28 29 SH00127 SH00001 1998 May 29 3 Philips Semiconductors Product specification 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ALVCH16821 LOGIC SYMBOL (IEEE/IEC) 1OE 1 1CP 56 2OE 28 2CP 29 1D0 55 2 1Q0 1D1 54 3 1Q1 1D2 52 5 1Q2 1D3 51 6 1Q3 1D4 49 8 1Q4 1D5 48 9 1Q5 1D6 47 10 1Q6 1D7 45 12 1Q7 1D8 44 13 1Q8 1D9 43 14 1Q9 2D0 42 15 2Q0 2D1 41 16 2Q1 2D2 40 17 2Q2 2D3 38 19 2Q3 2D4 37 20 2Q4 2D5 36 21 2Q5 2D6 34 23 2Q6 2D7 33 24 2Q7 2D8 31 26 2Q8 2D9 30 27 2Q9 EN2 C1 EN4 C3 2∇ 1D 4∇ 3D SH00003 LOGIC DIAGRAM nD0 nD1 nD2 nD3 nD4 nD5 nD6 nD7 nD8 nD9 D D D D D D D D D D CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q nCP nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 nQ9 SH00004 1998 May 29 4 Philips Semiconductors Product specification 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ALVCH16821 RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC PARAMETER CONDITIONS UNIT MIN MAX DC supply voltage 2.5V range (for max. speed performance @ 30 pF output load) 2.3 2.7 DC supply voltage 3.3V range (for max. speed performance @ 50 pF output load) 3.0 3.6 V VI DC Input voltage range 0 VCC V VO DC output voltage range 0 VCC V –40 +85 °C 0 0 20 10 ns/V Tamb Operating free-air temperature range tr, tf Input rise and fall times VCC = 2.3 to 3.0V VCC = 3.0 to 3.6V ABSOLUTE MAXIMUM RATINGS In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK PARAMETER CONDITIONS DC supply voltage DC input diode current VI 0 DC output diode current VO VCC or VO 0 DC output voltage Note 1 IO DC output source or sink current VO = 0 to VCC DC VCC or GND current Storage temperature range For temperature range: –40 to +125 °C above +55°C derate linearly with 11.3 mW/K above +55°C derate linearly with 8 mW/K NOTE: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 May 29 –50 mA –0.5 to VCC +0.5 VO Power dissipation per package –plastic medium-shrink (SSOP) –plastic thin-medium-shrink (TSSOP) V For data inputs1 IOK PTOT –0.5 to +4.6 –0.5 to +4.6 DC in input ut voltage Tstg UNIT For control pins1 VI IGND, ICC RATING 5 V 50 mA –0.5 to VCC +0.5 V 50 mA 100 mA –65 to +150 °C 850 600 mW Philips Semiconductors Product specification 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ALVCH16821 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER VIH HIGH level Input voltage VIL LOW level Input voltage VOH O HIGH level output voltage TEST CONDITIONS Temp = -40°C to +85°C MIN TYP1 VCC = 2.3 to 2.7V 1.7 1.2 VCC = 2.7 to 3.6V 2.0 1.5 UNIT MAX V VCC = 2.3 to 2.7V 1.2 0.7 VCC = 2.7 to 3.6V 1.5 0.8 V 3 to 3 6V; VI = VIH or VIL; IO = –100µA 100µA VCC = 2 2.3 3.6V; 02 VCC0.2 VCC VCC = 2.3V; VI = VIH or VIL; IO = –6mA VCC0.3 VCC0.08 VCC = 2.3V; VI = VIH or VIL; IO = –12mA VCC0.6 VCC0.26 VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC0.5 VCC0.14 VCC = 3.0V; VI = VIH or VIL; IO = –12mA VCC0.6 VCC0.09 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC1.0 VCC0.28 V VCC = 2 2.3 3 to 3 3.6V; 6V; VI = VIH or VIL; IO = 100µA GND 0 20 0.20 V VCC = 2.3V; VI = VIH or VIL; IO = 6mA 0.07 0.40 V VCC = 2.3V; VI = VIH or VIL; IO = 12mA 0.15 0.70 VCC = 2.7V; VI = VIH or VIL; IO = 12mA 0.14 0.40 VCC = 3.0V; VI = VIH or VIL; IO = 24mA 0.27 0.55 Input leakage g current VCC = 2 2.3 3 to 3 3.6V; 6V; VI = VCC or GND 0.1 5 µA µ IOZ 3-State output OFF-state current VCC = 2.7 to 3.6V; VI = VIH or VIL; VO = VCC or GND 0.1 10 µA ICC Quiescent supply current VCC = 2.3 to 3.6V; VI = VCC or GND; IO = 0 0.2 40 µA ∆ICC Additional quiescent supply current VCC = 2.3V to 3.6V; VI = VCC – 0.6V; IO = 0 150 750 µA IBHL Bus hold LOW sustaining current IBHH Bus hold HIGH sustaining current IBHLO Bus hold LOW overdrive current VCC = 3.6V2 500 µA IBHHO Bus hold HIGH overdrive current VCC = 3.6V2 –500 µA VOL II LOW level output voltage VCC = 2.3V; VI = 0.7V2 45 – 0.8V2 75 150 VCC = 2.3V; VI = 1.7V2 –45 2.0V2 –75 VCC = 3.0V; VI = VCC = 3.0V; VI = NOTES: 1. All typical values are at Tamb = 25°C. 2. Valid for data inputs of bus hold parts. 1998 May 29 6 –175 V µA µA Philips Semiconductors Product specification 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ALVCH16821 AC CHARACTERISTICS FOR VCC = 2.3V TO 2.7V RANGE GND = 0V; tr = tf ≤ 2.0ns; CL = 30pF LIMITS SYMBOL PARAMETER VCC = 2.5V ± 0.2V WAVEFORM UNIT MIN TYP1 MAX tPLH/tPHL Propagation delay nCP to nQn 1, 4 1.0 2.6 5.8 ns tPZH/tPZL 3-State output enable time nOEn to nQn 2, 4 1.0 2.8 6.6 ns tPHZ/tPLZ 3-State output disable time nOEn to nQn 2, 4 1.0 2.2 5.7 ns tW nCP pulse width HIGH or LOW 3, 4 3.0 1.8 ns tSU Set up time nDn to nCP 3, 4 1.4 0.3 ns Hold time nDn to nCP 3, 4 0.4 0.0 ns Maximum clock pulse frequency 1, 4 150 250 MHz th Fmax NOTE: 1. All typical values are at VCC = 2.5V and Tamb = 25°C. AC CHARACTERISTICS FOR VCC = 3.0V TO 3.6V RANGE AND VCC = 2.7V GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF LIMITS SYMBOL PARAMETER VCC = 3.3 ± 0.3V WAVEFORM VCC = 2.7V UNIT MIN TYP1 MAX MIN TYP1 MAX tPHL/tPLH Propagation delay nCP to nQn 1, 4 1.0 2.5 4.5 1.0 2.8 5.3 ns tPZH/tPZL 3-State output enable time nOEn to nQn 2, 4 1.0 2.3 5.1 1.0 3.2 6.2 ns tPHZ/tPLZ 3-State output disable time nOEn to nQn 2, 4 1.0 2.8 4.6 1.0 3.1 5.0 ns tW nCP pulse width HIGH or LOW 3, 4 3.3 0.2 3.3 1.7 ns tSU Set up time nDn to nCP 3, 4 1.0 0.2 1.2 0.3 ns th Hold time nDn to nCP 3, 4 0.8 0.4 0.6 –0.3 ns Fmax Maximum clock pulse frequency 1, 4 150 350 150 300 MHz NOTES: 1. All typical values are at Tamb = 25°C. 1998 May 29 7 Philips Semiconductors Product specification 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ALVCH16821 AC WAVEFORMS VCC = 2.3 TO 2.7 V RANGE 1. VM = 0.5 V 2. VX = VOL + 0.15V 3. VY = VOH – 0.15V 4. VI = VCC 5. VOL and VOH are the typical output voltage drop that occur with the output load. VCC = 3.0 TO 3.6 V RANGE AND VCC = 2.7 V 1. VM = 1.5 V 2. VX = VOL + 0.3V 3. VY = VOH – 0.3V 4. VI = 2.7 V 5. VOL and VOH are the typical output voltage drop that occur with the output load. VI VM nCP INPUT GND tsu tsu th th VI VM nDn INPUT GND VOH nQn OUTPUT VOL VM SH00129 Waveform 3. Set up and hold times. TEST CIRCUIT 1/fMAX VI nCP INPUT GND tw tPLH tPHL VOH nQn OUTPUT VM PULSE GENERATOR 2 * VCC Open GND RL = 500 Ω VO VI VM VOL D.U.T. RT SH00128 Waveform 1. S1 VCC VM RL = 500 Ω CL The input (nCP) to output propagation delays. Test Circuit for switching times DEFINITIONS VI RL = Load resistor nOE INPUT CL = Load capacitance includes jig and probe capacitance VM RT = Termination resistance should be equal to ZOUT of pulse generators. GND SWITCH POSITION tPLZ TEST tPZL tPLH/tPHL VCC OUTPUT LOW-to-OFF OFF-to-LOW VM VX S1 Open tPLZ/tPZL 2 VCC tPHZ/tPZH GND VCC VI < 2.7V VCC 2.7–3.6V 2.7V VOL SV00906 tPHZ tPZH Waveform 4. Load circuitry for switching times VOH OUTPUT HIGH-to-OFF OFF-to-HIGH VY VM GND outputs enabled outputs disabled outputs enabled SW00308 Waveform 2. The 3-State enable and disable times. 1998 May 29 8 Philips Semiconductors Product specification 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ALVCH16821 SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm 1998 May 29 9 SOT371-1 Philips Semiconductors Product specification 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ALVCH16821 TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm 1998 May 29 10 SOT364-1 Philips Semiconductors Product specification 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ALVCH16821 NOTES 1998 May 29 11 Philips Semiconductors Product specification 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ALVCH16821 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: 1998 May 29 12 Date of release: 05-96 9397-750-04553