54F/74F533 Octal Transparent Latch with TRI-STATEÉ Outputs General Description Features The ’F533 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The ’F533 is the same as the ’F373, except that the outputs are inverted. Y Commercial Y Y Y Eight latches in a single package TRI-STATE outputs for bus interfacing Inverted version of the ’F373 Guaranteed 4000V minimum ESD protection Package Number Military 74F533PC 54F533DM (Note 2) 74F533SC (Note 1) Package Description N20A 20-Lead (0.300× Wide) Molded Dual-In-Line J20A 20-Lead Ceramic Dual-In-Line M20B 20-Lead (0.300× Wide) Molded Small Outline, JEDEC M20D 20-Lead (0.300× Wide) Molded Small Outline, EIAJ 54F533FM (Note 2) W20A 20-Lead Cerpack 54F533LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C 74F533SJ (Note 1) Note 1: Devices also available in 13× reel. Use suffix e SCX and SJX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Logic Symbols Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak IEEE/IEC Pin Assignment for LCC TL/F/9548 – 3 TL/F/9548–4 TL/F/9548 – 2 TL/F/9548–1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9548 RRD-B30M75/Printed in U. S. A. 54F/74F533 Octal Transparent Latch with TRI-STATE Outputs May 1995 Unit Loading/Fan Out 54F/74F Pin Names D0 – D7 LE OE O0 – O 7 Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) Complementary TRI-STATE Outputs 1.0/1.0 1.0/1.0 1.0/1.0 150/40 (33.3) 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b0.6 mA b 3 mA/24 mA (20 mA) Function Table Inputs Output LE OE D O H H L X L L L H H L X X L H O0 Z H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Functional Description puts a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. The ’F533 contains eight D-type latches with TRI-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D in- Logic Diagram TL/F/9548 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55§ C to a 125§ C Free Air Ambient Temperature Military Commercial b 55§ C to a 125§ C 0§ C to a 70§ C Supply Voltage Military Commercial b 55§ C to a 175§ C b 55§ C to a 150§ C a 4.5V to a 5.5V a 4.5V to a 5.5V VCC Pin Potential to Ground Pin b 0.5V to a 7.0V b 0.5V to a 7.0V Input Voltage (Note 2) b 30 mA to a 5.0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) ESD Last Passing Voltage (Min) 4000V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol 54F/74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage Typ Units 2.0 54F 10% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 74F 5% VCC 74F 5% VCC VCC Conditions Max V Recognized as a HIGH Signal 0.8 V Recognized as a LOW Signal b 1.2 V 2.5 2.4 2.5 2.4 2.7 2.7 Min IIN e b18 mA V Min IOH IOH IOH IOH IOH IOH e e e e e e b 1 mA b 3 mA b 1 mA b 3 mA b 1 mA b 3 mA VOL Output LOW Voltage 54F 10% VCC 74F 10% VCC 0.5 0.5 V Min IOL e 20 mA IOL e 24 mA IIH Input HIGH Current 54F 74F 20.0 5.0 mA Max VIN e 2.7V IBVI Input HIGH Current Breakdown Test 54F 74F 100 7.0 mA Max VIN e 7.0V IBVIT Input HIGH Current Breakdown (I/O) 54F 74F 1.0 0.5 mA Max VIN e 5.5V ICEX Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC VID Input Leakage Test 74F V 0.0 IID e 1.9 mA All Other Pins Grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 150 mV All Other Pins Grounded IIL Input LOW Current b 0.6 mA Max VIN e 0.5V IOZH Output Leakage Current 50 mA Max VOUT e 2.7V IOZL Output Leakage Current IOS Output Short-Circuit Current IZZ Bus Drainage Test ICCZ Power Supply Current 4.75 b 60 41 3 b 50 mA Max VOUT e 0.5V b 150 mA Max VOUT e 0V 500 mA 0.0V VOUT e 5.25V 61 mA Max VO e HIGH Z AC Electrical Characteristics Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Units Min Typ Max Min Max Min Max tPLH tPHL Propagation Delay Dn to On 4.0 2.5 6.7 4.4 9.0 7.0 4.0 2.5 12.0 9.0 4.0 2.5 10.0 8.0 ns tPLH tPHL Propagation Delay LE to On 5.0 3.0 7.1 4.7 11.0 7.0 5.0 3.0 14.0 9.0 5.0 3.0 13.0 8.0 ns tPZH tPZL Output Enable Time 2.0 2.0 5.9 5.6 10.0 7.5 2.0 2.0 12.5 10.5 2.0 2.0 11.0 8.5 ns tPHZ tPLZ Output Disable Time 1.5 1.5 3.4 2.7 6.5 5.5 1.5 1.5 8.5 7.5 1.5 1.5 7.0 6.5 ns AC Operating Requirements Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V TA, VCC e Mil TA, VCC e Com Min Min Min Max Max Units Max ts(H) ts(L) Setup Time, HIGH or LOW Dn to LE 2.0 2.0 2.0 2.0 2.0 2.0 ns th(H) th(L) Hold Time, HIGH or LOW Dn to LE 3.0 3.0 3.0 3.0 3.0 3.0 ns tw(H) LE Pulse Width, HIGH 6.0 6.0 6.0 ns Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows: 74F 533 S Temperature Range Family 74F e Commercial 54F e Military C X Special Variations X e Devices shipped in 13× reels QB e Military grade device with environmental and burn-in processing shipped in tubes Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) 4 Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E20A 20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 5 Physical Dimensions inches (millimeters) (Continued) 20-Lead (0.300× Wide) Molded Small Outline Package, JEDEC (S) NS Package Number M20B 20-Lead (0.300× Wide) Molded Small Outline Package, EIAJ (SJ) NS Package Number M20D 6 Physical Dimensions inches (millimeters) (Continued) 20-Lead (0.300× Wide) Molded Dual-In-Line Package (P) NS Package Number N20A 7 54F/74F533 Octal Transparent Latch with TRI-STATE Outputs Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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