INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT40102 8-bit synchronous BCD down counter Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 8-bit synchronous BCD down counter 74HC/HCT40102 When the synchronous preset enable input (PE) is LOW, data at the jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition regardless of the state of TE. When the asynchronous preset enable input (PL) is LOW, data at the jam input (P0 to P7) is asynchronously forced into the counter regardless of the state of PE, TE, or CP. The jam inputs (P0 to P7) represent two 4-bit BCD words. FEATURES • Cascadable • Synchronous or asynchronous preset • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION When the master reset input (MR) is LOW, the counter is asynchronously cleared to its maximum count (decimal 99) regardless of the state of any other input. The precedence relationship between control inputs is indicated in the function table. The 74HC/HCT40102 are high-speed Si-gate CMOS devices and are pin compatible with the “40102” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40102 consist each of an 8-bit synchronous down counter with a single output which is active when the internal count is zero. The “40102” is configured as two cascaded 4-bit BCD counters and has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count output (TC) are active-LOW logic. If all control inputs except TE are HIGH at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 100 clock pulses long. The “40102” may be cascaded using the TE input and the TC output, in either a synchronous or ripple mode. In normal operation, the counter is decremented by one count on each positive-going transition of the clock (CP). Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW for one full clock period. • Programmable timers APPLICATIONS • Divide-by-n counters • Interrupt timers • Cycle/program counters QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay CP to TC fmax maximum clock frequency CI input capacitance CPD power dissipation capacitance per package CL = 15 pF; VCC = 5 V notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V December 1990 2 HCT 30 31 ns 30 30 MHz 3.5 3.5 pF 20 25 pF Philips Semiconductors Product specification 8-bit synchronous BCD down counter 74HC/HCT40102 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 CP clock input (LOW-to-HIGH, edge-triggered) 2 MR asynchronous master reset input (active LOW) 3 TE terminal enable input 4, 5, 6, 7, 10, 11, 12, 13 P0 to P7 jam inputs 8 GND ground (0 V) 9 PL asynchronous preset enable input (active LOW) 14 TC terminal count output (active LOW) 15 PE synchronous preset enable input (active LOW) 16 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification 8-bit synchronous BCD down counter 74HC/HCT40102 Fig.4 Functional diagram. FUNCTION TABLE CONTROL INPUTS PRESET MODE MR PL PE TE H H H H H H H L H H L X H L X X L X X X ACTION inhibit counter synchronous count down preset on next LOW-to HIGH clock transition asynchronous preset asynchronously clear to maximum count Notes 1. Clock connected to CP. 2. Synchronous operation: changes occur on the LOW-to-HIGH CP transition. 3. Jam inputs: MSD = P7, LSD = P0. H = HIGH voltage level L = LOW voltage level X = don’t care December 1990 4 Philips Semiconductors Product specification 8-bit synchronous BCD down counter 74HC/HCT40102 Fig.5 Logic diagram. Fig.6 Timing diagram. December 1990 5 Philips Semiconductors Product specification 8-bit synchronous BCD down counter 74HC/HCT40102 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 min. typ. max. min. max. −40 to +125 min. UNIT V WAVEFORMS CC (V) max. tPHL/ tPLH propagation delay CP to TC 96 35 28 300 60 51 375 75 64 450 90 77 ns 2.0 4.5 6.0 Fig.8 tPHL/ tPLH propagation delay TE to TC 50 18 14 200 40 34 250 50 43 300 60 51 ns 2.0 4.5 6.0 Fig.8 tPHL/ tPLH propagation delay Pn, PL to TC 110 40 32 240 68 58 425 85 72 510 102 87 ns 2.0 4.5 6.0 Fig.8 tPLH propagation delay MR to TC 83 30 24 275 55 47 345 69 59 415 83 71 ns 2.0 4.5 6.0 Fig.8 tTHL/ tTLH output transition time 9 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Figs 8 and 8 tW clock pulse width HIGH or LOW 165 33 28 22 8 6 205 41 35 250 50 43 ns 2.0 4.5 6.0 Fig.8 tW master reset pulse width LOW 150 30 26 30 11 9 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.8 tW preset enable pulse width PL; LOW 125 25 21 39 14 11 155 31 26 190 38 32 ns 2.0 4.5 6.0 Fig.8 trem removal time PL; MR to CP 50 10 9 8 3 2 65 13 11 75 15 13 ns 2.0 4.5 6.0 Fig.8 tsu set-up time PE to CP 100 20 17 36 13 10 125 25 21 150 30 26 ns 2.0 4.5 6.0 Fig.8 tsu set-up time TE to CP 175 35 30 50 18 14 220 44 37 265 53 45 ns 2.0 4.5 6.0 Fig.8 December 1990 6 Philips Semiconductors Product specification 8-bit synchronous BCD down counter 74HC/HCT40102 Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. WAVEFORMS UNIT V CC (V) max. tsu set-up time Pn to CP 100 20 17 33 12 10 125 25 21 150 30 26 ns 2.0 4.5 6.0 Fig.8 th hold time PE to CP 2 2 2 −8 −3 −2 2 2 2 2 2 2 ns 2.0 4.5 6.0 Fig.8 th hold time TE to CP 0 0 0 −41 −15 −12 0 0 0 0 0 0 ns 2.0 4.5 6.0 Fig.8 th hold time Pn to CP 2 2 2 −5 −5 −5 2 2 2 2 2 2 ns 2.0 4.5 6.0 Fig.8 fmax maximum clock pulse frequency 3 15 18 8.9 27 32 2 12 14 2 10 12 MHz 2.0 4.5 6.0 Fig.8 December 1990 7 Philips Semiconductors Product specification 8-bit synchronous BCD down counter 74HC/HCT40102 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT CP, PE MR TE Pn PL 1.50 1.00 0.80 0.25 0.35 December 1990 8 Philips Semiconductors Product specification 8-bit synchronous BCD down counter 74HC/HCT40102 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 −40 to +85 min. typ. max. min. max. −40 to +125 min. WAVEFORMS UNIT V CC (V) max. tPHL/ tPLH propagation delay Pn; CP to TC 38 63 79 95 ns 4.5 Figs 8 and 8 tPHL/ tPLH propagation delay TE to TC 25 50 63 75 ns 4.5 Fig.8 tPHL/ tPLH propagation delay PL to TC 49 83 104 125 ns 4.5 Fig.8 tPLH propagation delay MR to TC 31 55 69 83 ns 4.5 Fig.8 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Figs 8 and 8 tW clock pulse width HIGH or LOW 33 11 41 50 ns 4.5 Fig.8 tW master reset pulse width LOW 30 16 38 45 ns 4.5 Fig.8 tW preset enable pulse width 43 PL; LOW 25 54 65 ns 4.5 Fig.8 trem removal time PL; MR to CP 10 1 13 15 ns 4.5 Fig.8 tsu set-up time PE to CP 20 10 25 30 ns 4.5 Fig.8 tsu set-up time TE to CP 40 20 50 60 ns 4.5 Fig.8 tsu set-up time Pn to CP 20 12 25 30 ns 4.5 Fig.8 th hold time PE to CP 0 −4 0 0 ns 4.5 Fig.8 th hold time TE to CP 0 −15 0 0 ns 4.5 Fig.8 th hold time Pn to CP 0 −6 0 0 ns 4.5 Fig.8 fmax maximum clock pulse frequency 15 27 12 10 MHz 4.5 Fig.8 December 1990 9 Philips Semiconductors Product specification 8-bit synchronous BCD down counter 74HC/HCT40102 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Waveforms showing the clock input (CP) to TC propagation delays, the clock pulse width, the output transition times and the maximum clock pulse frequency. Fig.8 Waveforms showing the TE to TC propagation delays. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Fig.10 Waveforms showing removal time for MR and PL. Waveforms showing PL, MR, Pn to TC propagation delays. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.11 Waveforms showing hold and set-up times for MR or PE to CP. December 1990 Fig.12 Waveforms showing hold and set-up times for Pn, PE to CP. 10 Philips Semiconductors Product specification 8-bit synchronous BCD down counter APPLICATION INFORMATION Fig.13 Programmable timer. Fig.14 Divide-by-N counter. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 11 74HC/HCT40102