Revised August 2001 74LVTH16500 Low Voltage 18-Bit Universal Bus Transceivers with Bushold and 3-STATE Outputs General Description Features The LVTH16500 is an 18-bit universal bus transceiver combining D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. ■ Input and output interface capability to systems at 5V VCC Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The LVTH16500 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. The transceiver is designed for low voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH16500 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs ■ Live insertion/extraction permitted ■ Power up/down high impedance provides glitch-free bus loading ■ Outputs source/sink −32 mA/+64 mA ■ Functionally compatible with the 74 series 16500 ■ ESD Performance: Human-Body Model > 2000V Machine Model > 200V Charged-Device Model > 1000V ■ Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Ordering Code: Order Number 74LVTH16500GX (Note 1) Package Number BGA54A (Preliminary) Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 74LVTH16500MEA (Note 2) MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVTH16500MTD (Note 2) MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 1: BGA package available in Tape and Reel only. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix “X” to the ordering code. © 2001 Fairchild Semiconductor Corporation DS012447 www.fairchildsemi.com 74LVTH16500 Low Voltage 18-Bit Universal Bus Transceivers with Bushold and 3-STATE Outputs March 2001 74LVTH16500 Connection Diagrams Pin Descriptions Pin Names Pin Assignment for SSOP and TSSOP Description A1–A18 Data Register A Inputs/3-STATE Outputs B1–B18 Data Register B Inputs/3-STATE Outputs CLKAB, CLKBA Clock Pulse Inputs LEAB, LEBA Latch Enable Inputs OEAB, OEBA Output Enable Inputs FBGA Pin Assignments 1 2 3 4 5 6 A A2 A1 OEAB GND B1 B2 B A4 A3 LEAB CLKAB B3 B4 C A6 A5 VCC VCC B5 B6 D A8 A7 GND GND B7 B8 E A10 A9 GND GND B9 B10 F A12 A11 GND GND B11 B12 G A14 A13 VCC VCC B13 B14 H A16 A15 OEAB CLKBA B15 B16 J A17 A18 LEBA B18 B17 GND Function Table (Note 3) Inputs OEAB Pin Assignment for FBGA Output LEAB CLKAB An Bn Z L X X X H H X L L H H X H H H L ↓ L L H L ↓ H H H L H X B0 (Note 4) H L L X B0 (Note 5) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance ↓ = HIGH-to-LOW Clock Transition Note 3: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. OEBA is active LOW. Note 4: Output level before the indicated steady-state input conditions were established. Note 5: Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW. (Top Thru View) www.fairchildsemi.com 2 HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CLKAB. Output-enable OEAB is active-HIGH. When OEAB is Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active-HIGH and OEBA is active-LOW). Logic Diagram 3 www.fairchildsemi.com 74LVTH16500 Functional Description 74LVTH16500 Absolute Maximum Ratings(Note 6) Symbol Parameter Value Conditions Units VCC Supply Voltage −0.5 to +4.6 V VI DC Input Voltage −0.5 to +7.0 V VO DC Output Voltage −0.5 to +7.0 Output in 3-STATE V −0.5 to +7.0 Output in HIGH or LOW State (Note 7) IIK DC Input Diode Current −50 VI < GND IOK DC Output Diode Current −50 VO < GND IO DC Output Current 64 VO > VCC Output at HIGH State 128 VO > VCC Output at LOW State V mA mA mA ICC DC Supply Current per Supply Pin ±64 mA IGND DC Ground Current per Ground Pin ±128 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VI Input Voltage IOH HIGH-Level Output Current IOL LOW-Level Output Current TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V – 2.0V, VCC = 3.0V Min Max Units 2.7 3.6 V 0 5.5 V −32 mA 64 mA −40 85 °C 0 10 ns/V Note 6: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 7: IO Absolute Maximum Rating must be observed. www.fairchildsemi.com 4 Symbol VIK Input Clamp Diode Voltage T A = −40°C to +85°C VCC Parameter (V) Min Units Max −1.2 2.7 V VO ≤ 0.1V or VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC − 0.2 V IOH = −100 µA 2.7 2.4 V IOH = −8 mA 3.0 2.0 V IOH = −32 mA VOL II(HOLD) II(OD) Output LOW Voltage Bushold Input Minimum Drive Bushold Input Over-Drive Control Pins Data Pins IOFF Power Off Leakage Current IPU/PD Power Up/Down 3-STATE VO ≥ VCC − 0.1V 2.7 0.2 V IOL = 100 µA 2.7 0.5 V IOL = 24 mA 3.0 0.4 V IOL = 16 mA 3.0 0.5 V IOL = 32 mA 3.0 0.55 V IOL = 64 mA 75 µA VI = 0.8V −75 µA VI = 2.0V 500 µA (Note 8) −500 µA (Note 9) 3.0 Input Current V 0.8 3.0 Current to Change State II 2.0 Conditions II = −18 mA 3.6 10 µA VI = 5.5V 3.6 ±1 µA VI = 0V or VCC −5 µA VI = 0V 1 µA VI = VCC ±100 µA 3.6 0 0V ≤ VI or VO ≤ 5.5V VO = 0.5V to 3.0V 0–1.5V ±100 µA IOZL 3-STATE Output Leakage Current 3.6 −5 µA VO = 0.0V IOZH 3-STATE Output Leakage Current 3.6 5 µA VO = 3.6V IOZH+ 3-STATE Output Leakage Current 3.6 10 µA VCC < VO ≤ 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled ICCZ+ Power Supply Current 3.6 0.19 mA VCC ≤ VO ≤ 5.5V, ∆ICC Increase in Power Supply Current Output Current VI = GND or VCC Outputs Disabled 3.6 (Note 10) 0.2 mA One Input at VCC − 0.6V Other Inputs at VCC or GND Note 8: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 9: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 10: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol Parameter (Note 11) TA = 25°C VCC (V) Min Typ Conditions Max Units CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 12) VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.8 V (Note 12) Note 11: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 12: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW. 5 www.fairchildsemi.com 74LVTH16500 DC Electrical Characteristics 74LVTH16500 AC Electrical Characteristics TA = −40°C to +85°C, CL = 50 pF, RL = 500 Ω Symbol VCC = 3.3 ± 0.3V Parameter Min Max VCC = 2.7V Min fMAX CLKAB or CLKBA to B or A 150 tPLH Propagation Delay 1.3 5.2 1.3 5.8 tPHL Data to Outputs 1.3 4.7 1.3 5.3 tPLH Propagation Delay 1.5 5.5 1.5 6.3 tPHL LEBA or LEAB to B or A 1.5 5.1 1.5 5.7 tPLH Propagation Delay 1.3 5.8 1.3 6.9 tPHL CLKBA or CLKAB to B or A 1.2 5.0 1.3 5.9 tPZH Output Enable Time 1.2 5.0 1.3 5.7 1.3 5.5 1.3 6.5 1.7 6.0 1.7 6.7 1.6 5.8 1.7 6.3 tPZL tPHZ Output Disable Time tPLZ tSU Setup Time Units Max 150 A before CLKAB 2.9 2.9 B before CLKBA 2.9 2.9 A or B before LE, CLK HIGH 1.8 0.9 A or B before LE, CLK LOW 2.9 2.3 A or B after CLK 0.5 0.9 A or B after LE 1.6 1.6 MHz ns ns ns ns ns ns tH tW tOSLH Hold Time Pulse Duration LE HIGH 3.3 3.3 CLK HIGH or LOW 3.3 3.3 ns ns Output to Output Skew (Note 13) tOSHL 1.0 1.0 1.0 1.0 ns Note 13: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance (Note 14) Typical Units CIN Symbol Input Capacitance Parameter VCC = 0V, VI = 0V or VCC Conditions 4 pF CI/O Input/Output Capacitance VCC = 3.0V, VO = 0V or VCC 8 pF Note 14: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. www.fairchildsemi.com 6 74LVTH16500 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A Preliminary 7 www.fairchildsemi.com 74LVTH16500 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS56A www.fairchildsemi.com 8 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com 74LVTH16500 Low Voltage 18-Bit Universal Bus Transceivers with Bushold and 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)