Revised October 2001 74LVT16543 • 74LVTH16543 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs General Description Features The LVT16543 and LVTH16543 16-bit transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. Each byte has separate control inputs, which can be shorted together for full 16-bit operation. ■ Input and output interface capability to systems at 5V VCC The LVTH16543 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These transceivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16543 and LVTH16543 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16543) ■ Also available without bushold feature (74LVT16543) ■ Live insertion/extraction permitted ■ Power Up/Down high impedance provides glitch-free bus loading ■ Outputs source/sink −32 mA/+64 mA ■ Functionally compatible with the 74 series 16543 ■ Latch-up conforms to JEDEC JED78 ■ ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V Ordering Code: Order Number Package Number Package Description 74LVT16543MEA (Preliminary) MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVT16543MTD (Preliminary) MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 74LVTH16543MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVTH16543MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © 2001 Fairchild Semiconductor Corporation DS012449 www.fairchildsemi.com 74LVT16543 • 74LVTH16543 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs January 2000 74LVT16543 • 74LVTH16543 Connection Diagram Pin Descriptions Pin Names Description OEABn A-to-B Output Enable Input (Active LOW) OEBAn B-to-A Output Enable Input (Active LOW) CEABn A-to-B Enable Input (Active LOW) CEBAn B-to-A Enable Input (Active LOW) LEABn A-to-B Latch Enable Input (Active LOW) LEBAn B-to-A Latch Enable Input (Active LOW) A0–A15 A-to-B Data Inputs or B-to-A 3-STATE Outputs B0–B15 B-to-A Data Inputs or A-to-B 3-STATE Outputs Functional Description A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA. Each byte has separate control inputs, allowing the device to be used as two 8-bit transceivers or as one 16-bit transceiver. The LVT16543 and LVTH16543 contain two sets of D-type latches, with separate input and output controls for each. For data flow from A to B, for example, the A to B Enable (CEAB) input must be LOW in order to enter data from the A Port or take data from the B Port as indicated in the Data I/ O Control Table. With CEAB LOW, a low signal on (LEAB) input makes the A to B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB line puts the Data I/O Control Table Inputs Latch Status (Byte n) Output Buffers (Byte n) Latched High Z CEABn LEABn OEABn H X X X H X Latched — L L X Transparent — X X H — High Z L X L — Driving H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown; B-to-A flow control is the same, except using CEBAn, LEBAn and OEBAn www.fairchildsemi.com 2 74LVT16543 • 74LVTH16543 Logic Diagrams Byte 1 (0:7) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Byte 2 (8:15) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74LVT16543 • 74LVTH16543 Absolute Maximum Ratings(Note 1) Symbol Parameter Value Conditions Units VCC Supply Voltage −0.5 to +4.6 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 Output in 3-STATE −0.5 to +7.0 Output in HIGH or LOW State (Note 2) V V V IIK DC Input Diode Current −50 VI < GND IOK DC Output Diode Current −50 VO < GND IO DC Output Current 64 VO > VCC Output at HIGH State 128 VO > VCC Output at LOW State V mA mA mA ICC DC Supply Current per Supply Pin ±64 mA IGND DC Ground Current per Ground Pin ±128 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions Symbol Parameter Min Max 2.7 3.6 V 0 5.5 V VCC Supply Voltage VI Input Voltage IOH HIGH-Level Output Current −32 IOL LOW-Level Output Current 64 TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Units mA −40 85 °C 0 10 ns/V Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 2: IO Absolute Maximum Rating must be observed. www.fairchildsemi.com 4 Symbol T A = −40°C to +85°C VCC Parameter (V) Min Max Units −1.2 VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC − 0.2 V IOH = −100 µA 2.7 2.4 V IOH = −8 mA 3.0 2.0 II(HOLD) Output LOW Voltage Bushold Input Minimum Drive Bushold Input Over-Drive (Note 3) Current to Change State II Input Current 0.8 V VO ≤ 0.1V or VO ≥ VCC − 0.1V V IOH = −32 mA 2.7 0.2 V IOL = 100 µA 2.7 0.5 V IOL = 24 mA 3.0 0.4 V IOL = 16 mA 3.0 0.5 V IOL = 32 mA 3.0 0.55 V IOL = 64 mA 75 µA VI = 0.8V −75 µA VI = 2.0V 500 µA (Note 4) −500 µA (Note 5) 3.0 (Note 3) II(OD) 2.0 V Conditions Input Clamp Diode Voltage VOL 2.7 II = −18 mA VIK 3.0 3.6 10 µA VI = 5.5V 3.6 ±1 µA VI = 0V or VCC −5 µA VI = 0V 1 µA VI = VCC 0 ±100 µA 0V ≤ VI or VO ≤ 5.5V 0–1.5V ±100 µA IOZL (Note 3) 3-STATE Output Leakage Current 3.6 −5 µA VO = 0.0V IOZL 3-STATE Output Leakage Current 3.6 −5 µA VO = 0.5V IOZH (Note 3) 3-STATE Output Leakage Current 3.6 5 µA VO = 3.6V IOZH 3-STATE Output Leakage Current 3.6 5 µA VO = 3.0V IOZH+ 3-STATE Output Leakage Current 3.6 10 µA VCC < V O ≤ 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled ICCZ+ Power Supply Current 3.6 0.19 mA Control Pins Data Pins IOFF Power Off Leakage Current IPU/PD Power Up/Down 3-STATE 3.6 Output Current VO = 0.5V to 3.0V VI = GND or VCC VCC ≤ V O ≤ 5.5V, Outputs Disabled ∆ICC Increase in Power Supply Current 3.6 (Note 6) 0.2 mA One Input at VCC − 0.6V Other Inputs at VCC or GND Note 3: Applies to bushold versions only (74LVTH16543) Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol Parameter (Note 7) TA = 25°C VCC (V) Min Typ Units Max Conditions CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 8) VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.8 V (Note 8) Note 7: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 8: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW. 5 www.fairchildsemi.com 74LVT16543 • 74LVTH16543 DC Electrical Characteristics 74LVT16543 • 74LVTH16543 AC Electrical Characteristics TA = −40°C to +85°C Symbol CL = 50 pF, RL = 500 Ω Parameter VCC = 3.3 ± 0.3V VCC = 2.7V Min Max Min Max tPLH Propagation Delay 1.2 4.2 1.2 4.5 tPHL Data to Outputs 1.2 4.4 1.2 4.9 tPLH Propagation Delay 1.3 4.7 1.3 5.5 tPHL LE to A or B 1.3 5.1 1.3 5.8 tPZH Output Enable Time 1.3 4.7 1.3 5.4 tPZL OE to A or B 1.3 5.1 1.3 6.1 tPHZ Output Disable Time 2.0 5.5 2.0 5.7 tPLZ OE to A or B 2.0 4.9 2.0 4.9 tPZH Output Enable Time 1.3 4.6 1.3 5.6 tPZL CE to A or B 1.3 5.0 1.3 6.1 tPHZ Output Disable Time 2.0 5.5 2.0 5.8 tPLZ CE to A or B 2.0 4.9 2.0 4.9 tW Pulse Duration tS Setup Time LE LOW 3.3 3.3 A or B before LE, Data HIGH 0.5 0.5 A or B before LE, Data LOW 0.8 1.3 A or B before CE, Data HIGH 0.5 0.0 A or B before CE, Data LOW 0.6 1.1 A or B after LE, Data HIGH 1.5 0.7 A or B after LE, Data LOW 1.2 1.3 A or B after CE, Data HIGH 1.7 0.9 A or B after CE, Data LOW 1.6 Units ns ns ns ns ns ns ns ns tH Hold Time ns tOSLH Output to Output Skew (Note 9) tOSHL 1.8 1.0 1.0 1.0 1.0 ns Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance (Note 10) Typical Units CIN Symbol Input Capacitance Parameter VCC = OPEN, VI = 0V or VCC Conditions 4 pF CI/O Input/Output Capacitance VCC = 3.0V, VO = 0V or VCC 8 pF Note 10: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. www.fairchildsemi.com 6 74LVT16543 • 74LVTH16543 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS56A 7 www.fairchildsemi.com 74LVT16543 • 74LVTH16543 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8