74VCXH16245 Low-Voltage 1.8/2.5/3.3V 16-Bit Transceiver With 3.6 V–Tolerant Inputs and Outputs (3–State, Non–Inverting) The 74VCXH16245 is an advanced performance, non–inverting 16–bit transceiver. It is designed for very high–speed, very low–power operation in 1.8 V, 2.5 V or 3.3 V systems. When operating at 2.5 V (or 1.8 V) the part is designed to tolerate voltages it may encounter on either inputs or outputs when interfacing to 3.3 V busses. It is guaranteed to be over–voltage tolerant to 3.6 V. The VCXH16245 is designed with byte control. It can be operated as two separate octals, or with the controls tied together, as a 16–bit wide function. The Transmit/Receive (T/Rn) inputs determine the direction of data flow through the bi–directional transceiver. Transmit (active–HIGH) enables data from A ports to B ports; Receive (active–LOW) enables data from B to A ports. The Output Enable inputs (OEn), when HIGH, disable both A and B ports by placing them in a HIGH Z condition. The data inputs include active bushold circuitry, eliminating the need for external pull–up resistors to hold unused or floating inputs at a valid logic state. • Designed for Low Voltage Operation: VCC = 1.65–3.6 V • 3.6 V Tolerant Inputs and Outputs • High Speed Operation: 2.5 ns max for 3.0 to 3.6 V • • • • • • • 3.0 ns max for 2.3 to 2.7 V 6.0 ns max for 1.65 to 1.95 V Static Drive: ±24 mA Drive at 3.0 V ±18 mA Drive at 2.3 V ±6 mA Drive at 1.65 V Supports Live Insertion and Withdrawal Includes Active Bushold to Hold Unused or Floating Inputs at a Valid Logic State IOFF Specification Guarantees High Impedance When VCC = 0 V† Near Zero Static Supply Current in All Three Logic States (20 µA) Substantially Reduces System Power Requirements Latchup Performance Exceeds ±250 mA @ 125°C ESD Performance: Human Body Model >2000 V; Machine Model >200 V http://onsemi.com MARKING DIAGRAM 48 48 74VCXH16245DT 1 AWLYYWW TSSOP–48 DT SUFFIX CASE 1201 A WL YY WW 1 = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Package Shipping 74VCXH16245DT Device TSSOP 39 / Rail 74VCXH16245DTR TSSOP 2500 / Reel †NOTE: To ensure the outputs activate in the 3–state condition, the output enable pins should be connected to VCC through a pull–up resistor. The value of the resistor is determined by the current sinking capability of the output connected to the OE pin. Semiconductor Components Industries, LLC, 2001 January, 2001 – Rev. 1 1 Publication Order Number: 74VCXH16245/D 74VCXH16245 48 OE1 T/R1 1 B0 2 47 A0 B1 3 46 A1 GND 4 T/R1 1 OE1 T/R2 48 24 OE2 25 45 GND B2 5 44 A2 B3 6 43 A3 VCC 7 42 VCC B4 8 41 A4 B5 9 40 A5 GND 10 A0:7 B0:7 A8:15 B8:15 One of Eight 39 GND B6 11 38 A6 B7 12 37 A7 B8 13 36 A8 B9 14 35 A9 GND 15 34 GND B10 16 33 A10 B11 17 32 A11 VCC 18 31 VCC B12 19 30 A12 B13 20 29 A13 GND 21 28 GND B14 22 27 A14 B15 23 26 A15 T/R2 24 25 OE2 Figure 2. Logic Diagram 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 Figure 1. 48–Lead Pinout (Top View) PIN NAMES Pins Function OEn T/Rn A0–A15 B0–B15 Output Enable Inputs Transmit/Receive Inputs Side A Inputs or 3–State Outputs Side B Inputs or 3–State Outputs EN1 EN2 EN3 EN4 T/R1 48 OE1 25 OE2 24 T/R2 47 1 46 1∇ 2 3 5 44 43 41 1 2∇ 6 8 40 9 38 11 37 36 1 3∇ 12 13 35 14 33 16 32 30 1 4∇ 17 19 29 20 27 22 26 23 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 Figure 3. IEC Logic Diagram Inputs Inputs OE1 T/R1 L L L H O tp ts Outputs O tp ts Outputs OE2 T/R2 Bus B0:7 Data to Bus A0:7 L L Bus B8:15 Data to Bus A8:15 H Bus A0:7 Data to Bus B0:7 L H Bus A8:15 Data to Bus B8:15 X High Z State on A0:7, B0:7 H X High Z State on A8:15, B8:15 H = High Voltage Level; L = Low Voltage Level; X = High or Low Voltage Level and Transitions Are Acceptable http://onsemi.com 2 74VCXH16245 ABSOLUTE MAXIMUM RATINGS* Symbol Parameter VCC DC Supply Voltage VI VO Value Condition Unit –0.5 to +4.6 V DC Input Voltage –0.5 ≤ VI ≤ +4.6 V DC Output Voltage –0.5 ≤ VO ≤ +4.6 Output in 3–State V –0.5 ≤ VO ≤ VCC + 0.5 Note 1.; Outputs Active V IIK DC Input Diode Current –50 VI < GND mA IOK DC Output Diode Current –50 VO < GND mA +50 VO > VCC mA IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current Per Supply Pin ±100 mA IGND DC Ground Current Per Ground Pin ±100 mA TSTG Storage Temperature Range –65 to +150 °C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied. 1. IO absolute maximum rating must be observed. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Operating Data Retention Only Min Typ Max Unit 1.65 1.2 3.3 3.3 3.6 3.6 V –0.3 3.6 V 0 0 VCC 3.6 V VCC Supply Voltage VI Input Voltage VO Output Voltage IOH HIGH Level Output Current, VCC = 3.0V – 3.6V –24 mA IOL LOW Level Output Current, VCC = 3.0V – 3.6V 24 mA IOH HIGH Level Output Current, VCC = 2.3V – 2.7V –18 mA IOL LOW Level Output Current, VCC = 2.3V – 2.7V 18 mA IOH HIGH Level Output Current, VCC = 1.65 – 1.95V –6 mA IOL LOW Level Output Current, VCC = 1.65 – 1.95V 6 mA TA Operating Free–Air Temperature –40 +85 °C ∆t/∆V Input Transition Rise or Fall Rate, VIN from 0.8V to 2.0V, VCC = 3.0V 0 10 ns/V (Active State) (3–State) http://onsemi.com 3 74VCXH16245 DC ELECTRICAL CHARACTERISTICS TA = –40°C to +85°C Symbol VIH VIL VOH VOL Condition Min HIGH Level Input Voltage (Note 2.) 1.65V ≤ VCC < 2.3V 0.65 x VCC 2.3V ≤ VCC ≤ 2.7V 1.6 2.7V < VCC ≤ 3.6V 2.0 LOW Level Input Voltage (Note 2.) HIGH Level Output Voltage LOW Level Output Voltage II Input Leakage Current II(HOLD) ( ) Minimum Bushold Input Current II ((OD)) Minimum Bushold Over–Drive C Current tN Needed d d tto Ch Change St State t IOZ 3–State Output Current IOFF Power–Off Leakage Current ICC Quiescent Supply Current (Note 5.) ∆ICC 2. 3. 4. 5. Characteristic Increase in ICC per Input Max V 1.65V ≤ VCC < 2.3V 0.35 x VCC 2.3V ≤ VCC ≤ 2.7V 0.7 2.7V < VCC ≤ 3.6V 0.8 1.65V ≤ VCC ≤ 3.6V; IOH = –100µA VCC – 0.2 VCC = 1.65V; IOH = –6mA 1.25 VCC = 2.3V; IOH = –6mA 2.0 VCC = 2.3V; IOH = –12mA 1.8 VCC = 2.3V; IOH = –18mA 1.7 VCC = 2.7V; IOH = –12mA 2.2 VCC = 3.0V; IOH = –18mA 2.4 VCC = 3.0V; IOH = –24mA 2.2 0.2 VCC = 1.65V; IOL = 6mA 0.3 VCC = 2.3V; IOL = 12mA 0.4 VCC = 2.3V; IOL = 18mA 0.6 VCC = 2.7V; IOL = 12mA 0.4 VCC = 3.0V; IOL = 18mA 0.4 VCC = 3.0V; IOL = 24mA 0.55 1.65V ≤ VCC ≤ 3.6V; 0V ≤ VI ≤ 3.6V ±5.0 75 VCC = 3.0V, VIN = 2.0V –75 VCC = 2.3V, VIN = 0.7V 45 VCC = 2.3V, VIN = 1.6V –45 VCC = 1.65V, VIN = 0.57V 25 VCC = 1.65V, VIN = 1.07V –25 VCC = 3.6V, (Note 3.) 450 VCC = 3.6V, (Note 4.) –450 VCC = 2.7V, (Note 3.) 300 VCC = 2.7V, (Note 4.) –300 VCC = 1.95V, (Note 3.) 200 VCC = 1.95V, (Note 4.) –200 V V 1.65V ≤ VCC ≤ 3.6V; IOL = 100µA VCC = 3.0V, VIN = 0.8V Unit V µA µA µA 1.65V ≤ VCC ≤ 3.6V; 0V ≤ VO ≤ 3.6V; VI = VIH or VIL ±10 µA VCC = 0V; VI or VO = 3.6V 10 µA 1.65V ≤ VCC ≤ 3.6V; VI = GND or VCC 20 µA 1.65V ≤ VCC ≤ 3.6V; 3.6V ≤ VI, VO ≤ 3.6V ±20 µA 2.7V < VCC ≤ 3.6V; VIH = VCC – 0.6V 750 µA These values of VI are used to test DC electrical characteristics only. An external driver must source at least the specified current to switch from LOW–to–HIGH. An external driver must source at least the specified current to switch from HIGH–to–LOW. Outputs disabled or 3–state only. http://onsemi.com 4 74VCXH16245 AC CHARACTERISTICS (Note 6.; tR = tF = 2.0ns; CL = 30pF; RL = 500Ω) Limits TA = –40°C to +85°C VCC = 3.0V to 3.6V Symbol Parameter VCC = 2.3V to 2.7V VCC = 1.65 to1.95V Waveform Min Max Min Max Min Max Unit tPLH tPHL Propagation Delay Input to Output 1 0.8 0.8 2.5 2.5 1.0 1.0 3.0 3.0 1.5 1.5 6.0 6.0 ns tPZH tPZL Output Enable Time to High and Low Level 2 0.8 0.8 3.8 3.8 1.0 1.0 4.9 4.9 1.5 1.5 9.3 9.3 ns tPHZ tPLZ Output Disable Time From High and Low Level 2 0.8 0.8 3.7 3.7 1.0 1.0 4.2 4.2 1.5 1.5 7.6 7.6 ns tOSHL tOSLH Output–to–Output Skew (Note 7.) 0.75 0.75 ns 0.5 0.5 0.5 0.5 6. For CL = 50pF, add approximately 300ps to the AC maximum specification. 7. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (tOSHL) or LOW–to–HIGH (tOSLH); parameter guaranteed by design. DYNAMIC SWITCHING CHARACTERISTICS TA = +25°C Symbol VOLP VOLV VOHV Characteristic Condition Typ Unit Dynamic LOW Peak Voltage VCC = 1.8V, CL = 30pF, VIH = VCC, VIL = 0V 0.25 V (Note 8.) VCC = 2.5V, CL = 30pF, VIH = VCC, VIL = 0V 0.6 VCC = 3.3V, CL = 30pF, VIH = VCC, VIL = 0V 0.8 Dynamic LOW Valley Voltage VCC = 1.8V, CL = 30pF, VIH = VCC, VIL = 0V –0.25 (Note 8.) VCC = 2.5V, CL = 30pF, VIH = VCC, VIL = 0V –0.6 VCC = 3.3V, CL = 30pF, VIH = VCC, VIL = 0V –0.8 Dynamic HIGH Valley Voltage VCC = 1.8V, CL = 30pF, VIH = VCC, VIL = 0V 1.5 (Note 9.) VCC = 2.5V, CL = 30pF, VIH = VCC, VIL = 0V 1.9 VCC = 3.3V, CL = 30pF, VIH = VCC, VIL = 0V 2.2 V V 8. Number of outputs defined as “n”. Measured with “n–1” outputs switching from HIGH–to–LOW or LOW–to–HIGH. The remaining output is measured in the LOW state. 9. Number of outputs defined as “n”. Measured with “n–1” outputs switching from HIGH–to–LOW or LOW–to–HIGH. The remaining output is measured in the HIGH state. CAPACITIVE CHARACTERISTICS Symbol Parameter Condition Typical Unit CIN Input Capacitance Note 10. 6 pF COUT Output Capacitance Note 10. 7 pF CPD Power Dissipation Capacitance Note 10., 10MHz 20 pF 10. VCC = 1.8, 2.5 or 3.3V; VI = 0V or VCC. http://onsemi.com 5 74VCXH16245 VIH Vm An, Bn Vm tPLH 0V tPHL Vm Bn, An VOH Vm VOL WAVEFORM 1 - PROPAGATION DELAYS tR = tF = 2.0ns, 10% to 90%; f = 1MHz; tW = 500ns VIH Vm OEn, T/Rn Vm 0V tPZH tPHZ VOH Vy Vm An, Bn ≈ 0V tPZL tPLZ ≈ VCC Vm An, Bn Vx VOL WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.0ns, 10% to 90%; f = 1MHz; tW = 500ns Figure 4. AC Waveforms VCC Symbol 3.3V ±0.3V 2.5V ±0.2V 1.8V ±0.15V VIH 2.7V VCC VCC Vm 1.5V VCC/2 VCC/2 Vx VOL + 0.3V VOL + 0.15V VOL + 0.15V Vy VOH – 0.3V VOH – 0.15V VOH – 0.15V VCC PULSE GENERATOR RL DUT RT CL TEST RL SWITCH tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ±0.3V; VCC× 2 at VCC = 2.5 ±0.2V; 1.8V ±0.15V tPZH, tPHZ GND CL = 30pF or equivalent (Includes jig and probe capacitance) RL = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) Figure 5. Test Circuit http://onsemi.com 6 6V or VCC × 2 OPEN GND 74VCXH16245 VIH Vm An, Bn Vm tPLH 0V tPHL Vm Bn, An VOH Vm VOL WAVEFORM 3 - PROPAGATION DELAYS tR = tF = 2.0ns, 10% to 90%; f = 1MHz; tW = 500ns VIH Vm OEn, T/Rn Vm 0V tPZH tPHZ VOH Vy Vm An, Bn ≈ 0V tPZL tPLZ ≈ VCC Vm An, Bn Vx VOL WAVEFORM 4 - OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.0ns, 10% to 90%; f = 1MHz; tW = 500ns Figure 6. AC Waveforms VCC Symbol 3.3V ±0.3V 2.7V VIH 2.7V 2.7V Vm 1.5V 1.5V Vx VOL + 0.3V VOL + 0.3V Vy VOH – 0.3V VOH – 0.3V VCC PULSE GENERATOR RL DUT RT CL TEST RL SWITCH tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ±0.3V; VCC × 2 at VCC = 2.5 ±0.2V; 1.8 ±0.15V tPZH, tPHZ GND CL = 50pF or equivalent (Includes jig and probe capacitance) RL = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) Figure 7. Test Circuit http://onsemi.com 7 6V or VCC × 2 OPEN GND 74VCXH16245 AC CHARACTERISTICS (tR = tF = 2.0ns; CL = 50pF; RL = 500Ω) Limits TA = –40°C to +85°C VCC = 3.0V to 3.6V Symbol Parameter VCC = 2.7V Waveform Min Max Max Unit tPLH tPHL Propagation Delay Input to Output 3 1.0 1.0 3.0 3.0 Min 3.6 3.6 ns tPZH tPZL Output Enable Time to High and Low Level 4 1.0 1.0 4.4 4.4 5.4 5.4 ns tPHZ tPLZ Output Disable Time From High and Low Level 4 1.0 1.0 4.1 4.1 4.6 4.6 ns tOSHL tOSLH Output–to–Output Skew (Note 11.) 0.5 0.5 0.5 0.5 ns 11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (tOSHL) or LOW–to–HIGH (tOSLH); parameter guaranteed by design. http://onsemi.com 8 74VCXH16245 P0 K t P2 D TOP COVER TAPE E A0 + K0 SEE NOTE 2 B1 10 PITCHES CUMULATIVE TOLERANCE ON TAPE ±0.2 mm (±0.008") SEE NOTE 2 F + B0 W + D1 FOR COMPONENTS 2.0 mm × 1.2 mm AND LARGER P EMBOSSMENT FOR MACHINE REFERENCE ONLY INCLUDING DRAFT AND RADII CONCENTRIC AROUND B0 CENTER LINES OF CAVITY USER DIRECTION OF FEED *TOP COVER TAPE THICKNESS (t1) 0.10 mm (0.004") MAX. R MIN. BENDING RADIUS 10° TAPE AND COMPONENTS SHALL PASS AROUND RADIUS R" WITHOUT DAMAGE EMBOSSED CARRIER 100 mm (3.937") MAXIMUM COMPONENT ROTATION EMBOSSMENT 1 mm MAX TYPICAL COMPONENT CAVITY CENTER LINE TAPE 1 mm (0.039") MAX TYPICAL COMPONENT CENTER LINE 250 mm (9.843") CAMBER (TOP VIEW) ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm Figure 8. Carrier Tape Specifications EMBOSSED CARRIER DIMENSIONS (See Notes 1 and 2) Tape Size B1 Max 24mm 20.1mm (0.791") D D1 E F K P P0 P2 R T W 1.5 + 0.1mm -0.0 (0.059 +0.004" -0.0) 1.5mm Min (0.060") 1.75 ±0.1 mm (0.069 ±0.004") 11.5 ±0.10 mm (0.453 ±0.004") 11.9 mm Max (0.468") 16.0 ±0.1 mm (0.63 ±0.004") 4.0 ±0.1 mm (0.157 ±0.004") 2.0 ±0.1 mm (0.079 ±0.004") 30 mm (1.18") 0.6 mm (0.024") 24.3 mm (0.957") 1. Metric Dimensions Govern–English are in parentheses for reference only. 2. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. The component cannot rotate more than 10° within the determined cavity. http://onsemi.com 9 74VCXH16245 t MAX 13.0 mm ±0.2 mm (0.512" ±0.008") 1.5 mm MIN (0.06") A 20.2 mm MIN (0.795") 50 mm MIN (1.969") FULL RADIUS G Figure 9. Reel Dimensions REEL DIMENSIONS Tape Size A Max G t Max 24 mm 360 mm (14.173") 24.4 mm + 2.0 mm, -0.0 (0.961" + 0.078", -0.00) 30.4 mm (1.197") DIRECTION OF FEED BARCODE LABEL POCKET Figure 10. Reel Winding Direction http://onsemi.com 10 HOLE 74VCXH16245 CAVITY TAPE TOP TAPE TAPE TRAILER (Connected to Reel Hub) NO COMPONENTS 160 mm MIN TAPE LEADER NO COMPONENTS 400 mm MIN COMPONENTS DIRECTION OF FEED Figure 11. Tape Ends for Finished Goods User Direction of Feed Figure 12. Reel Configuration ÉÉ ÉÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉÉÉÉÉ ÉÉ ÉÉ ÉÉ É ÉÉ É ÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉ ÉÉ ÉÉ ÉÉ É ÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉ K L G 48 Leads Figure 13. Package Footprint http://onsemi.com 11 F 74VCXH16245 PACKAGE DIMENSIONS TSSOP DT SUFFIX CASE 1201–01 ISSUE A 48X ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ K K1 K REF 0.12 (0.005) M T U S V S T U S J J1 48 25 0.254 (0.010) M SECTION N–N B –U– L N 1 24 A –V– PIN 1 IDENT. N F DETAIL E D 0.076 (0.003) –T– SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. C M 0.25 (0.010) –W– DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 12.40 12.60 6.00 6.20 --1.10 0.05 0.15 0.50 0.75 0.50 BSC 0.37 --0.09 0.20 0.09 0.16 0.17 0.27 0.17 0.23 7.95 8.25 0 8 INCHES MIN MAX 0.488 0.496 0.236 0.244 --0.043 0.002 0.006 0.020 0.030 0.0197 BSC 0.015 --0.004 0.008 0.004 0.006 0.007 0.011 0.007 0.009 0.313 0.325 0 8 H G ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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