PRELIMINARY ICS87004I-03 LVCMOS/LVTTL FANOUT BUFFER/DIVIDER GENERAL DESCRIPTION FEATURES The ICS87004I-03 is a low skew, ÷1, ÷2 ÷3, ÷4 ÷5, ICS ÷6 ÷8, ÷16 LVCMOS/LVTTL Fanout Buffer/Divider HiPerClockS™ and a member of theHiPerClockS™ family of High Perfor mance Clock Solutions from IDT. The ICS87004I-03 has selectable clock inputs that accept single ended input levels. Output enable pin controls whether the output is in the active or high impedance state. • Two banks of two LVCMOS/LVTTL outputs, 15Ω typical output impedance • Selectable LVCMOS/LVTTL clock inputs • LVCMOS_CLK supports the following input types: LVCMOS, LVTTL • The ICS87004I-03 is characterized at 3.3V, 2.5V and mixed 3.3V/2.5V, 3.3V/1.8V, 2.5V/1.8V input/output supply operating modes.Guaranteed bank, output, and par t-to-par t skew character istics make the ICS87004I-03 ideal for those applications demanding well defined perfor mance and repeatability. Maximum output frequency: 250MHz • Output skew: 40ps (typical) • Bank skew: 20ps (typical) • Part-to-part skew: TBD • Power supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V • -40°C to 85°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM OEA Pullup NA2:NA0 Pulldown 3 CLK_SEL Pulldown CLK0 Pulldown 0 CLK1 Pulldown 1 NB2:NB0 Pulldown N Output Divider NA2:NA0 0 0 0 ÷1 (default) 0 0 1 ÷2 0 1 0 ÷3 0 1 1 ÷4 1 0 0 ÷5 1 0 1 ÷6 1 1 0 ÷8 1 1 1 ÷16 N Output Divider NB2:NB0 0 0 0 ÷1 (default) 0 0 1 ÷2 0 1 0 ÷3 0 1 1 ÷4 1 0 0 ÷5 1 0 1 ÷6 1 1 0 ÷8 1 1 1 ÷16 PIN ASSIGNMENT VDD NA2 NA1 NA0 QA0 QA1 CLK0 CLK_SEL CLK1 NB2 NB1 NB0 VDD0A VDD0B 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 OEA VDDOA QA0 QA1 GND QB1 QB0 VDDOB GND OEB ICS87004I-03 20-Lead TSSOP 6.50mm x 4.40mm x 0.925mm package body G Package Top View QB0 QB1 3 OEB Pullup The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER 1 ICS87004BGI-03 REV. B JUNE 10, 2008 ICS87004I-03 LVCMOS/LVTTL FANOUT BUFFER/DIVIDER PRELIMINARY TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 VDD Power 2, 3, 4 NA2, NA1, NA0 Input Pulldown N divider pins for Bank A outputs. LVCMOS / LVTTL interface levels. 5, 7 CLK0, CLK1 Input 6 CLK_SEL Input 8, 9, 10 NB2, NB1, NB0 Input 11 OE B Input 12, 16 GND Power Pulldown Single-ended clock inputs. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK1 input. Pulldown When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels. Pulldown N divider pins for Bank B outputs. LVCMOS / LVTTL interface levels. Output enable. When LOW, Bank B outputs are in HIGH impedance state. When HIGH, Bank B outputs are active. Pullup LVCMOS / LVTTL interface levels. Power supply ground. Power supply pin. 13 VDDOB Power Output supply pin for Bank B outputs. 14, 15 QB0, QB1 Output Single-ended Bank B clock outputs. LVCMOS / LVTTL interface levels. 17, 18 QA1, QA0 Output Single-ended Bank A clock outputs. LVCMOS / LVTTL interface levels. Bank A output supply pin. Output enable. When LOW, Bank A outputs are in HIGH impedance state. When HIGH, Bank A outputs are active. 20 OEA Input Pullup LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 19 Power VDDOA TABLE 2. PIN CHARACTERISTICS Parameter Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance 51 kΩ 10 pF 15 Ω CPD ROUT Test Conditions Minimum Typical Maximum Units Symbol CIN TABLE 3. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE N2 0 Inputs N1 0 N0 0 N Divider Value ÷1 (default) 0 0 1 ÷2 12 5 0 1 0 ÷3 83.333 Output Frequency (MHz) 250 0 1 1 ÷4 62.5 1 0 0 ÷5 50 1 0 1 ÷6 41.667 1 1 0 ÷8 31.25 1 1 1 ÷16 15.625 NOTE: Some combinations of Bank A and Bank B output divider selections are not synchronous. IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER 2 ICS87004BGI-03 REV. B JUNE 10, 2008 ICS87004I-03 LVCMOS/LVTTL FANOUT BUFFER/DIVIDER PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDOX + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 91.1°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDOA = VDDOB = 3.3V±5%, TA = -40°C TO 85°C Symbol VDD Parameter Power Supply Voltage VDDOA, VDDOB Output Supply Voltage IDD IDDOA, IDDOB Power Supply Current Output Supply Current Test Conditions Minimum 3.135 Typical 3. 3 Maximum 3.465 3.135 3. 3 3.465 40 1 Units V V mA mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDOA = VDDOB = 2.5V±5%, TA = -40°C TO 85°C Symbol VDD Parameter Power Supply Voltage VDDOA, VDDOB Output Supply Voltage IDD IDDOA, IDDOB Power Supply Current Output Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 2.375 2.5 2.625 40 1 Units V V mA mA TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDOA = VDDOB = 1.8V±0.15V, TA = -40°C TO 85°C Symbol VDD Parameter Power Supply Voltage VDDOA, VDDOB Output Supply Voltage IDD IDDOA, IDDOB Power Supply Current Output Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 1.65 1.8 1.95 40 1 Units V V mA mA TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDOA = VDDOB = 2.5V±5%, TA = -40°C TO 85°C Symbol VDD Parameter Power Supply Voltage VDDOA, VDDOB Output Supply Voltage IDD IDDOA, IDDOB Power Supply Current Output Supply Current Test Conditions Minimum 2.375 Typical 2.5 Maximum 2.625 2.375 2.5 2.625 39 1 Units V V mA mA TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V±5%, VDDOA = VDDOB = 1.8V±0.15V, TA = -40°C TO 85°C Symbol VDD Parameter Power Supply Voltage VDDOA, VDDOB Output Supply Voltage IDD IDDOA, IDDOB Power Supply Current Output Supply Current IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER Test Conditions Minimum 2.375 Typical 2. 5 Maximum 2.625 Units V 1.65 1.8 1.95 V 39 1 3 mA mA ICS87004BGI-03 REV. B JUNE 10, 2008 ICS87004I-03 LVCMOS/LVTTL FANOUT BUFFER/DIVIDER PRELIMINARY TABLE 4F. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5% OR 2.5V±5%VDDOA = VDDOB = 3.3V±5%, 2.5V±5% OR 1.8V±0.15V, TA = -40°C TO 85°C Symbol Parameter VIH VIL IIH IIL VOH Test Conditions Input High Voltage Input Low Voltage Input High Current Input Low Current CLK0, CLK1, CLK_SEL, NA2:NA0, NB2:NB0 OEA, OEB CLK0, CLK1, CLK_SEL, NA2:NA0, NB2:NB0 OEA, OEB Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 IOZL Output Hi-Z Current Low IOZH Output Hi-Z Current High Minimum Typical Maximum Units 2 VDD + 0.3 V VDD = 2.5V 1. 7 VDD + 0.3 V VDD = 3.3V -0.3 0.8 V VDD = 2.5V VDD = VIN = 3.465V or 2.625V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V -0.3 0.7 V 150 µA 5 µA VDD = 3.3V -5 µA VDD = 3.465V or 2.625V, VIN = 0V -150 µA VDDOX = 3.3V ± 5% 2.6 V VDDOX = 2.5V ± 5% 1.8 V VDDOX = 1.8V ± 0.15V 1.5 V VDDOX = 3.3V ± 5% 0.5 V VDDOX = 2.5V ± 5% 0.5 V VDDOX = 1.8V ± 0.15V 0.4 -5 V µA 5 µA NOTE 1: Outputs terminated with 50Ω to VDDOX/2. See Parameter Measurement Information, Output Load Test Circuit. TABLE 5A. AC CHARACTERISTICS, VDD = VDDOA = VDDOB = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units 250 MH z fMAX Output Frequency tPD Propagation Delay, NOTE 1 4.3 ns t sk(o) Output Skew; NOTE 2, 3 40 ps t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 t sk(b) Bank Skew; NOTE 3, 5 t R / tF Output Rise/Fall Time; NOTE 6 odc Output Duty Cycle tEN Output Enable Time; NOTE 6 ps 20% to 80% 20 ps 700 ps 50 % Output Disable Time; NOTE 6 tDIS All parameters measured at ƒ ≤ TBDMHz unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDOX/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE: 5 Defined as skew within a bank with equal load conditions. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER 4 5 ns 5 ns ICS87004BGI-03 REV. B JUNE 10, 2008 ICS87004I-03 LVCMOS/LVTTL FANOUT BUFFER/DIVIDER PRELIMINARY TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDOA = VDDOB = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency Test Conditions Minimum Typical Maximum Units 250 MH z tPD Propagation Delay, NOTE 1 4.6 ns t sk(o) Output Skew; NOTE 2, 3 40 ps t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 t sk(b) Bank Skew; NOTE 3, 5 20 ps t R / tF Output Rise/Fall Time; NOTE 6 800 ps odc Output Duty Cycle tEN Output Enable Time; NOTE 6 ps 20% to 80% 50 % 5 ns 5 ns Maximum Units 250 MH z Output Disable Time; NOTE 6 tDIS All parameters measured at ƒ ≤ TBDMHz unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDOX/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE: 5 Defined as skew within a bank with equal load conditions. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDOA = VDDOB = 1.8V±0.15V, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency Test Conditions Minimum Typical tPD Propagation Delay, NOTE 1 5.0 ns t sk(o) Output Skew; NOTE 2, 3 40 ps t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 t sk(b) Bank Skew; NOTE 3, 5 20 ps t R / tF Output Rise/Fall Time; NOTE 6 1 ns odc Output Duty Cycle tEN Output Enable Time; NOTE 6 ps 20% to 80% 50 Output Disable Time; NOTE 6 tDIS All parameters measured at ƒ ≤ TBDMHz unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDOX/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE: 5 Defined as skew within a bank with equal load conditions. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER 5 % 5 ns 5 ns ICS87004BGI-03 REV. B JUNE 10, 2008 ICS87004I-03 LVCMOS/LVTTL FANOUT BUFFER/DIVIDER PRELIMINARY TABLE 5D. AC CHARACTERISTICS, VDD = VDDOA = VDDOB = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency Test Conditions Minimum Typical Maximum Units 250 MH z tPD Propagation Delay, NOTE 1 4.7 ns t sk(o) Output Skew; NOTE 2, 3 40 ps t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 t sk(b) Bank Skew; NOTE 3, 5 20 ps t R / tF Output Rise/Fall Time; NOTE 6 900 ps odc Output Duty Cycle tEN Output Enable Time; NOTE 6 ps 20% to 80% 50 % 5 ns 5 ns Maximum Units 250 MH z Output Disable Time; NOTE 6 tDIS All parameters measured at ƒ ≤ TBDMHz unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDOX/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE: 5 Defined as skew within a bank with equal load conditions. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. TABLE 5E. AC CHARACTERISTICS, VDD = 2.5V±5%, VDDOA = VDDOB = 1.8V±0.15V, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency Test Conditions Minimum Typical tPD Propagation Delay, NOTE 1 5.0 ns t sk(o) Output Skew; NOTE 2, 3 40 ps t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 t sk(b) Bank Skew; NOTE 3, 5 20 ps 1.1 ns 50 % t R / tF Output Rise/Fall Time; NOTE 6 od c Output Duty Cycle tEN Output Enable Time; NOTE 6 ps 20% to 80% Output Disable Time; NOTE 6 tDIS All parameters measured at ƒ ≤ TBDMHz unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDOX/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE: 5 Defined as skew within a bank with equal load conditions. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER 6 5 ns 5 ns ICS87004BGI-03 REV. B JUNE 10, 2008 ICS87004I-03 LVCMOS/LVTTL FANOUT BUFFER/DIVIDER PRELIMINARY PARAMETER MEASUREMENT INFORMATION 1.65V±5% 2.05V±5% 1.25V±5% SCOPE VDD, VDDOA, VDDOB SCOPE VDD VDDOA, VDDOB Qx LVCMOS Qx GND LVCMOS GND -1.65V±5% -1.25V±5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 1.25V±5% 2.4V±0.09V 0.9V±0.075V VDDOA, VDDOB SCOPE VDD, VDDOA, VDDOB SCOPE VDD Qx Qx LVCMOS GND LVCMOS GND -1.25V±5% -0.9V±0.075V 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 1.6V±5% PART 1 0.9V±0.075V Qx V DDOX 2 SCOPE VDD VDDOA, VDDOB PART 2 Qy Qx GND V DDOX 2 tsk(pp) LVCMOS -0.9V±0.075V 2.5V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER PART-TO-PART SKEW 7 ICS87004BGI-03 REV. B JUNE 10, 2008 ICS87004I-03 LVCMOS/LVTTL FANOUT BUFFER/DIVIDER PRELIMINARY PARAMETER MEASUREMENT INFORMATION, CONTINUED V DDOX Qx QX0, QX1 2 VDDOX 2 VDDOX 2 V DDOX Qy QX0, QX1 2 tsk(o) tsk(b) BANK SKEW (where X denotes outputs in the same bank) OUTPUT SKEW VDD 2 CLK0, CLK1 QA0,QA1 QB0,QB1 QA0,QA1 QB0,QB1 80% tR tF 20% 20% VDDOX 2 t 80% PD PROPAGATION DELAY OUTPUT RISE/FALL TIME V DDOX QA0,QA1 QB0,QB1 2 t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER 8 ICS87004BGI-03 REV. B JUNE 10, 2008 ICS87004I-03 LVCMOS/LVTTL FANOUT BUFFER/DIVIDER PRELIMINARY APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK INPUTS For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. LVCMOS OUTPUTS All unused LVCMOS output can be left floating. There should be no trace attached. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER 9 ICS87004BGI-03 REV. B JUNE 10, 2008 ICS87004I-03 LVCMOS/LVTTL FANOUT BUFFER/DIVIDER PRELIMINARY RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 91.1°C/W 86.7°C/W 84.6°C/W TRANSISTOR COUNT The transistor count for ICS87004I-03 is: 2781 PACKAGE OUTLINE AND DIMENSIONS PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS Millimeters SYMBOL MIN N MAX 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 E E1 6.60 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER 10 ICS87004BGI-03 REV. B JUNE 10, 2008 ICS87004I-03 LVCMOS/LVTTL FANOUT BUFFER/DIVIDER PRELIMINARY TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 87004BGI-03 ICS87004BI03 20 Lead TSSOP tube -40°C to 85°C 87004BGI-03T ICS87004BI03 20 Lead TSSOP 2500 tape & reel -40°C to 85°C 87004BGI-03LF TBD 20 Lead "Lead-Free" TSSOP tube -40°C to 85°C 87004BGI-03LFT TBD 20 Lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER 11 ICS87004BGI-03 REV. B JUNE 10, 2008 ICS87004I-03 LVCMOS/LVTTL FANOUT BUFFER/DIVIDER PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support Corporate Headquarters 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT [email protected] +480-763-2056 Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA