ONSEMI 87F064JU

Ordering number : ENA2197
LC87F1K64A
CMOS IC
8-bit Microcontroller
with USB-host Controller
http://onsemi.com
64K-byte Flash ROM / 8K-byte RAM / 48-pin
Overview
The LC87F1K64A is an 8-bit microcontroller that, integrates on a single chip a number of hardware features such as
64K-byte flash ROM, 8192-byte RAM, an on-chip debugger, a sophisticated 16-bit timer/counter (may be divided into
8-bit timers), a 16-bit timer (may be divided into 8-bit timers or PWMs), four 8-bit timers with a prescaler, a base timer
serving as a time-of-day clock, two channels of synchronous SIO interface with automatic data transfer capabilities, an
asynchronous/synchronous SIO interface, a single-master I2C/synchronous SIO interface, a UART interface (full
duplex), a full/low-speed USB interface (host control function) × 2 ports, a 12-bit 12-channel AD converter, two
channels of 12-bit PWM, a system clock frequency divider, an infrared remote control receiver circuit, an internal reset
circuit, and a 44-source 10-vector interrupt feature.
Features
■Flash ROM
• 65536×8 bits
• Capable of on-board programming with a wide range of
supply voltage from 3.0 to 5.5V
• Block-erasable in 128-byte units
• Data written in 2-byte units
■RAM
SQFP48(7X7)
• 8192×9 bits
■Package Form
• SQFP48 (7×7): Lead-/halogen-free product
■Bus Cycle Time
36
25
37
24
48
13
7.0
9.0
• 83.3ns (when CF=12MHz)
Note: The bus cycle time here refers to the ROM read
speed.
0.5
9.0
7.0
■Minimum Instruction Cycle Time (tCYC)
• 250ns (when CF=12MHz)
1
12
0.5
(1.5)
0.15
0.1
1.7max
(0.75)
0.18
ORDERING INFORMATION
See detailed ordering and shipping information on page 35 of this data sheet.
SQFP48(7X7)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
July, 2013
ver.1.02
71713HKPC 20111124-S00003 No.A2197-1/35
LC87F1K64A
■Ports
• I/O ports
Ports whose input/output can be specified in 1-bit units:
• USB ports
• Dedicated oscillator ports
• Input-only port (also used for the oscillator)
• Reset pin
• Power supply pins
34 (P00 to P07, P10 to P17, P20 to P25, P30 to P34,
P70 to P73, PWM0, PWM1, XT2)
4 (UHAD+, UHAD–, UHBD+, UHBD–)
2 (CF1, CF2)
1 (XT1)
1 (RES)
6 (VSS1 to 3, VDD1 to 3)
■Timers
• Timer 0: 16-bit timer/counter with 2 capture registers
Mode 0: 8-bit timer with an 8-bit programmable prescaler
(with two 8-bit capture registers) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler
(with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers)
Mode 3: 16-bit counter (with two 16-bit capture registers)
• Timer 1: 16-bit timer/counter that supports PWM/toggle output
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle output)
+ 8-bit timer/counter with an 8-bit prescaler (with toggle output)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle output)
(Toggle output also possible from low-order 8 bits.)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle output)
(Low-order 8 bits can be used as a PWM output.)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)
• Base timer
1) The clock can be selected from among a subclock (32.768kHz crystal oscillator), low-speed RC
oscillator clock, system clock, and timer 0 prescaler output.
2) Interrupts programmable in 5 different time schemes.
■Serial Interfaces
• SIO0: Synchronous serial interface
1) LSB first/MSB first selectable
2) Transfer clock cycle: 4/3 to 512/3 tCYC
3) Continuous automatic data transmission (1 to 256 bits can be specified in 1-bit units)
(Suspension and resumption of data transfer possible in 1-byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clock)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrate)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clock)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
• SIO4: Synchronous serial interface
1) LSB first/MSB first selectable
2) Transfer clock cycle: 4/3 to 1020/3 tCYC
3) Continuous automatic data transmission (1 to 8192 bytes can be specified in 1-byte units)
(Suspension and resumption of data transmission possible in 1-byte units or in word units)
4) Clock polarity can be selected.
5) CRC16 calculator circuit built- in
• SMIIC0: Single-master I2C/8-bit synchronous SIO
Mode 0: Communication in single-master mode.
Mode 1: 8-bit synchronous serial I/O (data MSB first)
No.A2197-2/35
LC87F1K64A
■Full Duplex UART
1) Data length:
2) Stop bits:
3) Parity bits:
4) Baudrate:
7/8/9 bits selectable
1 bit (2 bits in continuous transmission mode)
None/even/odd selectable (for 8-bit data only)
16/3 to 8192/3 tCYC
■AD Converter: 12 bits × 12 channels
■PWM: Variable frequency 12-bit PWM × 2 channels
■Infrared Remote Control Receiver Circuit
1) Noise rejection function (noise filter time constant: Approx. 120μs when the 32.768kHz crystal oscillator is selected
as the reference clock)
2) Supports data encoding systems such as PPM (Pulse Position Modulation) and Manchester encoding.
3) X'tal HOLD mode release function
■USB Interface (host control function) × 2 ports
1) Supports full-speed (12Mbps) and low-speed (1.5Mbps) specifications.
2) Supports four transfer types (control transfer, bulk transfer, interrupt transfer, and isochronous transfer).
■Audio Interface
1) Sampling frequencies (fs): 8kHz/11.025kHz/12kHz/16kHz/22.05kHz/24kHz/32kHz/44.1kHz/48kHz
2) Master clock:
256fs/384fs
3) Bit clock:
48fs/64fs
4) Data bit length:
16bits/18bits/20bits/24bits
5) LSB first/MSB first selectable.
6) Left justified/right justified/I2S format selectable
■Watchdog Timer
• External RC time constant type
1) Interrupt generation/reset generation selectable
2) Operation in HALT/HOLD mode can be selected from “continue operation” and “suspend operation.”
• Internal timer type
1) Capable of generating a internal reset signal on an overflow of the timer running on the low-speed RC oscillator
clock, or subclock.
2) Operation in HALT/HOLD mode can be selected from among “continue count operation,” “suspend operation,”
and “retain the count value.”
■Clock Output Function
1) Can output a clock with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillator clock selected as
the system clock.
2) Can output the source oscillator clock for the subclock.
No.A2197-3/35
LC87F1K64A
■Interrupts
• 44 sources, 10 vectors
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt request of
the level equal to or lower than the current interrupt level is not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the lowest vector
address is given priority.
No.
Vector
Level
1
00003H
X or L
Interrupt Source
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4/UHC-A bus active/UHC-B bus active/remote control receive
4
0001BH
H or L
INT3/INT5/base timer
5
00023H
H or L
T0H/INT6/UHC-A device connected, disconnected, resumed
6
0002BH
H or L
T1L/T1H/INT7/AIF start/SMIIC0/UHC-B device connected, disconnected, resumed
INT0
7
00033H
H or L
SIO0/UART1 reception completed
8
0003BH
H or L
SIO1/SIO4/UART1 buffer empty/UART1 transmission completed/AIF end
9
00043H
H or L
ADC/T6/T7/UHC-ACK/UHC-NAK/UHC error/UHC-STALL
10
0004BH
H or L
Port 0/PWM0/PWM1/T4/T5/UHC-SOF
• Priority levels X > H > L
• When interrupts of the same level occur at the same time, the interrupt with the lowest vector address is given
priority.
■Subroutine Stack Levels: Up to 4096 levels (The stack is allocated in RAM.)
■High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
• 24 bits × 16 bits
• 16 bits ÷ 8 bits
• 24 bits ÷ 16 bits
(5 tCYC execution time)
(12 tCYC execution time)
(8 tCYC execution time)
(12 tCYC execution time)
■Oscillator Circuit and PLL
• Medium-speed RC oscillator circuit (internal):
• Low-speed RC oscillator circuit (internal):
• CF oscillator circuit:
• Crystal oscillator circuit:
• PLL circuit (internal):
For system clock (approx. 1MHz)
For system clock, timer, and watchdog timer (approx. 30kHz)
For system clock
For system clock and time-of-day clock
For USB interface (see Fig. 5) and audio interface (see Fig. 6)
■Internal Reset Functions
• Power-on reset (POR) function
1) POR is activated at power-on.
2) POR release voltage can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V, and 4.35V)
by setting options.
• Low voltage detection reset (LVD) function
1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls
below a threshold level.
2) The use/disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V,
2.81V, 3.79V, and 4.28V) can be selected by setting options.
No.A2197-4/35
LC87F1K64A
■Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillators do not stop automatically.
2) There are three ways of releasing HOLD mode.
(1) Setting the reset pin to a low level.
(2) Generating a reset signal by watchdog timer or low-voltage detection
(3) Occurrence of an interrupt
• HOLD mode: Suspends instruction execution and operation of the peripheral circuits.
1) The PLL, CF, RC and crystal oscillators automatically stop operation.
Note: Low-speed RC oscillator is controlled directly by the watchdog timer and its oscillation in standby mode
is also controlled.
2) There are five ways of releasing HOLD mode.
(1) Setting the reset pin to a low level
(2) Generating a reset signal by the watchdog timer or low-voltage detection
(3) Establishing an interrupt source at one of INT0, INT1, INT2, INT4, and INT5 pins
* INT0 and INT1 HOLD mode release is available only when level detection is configured.
(4) Establishing an interrupt source at port 0
(5) Establishing an bus active interrupt source in the USB host control circuit
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer
and infrared remote control receiver circuit.
1) The PLL, CF and RC oscillators automatically stop operation.
Note: Low-speed RC oscillator is controlled directly by the watchdog timer and its oscillation in standby mode
is also controlled.
Note: The low-speed RC oscillator retains the state that is established on entry into X'tal HOLD mode if the base
timer is running with the low-speed RC oscillator selected as the base timer input clock source.
2) The state of crystal oscillator established when the X'tal HOLD mode is entered is retained.
3) There are seven ways of releasing X'tal HOLD mode.
(1) Setting the reset pin to a low level
(2) Generating a reset signal by the watchdog timer or low-voltage detection
(3) Establishing an interrupt source at one of INT0, INT1, INT2, INT4, and INT5 pins
* INT0 and INT1 X'tal HOLD mode release is available only when level detection is configured.
(4) Establishing an interrupt source at port 0
(5) Establishing an interrupt source in the base timer circuit
(6) Establishing an interrupt source in the infrared remote control receiver circuit
(7) Establishing an bus active interrupt source in the USB host control circuit
■Development Tools
• On-chip debugger: TCB87–Type B + LC87F1K64A or
TCB87–Type C (3-wire communication cable) + LC87F1K64A
■Flash ROM Programming Board
Package
Programming Board
SQFP48 (7×7)
W87F55256SQ
No.A2197-5/35
LC87F1K64A
■Flash ROM Programmer
Maker
Flash Support Group
Company (FSG)
Single
Flash Support Group
Model
Supported Version
Device
AF9709C
Rev.03.32 and later
87F064JU
(Note 2)
LC87F1K64A
AF9101/AF9103 (main unit)
Company (FSG)
Onboard
(FSG model)
+
single/ganged
SIB87 Type C (interface driver)
Our company (Note 1)
(Our company model)
Single/ganged
Our company
SKK/SKK Type C
Application version
(SANYO FWS)
1.07 and later
Onboard
SKK-DBG Type C
Chip data version
single/ganged
(SANYO FWS)
2.39 and later
LC87F1K64
(Further information on the AF series)
Flash Support Group Company (TOA ELECTRONICS, Inc.)
Phone: 053-459-1050
E-mail: sales@j- fsg.co.jp
Note 1: PC-less standalone onboard programming is possible using the FSG onboard programmer (AF9101/AF9103) and
the serial interface driver (SIB87 Type C) provided by Our company in pair.
Note 2: Dedicated programming device and program are required depending on the programming conditions. Contact Our
company or FSG if you have any questions or difficulties regarding this matter.
No.A2197-6/35
LC87F1K64A
Package Dimensions
unit : mm (typ)
3163B
36
0.5
9.0
7.0
25
24
48
13
7.0
9.0
37
1
12
0.5
0.15
(1.5)
0.1
1.7max
(0.75)
0.18
SQFP48(7X7)
LC87F1K64A
24
23
22
21
20
19
18
17
16
15
14
13
P03/AN3/DBGP1
P02/AN2/DBGP0
P01/AN1
P00/AN0
VSS2
VDD2
PWM0/MCLKO
PWM1/MCLKI
P17/T1PWMH/BUZ/SM0CK0
P16/T1PWML/SM0DA0
P15/SCK1/SM0DO
P14/SI1/SB1/SM0DA1
1
2
3
4
5
6
7
8
9
10
11
12
37
38
39
40
41
42
43
44
45
46
47
48
P73/INT3/T0IN/RMIN
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1/SM0CK1
UHADUHAD+
VDD3
VSS3
P34/UFILT
P33/AFILT
P32
P31/URX1
P30/UTX1
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
36
35
34
33
32
31
30
29
28
27
26
25
UHBD+
UHBDP25/INT5
P24/INT5/INT7/SCK4
P23/INT4/SI4
P22/INT4/SO4
P21/INT4
P20/INT4/INT6
P07/AN7/T7O/LRCK
P06/AN6/T6O/BCLK
P05/AN5/CKO/SDAT
P04/AN4/DBGP2
Pin Assignment
Top view
SQFP48 (7×7) (Lead-/halogen-free product)
No.A2197-7/35
LC87F1K64A
SQFP48
NAME
SQFP48
NAME
1
P73/INT3/T0IN/RMIN
25
P04/AN4/DBGP2
2
RES
26
P05/AN5/CKO/SDAT
3
XT1/AN10
27
P06/AN6/T6O/BCLK
4
XT2/AN11
28
P07/AN7/T7O/LRCK
5
VSS1
29
P20/INT4/INT6
6
CF1
30
P21/INT4
P22/INT4/SO4
7
CF2
31
8
VDD1
32
P23/INT4/SI4
9
P10/SO0
33
P24/INT5/INT7/SCK4
10
P11/SI0/SB0
34
P25/INT5
11
P12/SCK0
35
UHBD-
12
P13/SO1/SM0CK1
36
UHBD+
13
P14/SI1/SB1/SM0DA1
37
UHAD-
14
P15/SCK1/SM0DO
38
UHAD+
15
P16/T1PWML/SM0DA0
39
VDD3
16
P17/T1PWMH/BUZ/SM0CK0
40
VSS3
17
PWM1/MCLKI
41
P34/UFILT
18
PWM0/MCLKO
42
P33/AFILT
19
VDD2
43
P32
P31/URX1
20
VSS2
44
21
P00/AN0
45
P30/UTX1
22
P01/AN1
46
P70/INT0/T0LCP/AN8
23
P02/AN2/DBGP0
47
P71/INT1/T0HCP/AN9
24
P03/AN3/DBGP1
48
P72/INT2/T0IN
No.A2197-8/35
LC87F1K64A
System Block Diagram
Interrupt control
Standby control
ROM
CF
USB PLL
RC
Clock
generator
X’tal
PC
RES
Reset circuit
(LVD/POR)
ACC
Reset control
WDT
PLA
IR
B register
C register
SIO0
Bus interface
SIO1
Port 0
SIO4
Port 1
SMIIC0
Port 2
RAR
Timer 0
Port 3
RAM
Timer 1
Port 7
Stack pointer
Timer 4
INT0 to INT7
Noise filter
Watchdog timer
Timer 5
UART1
Timer 6
Audio interface
Timer 7
ADC
Base timer
USB host
PWM0
IFR control
receiver circuit
ALU
PSW
On-chip debugger
PWM1
No.A2197-9/35
LC87F1K64A
Pin Description
Pin Name
I/O
Description
Option
VSS1, VSS2,
VSS3
-
-power supply
No
VDD1, VDD2
-
+power supply
No
VDD3
-
USB reference voltage
Yes
Port 0
I/O
• 8-bit I/O port
Yes
• I/O can be specified in 1-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 1-bit units.
• HOLD release input
• Port 0 interrupt input
• Pin functions
AD converter input port: AN0 to AN7 (P00 to P07)
On-chip debugger pins: DBGP0 to DBGP2 (P02 to P04)
P05: System clock output / audio interface SDAT I/O
P06: Timer 6 toggle output / audio interface BCLK I/O
P07: Timer 7 toggle output / audio interface LRCK I/O
Port 1
I/O
• 8-bit I/O port
Yes
• I/O can be specified in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P10: SIO0 data output
P11: SIO0 data input / bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output / SMIIC0 clock I/O
P14: SIO1 data input / bus I/O / SMIIC0 bus I/O / data input
P15: SIO1 clock I/O / SMIIC0 data output (used in 3-wire SIO mode)
P16: Timer 1 PWML output / SMIIC0 bus I/O / data input
P17: Timer 1 PWMH output / buzzer output / SMIIC0 clock I/O
Port 2
I/O
Yes
• 6-bit I/O port
• I/O can be specified in 1-bit units
P20 to P25
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P20 to P23: INT4 input / HOLD release input / timer 1 event input /
timer 0L capture input / timer 0H capture input
P24 to P25: INT5 input / HOLD release input / timer 1 event input /
timer 0L capture input / timer 0H capture input
P20: INT6 input / timer 0L capture 1 input
P22: SIO4 data I/O
P23: SIO4 data I/O
P24: INT7 input / timer 0H capture 1 input / SIO4 clock I/O
Interrupt acknowledge types
Port 3
P30 to P34
I/O
Rising
Falling
INT4
Enable
Enable
INT5
Enable
Enable
INT6
Enable
INT7
Enable
Rising &
H Level
L Level
Enable
Disable
Disable
Enable
Disable
Disable
Enable
Enable
Disable
Disable
Enable
Enable
Disable
Disable
Falling
• 5-bit I/O port
Yes
• I/O can be specified in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P30: UART1 transmit
P31: UART1 receive
P33: Connected to audio interface PLL filter circuit (see Fig. 6).
P34: Connected to USB interface PLL filter circuit (see Fig. 5).
Continued on next page.
No.A2197-10/35
LC87F1K64A
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
No
• 4-bit I/O port
• I/O can be specified in 1-bit units
P70 to P73
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P70: INT0 input / HOLD release input / timer 0L capture input /
watchdog timer output
P71: INT1 input / HOLD release input / timer 0H capture input
P72: INT2 input / HOLD release input / timer 0 event input /
timer 0L capture input / high-speed clock counter input
P73: INT3 input (input with noise filter) / timer 0 event input /
timer 0H capture input / infrared remote control receiver input
AD converter input port: AN8 (P70), AN9 (P71)
Interrupt acknowledge types
PWM0
I/O
PWM1
Rising &
Rising
Falling
INT0
Enable
Enable
Disable
INT1
Enable
Enable
Disable
Enable
Enable
INT2
Enable
Enable
Enable
Disable
Disable
INT3
Enable
Enable
Enable
Disable
Disable
PWM0 and PWM1 output port
Falling
H Level
L Level
Enable
Enable
No
General-purpose input port
• Pin functions
PWM0: Audio interface master clock output
PWM1: Audio interface master clock input
UHAD-
I/O
USB-A port data I/O pin / general-purpose I/O port
No
I/O
USB-B port data I/O pin / general-purpose I/O port
No
RES
I/O
External reset input / internal reset output
No
XT1
I
• 32.768kHz crystal resonator input
No
UHAD+
UHBDUHBD+
• Pin functions
General-purpose input port
AD converter input port: AN10
XT2
I/O
• 32.768kHz crystal resonator output
No
• Pin functions
General-purpose I/O port
AD converter input port: AN11
CF1
I
Ceramic/crystal resonator input
No
CF2
O
Ceramic/crystal resonator output
No
No.A2197-11/35
LC87F1K64A
On-chip Debugger Pin Treatment
For the treatment of the on-chip debugger pins, refer to the separately available documents entitled "RD87 On-chip
Debugger Installation Manual."
Recommended Unused Pin Treatment
Recommended Unused Pin Treatment
Pin Name
Board
Software
P00 to P03, P05 to P07
Open
Set output low.
P04
Pull-down with a 100kΩ resistor.
-
P10 to P17
Open
Set output low.
P20 to P25
Open
Set output low.
P30 to P34
Open
Set output low.
P70 to P73
Open
Set output low.
PWM0, PWM1
Open
Set output low.
UHAD+, UHAD-
Open
Set output low.
UHBD+, UHBD-
Open
Set output low.
XT1
Pull-down with a resistor of 100kΩ or lower.
-
XT2
Open
Set output low.
Note: Since P34 is multiplexed with UFILT, it must be configured for input when the USB function is to be used.
Since P33 is multiplexed with AFILT, it must be configured for input when the audio interface PLL circuit is to be
used.
Port Output Types
The table below lists the type of port output and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in output mode.
Port Name
P00 to P07
Option Selected in
Option Type
Units of
1 bit
P10 to P17
Output Type
Pull-up Resistor
1
CMOS
Programmable
2
N-channel open drain
Programmable
P20 to P25
P30 to P34
P70
-
No
N-channel open drain
Programmable
P71 to P73
-
No
CMOS
Programmable
PWM0, PWM1
-
No
CMOS
No
UHAD+, UHAD-
-
No
CMOS
No
XT1
-
No
Input only
No
XT2
-
No
32.768kHz crystal resonator output
No
UHBD+, UHBD-
(N-channel open drain when in
general-purpose output mode)
No.A2197-12/35
LC87F1K64A
User Option Table
Option Name
Port output type
Program start
address
USB regulator
Option to be
Applied on
1 bit
P10 to P17
○
1 bit
P20 to P25
○
1 bit
P30 to P34
○
1 bit
-
○
-
USB regulator
USB regulator
(HALT mode)
Low-voltage
detection reset
function
Power-on reset
function
○
-
○
-
○
-
-
○
-
Detection function
○
-
Detection level
Power-on reset level
○
○
Option Selection
in Units of
○
(HOLD mode)
selection
Option Selected
P00 to P07
USB regulator
Main clock 8MHz
Flash-ROM Version
CMOS
N-channel open drain
CMOS
N-channel open drain
CMOS
N-channel open drain
CMOS
N-channel open drain
00000h
0FE00h
Use
Non-use
Use
Non-use
Use
Non-use
Enable
Disable
Enable: Use
Disable: Non-use
-
7 levels
-
8 levels
No.A2197-13/35
LC87F1K64A
USB Reference Power Option
When a voltage 4.5 to 5.5V is supplied to VDD1 and the internal USB reference voltage circuit is activated, the
reference voltage for USB port output is generated. The active/inactive state of the reference voltage circuit can be
switched by selecting an option. The procedure for making the option selection is described below.
Option settings
Reference voltage circuit state
(1)
(2)
(3)
(4)
Use
Use
Use
Non-use
USB regulator at HOLD mode
Use
Non-use
Non-use
Non-use
USB regulator at HALT mode
Use
Non-use
Use
Non-use
Normal mode
Active
Active
Active
Inactive
HOLD mode
Active
Inactive
Inactive
Inactive
HALT mode
Active
Inactive
Active
Inactive
USB regulator
• When the USB reference voltage circuit is made inactive, the level of the reference voltage for the USB port output is
equal to VDD1.
• Selection (2) or (3) can be used to set the reference voltage circuit inactive in HOLD or HALT mode.
• When the reference voltage circuit is activated, the current drain increases by approximately 100μA compared with
when the reference voltage circuit is inactive.
Example 1: VDD1=VDD2=3.3V
• Inactivating the reference voltage circuit (selection (4)).
• Connecting VDD3 to VDD1 and VDD2.
IC
Power supply
3.3V
VDD1
VDD2
UHAD+
/UHBD+
To USB connector
33Ω
UHAD/UHBD5pF
VDD3
2.2μF
15kΩ
UFILT
0Ω
VSS1 VSS2 VSS3
2.2μF
Example 2: VDD1=VDD2=5.0V
• Activating the reference voltage circuit (selection (1)).
• Isolating VDD3 from VDD1 and VDD2, and connecting capacitor between VDD3 and VSS.
IC
Power supply
5V
VDD1
UHAD+
/UHBD+
VDD2
UHAD/UHBD-
To USB connector
33Ω
5pF
VDD3
2.2μF
0.1μF
15kΩ
UFILT
0Ω
VSS1 VSS2 VSS3
2.2μF
(Note: Do not apply the voltage of more than 3.6V to UHAD+, UHAD-,
UHBD+ and UHBD- when the reference voltage circuit is active.
No.A2197-14/35
LC87F1K64A
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Maximum supply
Symbol
Pin/Remarks
VDD max
VDD1, VDD2, VDD3
Input voltage
VI(1)
XT1, CF1, RES
Input/output
VIO(1)
Ports 0, 1, 2, 3, 7
Conditions
VDD1=VDD2=VDD3
voltage
voltage
PWM0, PWM1
Specification
VDD[V]
min
typ
max
unit
-0.3
+6.5
-0.3
VDD+0.3
-0.3
VDD+0.3
V
XT2
Peak output
IOPH(1)
Ports 0, 1, 2
current
• When CMOS output
type is selected
-10
• Per 1 applicable pin
IOPH(2)
PWM0, PWM1
• Per 1 applicable pin
IOPH(3)
Port 3
• When CMOS output
P71 to P73
type is selected
-20
-5
• Per 1 applicable pin
High level output current
Average
IOMH(1)
Ports 0, 1, 2
output current
• When CMOS output
type is selected
(Note 1-1)
-7.5
• Per 1 applicable pin
IOMH(2)
PWM0, PWM1
Per 1 applicable pin
IOMH(3)
Port 3
• When CMOS output
P71 to P73
type is selected
-15
-3
• Per 1 applicable pin
Total output
ΣIOAH(1)
Ports 0, 2
current
ΣIOAH(2)
ΣIOAH(3)
ΣIOAH(4)
ΣIOAH(5)
Peak output
Total current of all
applicable pins
IOPL(1)
current
Port 1
Total current of all
PWM0, PWM1
applicable pins
Ports 0, 1, 2
Total current of all
PWM0, PWM1
applicable pins
Port 3
Total current of all
P71 to P73
applicable pins
UHAD+, UHAD-
Total current of all
UHBD+, UHBD-
applicable pins
P02 to P07
Per 1 applicable pin
-25
-25
-45
-10
-50
Ports 1, 2
mA
20
PWM0, PWM1
IOPL(2)
P00, P01
Per 1 applicable pin
IOPL(3)
Ports 3, 7
Per 1 applicable pin
30
10
XT2
Low level output current
Average
IOML(1)
P02 to P07
output current
Ports 1, 2
(Note 1-1)
PWM0, PWM1
IOML(2)
IOML(3)
Per 1 applicable pin
15
P00, P01
Per 1 applicable pin
Ports 3, 7
Per 1 applicable pin
20
7.5
XT2
Total output
ΣIOAL(1)
Ports 0, 2
current
ΣIOAL(2)
ΣIOAL(3)
ΣIOAL(4)
ΣIOAL(5)
Allowable power
Total current of all
45
applicable pins
Pd max
Port 1
Total current of all
PWM0, PWM1
applicable pins
Ports 0, 1, 2
Total current of all
PWM0, PWM1
applicable pins
Ports 3, 7
Total current of all
XT2
applicable pins
UHAD+, UHAD-
Total current of all
UHBD+, UHBD-
applicable pins
SQFP48(7×7)
Ta=-40 to +85°C
45
80
15
50
140
dissipation
Operating ambient
Topr
Temperature
Storage ambient
temperature
Tstg
-40
+85
-55
+125
mW
°C
Note 1-1: The average output current is an average of current values measured over 100ms intervals.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
No.A2197-15/35
LC87F1K64A
Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Operating
Symbol
VDD(1)
Pin/Remarks
VDD1=VDD2=VDD3
supply voltage
Conditions
Specification
VDD[V]
0.245μs ≤ tCYC ≤ 200μs
0.245μs ≤ tCYC ≤ 0.383μs
(Note 2-1)
USB circuit active.
min
typ
max
unit
3.0
5.5
3.0
5.5
2.7
5.5
2.0
5.5
0.490μs ≤ tCYC ≤ 200μs
Except for onboard
programming mode
Memory
VHD
VDD1=VDD2=VDD3
retention supply
RAM and register contents are
retained in HOLD mode
voltage
High level
VIH(1)
input voltage
Low level
Ports 0, 1, 2, 3, 7
2.7 to 5.5
PWM0, PWM1
VIH(2)
XT1, XT2, CF1, RES
VIL(1)
Ports 1, 2, 3, 7
input voltage
VIL(2)
VIL(3)
Port 0
PWM0, PWM1
VIL(4)
VIL(5)
Instruction
XT1, XT2, CF1, RES
tCYC
cycle time
USB circuit active.
(Note 2-2)
Except for onboard
programming mode
External
FEXCF(1)
CF1
system clock
0.3VDD
VDD
+0.7
2.7 to 5.5
0.75VDD
4.0 to 5.5
VSS
2.7 to 4.0
VSS
4.0 to 5.5
VSS
2.7 to 4.0
VSS
0.2VDD
2.7 to 5.5
VSS
0.25VDD
3.0 to 5.5
0.245
200
3.0 to 5.5
0.245
0.383
2.7 to 5.5
0.490
200
3.0 to 5.5
0.1
12
V
VDD
0.1VDD
+0.4
0.2VDD
0.15VDD
+0.4
μs
• CF2 pin open
• System clock frequency
frequency
division ratio =1/1
• External system clock duty
=50±5%
MHz
• CF2 pin open
• System clock frequency
division ratio =1/1
2.7 to 5.5
0.1
6
• External system clock duty
=50±5%
Oscillation
FmCF
CF1, CF2
12MHz ceramic oscillation
frequency range
mode
(Note 2-3)
See Fig. 1.
FmRC
Internal medium-speed RC
oscillation
FmSRC
Internal low-speed RC
oscillation
FsX'tal
XT1, XT2
3.0 to 5.5
12
MHz
2.7 to 5.5
0.5
1.0
2.0
2.7 to 5.5
15
30
60
kHz
32.768kHz crystal oscillation
mode
2.7 to 5.5
32.768
See Fig. 2.
Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a
division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
No.A2197-16/35
LC87F1K64A
Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
High level input
Symbol
IIH(1)
current
Pin/Remarks
Conditions
Ports 0, 1, 2, 3, 7
Output disabled
RES
Pull-up resistor off
PWM0, PWM1
VIN=VDD
(Including output Tr's off
Specification
VDD[V]
min
typ
max
unit
2.7 to 5.5
1
2.7 to 5.5
1
2.7 to 5.5
15
leakage current)
IIH(2)
Low level input
XT1, XT2
Input port configuration
IIH(3)
CF1
VIN=VDD
VIN=VDD
IIL(1)
Ports 0, 1, 2, 3, 7
Output disabled
RES
Pull-up resistor off
PWM0, PWM1
VIN=VSS
(Including output Tr's off
current
2.7 to 5.5
-1
2.7 to 5.5
-1
μA
leakage current)
IIL(2)
XT1, XT2
Input port configuration
IIL(3)
CF1
VIN=VSS
VIN=VSS
2.7 to 5.5
-15
High level output
VOH(1)
Ports 0, 1, 2, 3
IOH=-1mA
4.5 to 5.5
VDD-1
voltage
VOH(2)
P71 to P73
VOH(3)
3.0 to 5.5
VDD-0.4
2.7 to 5.5
VDD-0.4
VOH(4)
PWM0, PWM1
IOH=-10mA
4.5 to 5.5
VDD-1.5
VOH(5)
P05 to P07
IOH=-1.6mA
3.0 to 5.5
VDD-0.4
IOH=-1mA
2.7 to 5.5
VDD-0.4
IOL=30mA
4.5 to 5.5
1.5
IOL=5mA
3.0 to 5.5
0.4
VOH(6)
Low level output
VOL(1)
voltage
VOL(2)
(Note 3-1)
P00, P01
VOL(3)
IOL=2.5mA
2.7 to 5.5
0.4
VOL(4)
Ports 0, 1, 2
IOL=10mA
4.5 to 5.5
1.5
VOL(5)
PWM0, PWM1
IOL=1.6mA
3.0 to 5.5
0.4
IOL=1mA
2.7 to 5.5
0.4
IOL=1.6mA
3.0 to 5.5
0.4
IOL=1mA
2.7 to 5.5
VOH=0.9VDD
4.5 to 5.5
15
35
80
2.7 to 4.5
18
50
150
VOL(6)
VOL(7)
XT2
Ports 3, 7
VOL(8)
Pull-up resistance
IOH=-0.4mA
IOH=-0.2mA
Rpu(1)
Ports 0, 1, 2, 3, 7
Rpu(2)
Hysteresis voltage
VHYS
RES
Ports 1, 2, 3, 7
Pin capacitance
CP
All pins
V
0.4
kΩ
2.7 to 5.5
0.1VDD
V
2.7 to 5.5
10
pF
For pins other than those
under test:
VIN=VSS
f=1MHz
Ta=25°C
Note 3-1: When the CKO system clock output function (P05) or the audio interface output function (P05 to P07) is used.
No.A2197-17/35
LC87F1K64A
Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter
Symbol
Frequency
tSCK(1)
Low level
tSCKL(1)
Pin/
Conditions
Remarks
SCK0(P12)
Specification
VDD[V]
See Fig. 9.
tSCKH(1)
pulse width
tSCKHA(1a)
typ
max
unit
2
1
pulse width
High level
min
1
• Continuous data transmission/
reception mode
• USB, AIF, SIO4 not used at the
4
same time.
• See Fig. 9.
Input clock
• (Note 4-1-2)
tSCKHA(1b)
• Continuous data transmission/
reception mode
2.7 to 5.5
tCYC
• USB used at the same time
• AIF, SIO4 not used at the same
7
time.
• See Fig. 9.
• (Note 4-1-2)
tSCKHA(1c)
• Continuous data transmission/
reception mode
• USB, AIF, SIO4 used at the
9
same time.
• See Fig. 9.
Serial clock
• (Note 4-1-2)
Frequency
tSCK(2)
Low level
tSCKL(2)
• When CMOS output type is
4/3
selected.
1/2
• See Fig. 9.
pulse width
High level
SCK0(P12)
tSCK
tSCKH(2)
1/2
pulse width
tSCKHA(2a)
• Continuous data transmission/
reception mode
• USB, AIF, SIO4 not used at the
tSCKH(2)
same time.
+2tCYC
• When CMOS output type is
tSCKH(2)
+
(10/3)tCYC
Output clock
selected.
• See Fig. 9.
tSCKHA(2b)
• Continuous data transmission/
reception mode
2.7 to 5.5
• USB used at the same time
• AIF, SIO4 not used at the same
time.
tSCKH(2)
+2tCYC
• When CMOS output type is
tSCKH(2)
+
tCYC
(19/3)tCYC
selected.
• See Fig. 9.
tSCKHA(2c)
• Continuous data transmission/
reception mode
• USB, AIF, SIO4 used at the
same time
• When CMOS output type is
tSCKH(2)
+2tCYC
tSCKH(2)
+
(25/3)tCYC
selected.
• See Fig. 9.
Note 4-1-1: These specifications are theoretical values. Margins must be allowed according to the actual operating
conditions.
Note 4-1-2: In an application where the serial clock input is to be used in continuous data transmission/reception mode,
the time from SI0RUN being set when serial clock is high to the falling edge of the first serial clock must be
longer than tSCKHA.
Continued on next page.
No.A2197-18/35
LC87F1K64A
Continued from preceding page.
Serial input
Parameter
Data setup time
tsDI(1)
Pin/
Data hold time
SB0(P11),
Input clock
tdDO(1)
Specification
VDD[V]
min
• Must be specified with respect to
rising edge of SIOCLK
• See Fig. 9.
thDI(1)
time
Conditions
Remarks
SI0(P11)
Output delay
typ
max
unit
0.03
2.7 to 5.5
0.03
SO0(P10),
SB0(P11)
• Continuous data transmission/
(1/3)tCYC
reception mode
+0.05
• (Note 4-1-3)
tdDO(2)
• Synchronous 8-bit mode
1tCYC
• (Note 4-1-3)
tdDO(3)
μs
+0.05
2.7 to 5.5
Output clock
Serial output
Symbol
(Note 4-1-3)
(1/3)tCYC
+0.05
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be defined as the time up to the beginning of
output state change in open drain output mode. See Fig. 9.
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Input clock
Symbol
Frequency
tSCK(3)
Low level
tSCKL(3)
Pins/
Conditions
Remarks
SCK1(P15)
• See Fig. 9.
Frequency
SCK1(P15)
• When CMOS output type is
• See Fig. 9.
tSCKL(4)
pulse width
High level
2
2.7 to 5.5
1/2
tSCK
tSCKH(4)
1/2
Serial input
SB1(P14),
SI1(P14)
• Must be specified with respect to
Data hold time
0.03
rising edge of SIOCLK.
• See Fig. 9.
thDI(2)
2.7 to 5.5
0.03
Output delay
Serial output
tsDI(2)
unit
1
pulse width
Data setup time
max
1
selected.
Low level
typ
tCYC
tSCKH(3)
tSCK(4)
min
2
2.7 to 5.5
pulse width
High level
Specification
VDD[V]
pulse width
Output clock
Serial clock
Parameter
time
tdD0(4)
SO1(P13),
SB1(P14)
μs
• Must be specified with respect to
falling edge of SIOCLK.
• Must be specified as the time up
to the beginning of output state
change in open drain output
2.7 to 5.5
(1/3)tCYC
+0.05
mode.
• See Fig. 9.
Note 4-2-1: These specifications are theoretical values. Margins must be allowed according to the actual operating
conditions.
No.A2197-19/35
LC87F1K64A
3. SIO4 Serial I/O Characteristics (Note 4-3-1)
Parameter
Symbol
Frequency
tSCK(5)
Low level
tSCKL(5)
Pin/
Conditions
Remarks
SCK4(P24)
Specification
VDD[V]
See Fig. 9.
tSCKH(5)
pulse width
tSCKHA(5a)
typ
max
unit
2
1
pulse width
High level
min
1
• USB, SIO0 continuous transfer
mode,
AIF not used at the same time.
4
Input clock
• See Fig. 9.
• (Note 4-3-2)
tSCKHA(5b)
• USB used at the same time.
2.7 to 5.5
tCYC
• SIO0 continuous transfer mode,
AIF not used at the same time.
7
• See Fig. 9.
• (Note 4-3-2)
tSCKHA(5c)
• USB, SIO0 continuous transfer
mode used at the same time.
• AIF not used at the same time.
10
• See Fig. 9.
Serial clock
• (Note 4-3-2)
Frequency
tSCK(6)
Low level
tSCKL(6)
SCK4(P24)
• When CMOS output type is
4/3
selected.
1/2
• See Fig. 9.
pulse width
High level
tSCKH(6)
pulse width
tSCKHA(6a)
• USB, SIO0 continuous transfer
mode
tSCKH(6)
AIF not used at the same time.
• When CMOS output type is
selected.
Output clock
tSCK
1/2
tSCKH(6)
+
+
(5/3)tCYC
(10/3)tCYC
tSCKH(6)
tSCKH(6)
• See Fig. 9.
tSCKHA(6b)
• USB used at the same time.
2.7 to 5.5
• SIO0 continuous transfer mode
AIF not used at the same time.
• When CMOS output type is
selected.
+
+
(5/3)tCYC
(19/3)tCYC
tSCKH(6)
tSCKH(6)
tCYC
• See Fig. 9.
tSCKHA(6c)
• USB, SIO0 continuous transfer
mode used at the same time
• AIF not used at the same time.
• When CMOS output type is
selected.
+
+
(5/3)tCYC
(28/3)tCYC
• See Fig. 9.
Serial input
Data setup time
SO4(P22),
SI4(P23)
• Must be specified with respect to
Data hold time
0.03
rising edge of SIOCLK.
• See Fig. 9.
thDI(3)
2.7 to 5.5
0.03
Output delay
Serial output
tsDI(3)
time
tdDO(5)
SO4(P22),
SI4(P23)
μs
• Must be specified with respect to
falling edge of SIOCLK.
• Must be specified as the time up
to the beginning of output state
2.7 to 5.5
(1/3)tCYC
+0.05
change in open drain output mode
• See Fig. 9.
Note 4-3-1: These specifications are theoretical values. Margins must be allowed according to the actual operating
conditions.
Note 4-3-2: In an application where the serial clock input is to be used, the time from SI4RUN being set when serial clock
is high to the falling edge of the first serial clock must be longer than tSCKHA when continuous data
transmission/reception is started.
No.A2197-20/35
LC87F1K64A
4-1. SMIIC0 Simple SIO Mode I/O Characteristics (Note 4-4-1)
Input clock
Symbol
Pin/Remarks
Frequency
tSCK(7)
SM0CK0(P17),
Low level
tSCKL(7)
SM0CK1(P13)
Conditions
See Fig. 9.
tSCKH(7)
typ
tSCK(8)
SM0CK0(P17),
Low level
tSCKL(8)
SM0CK1(P13)
• When CMOS output type is
tCYC
4/3
1/2
2.7 to 5.5
tSCK
tSCKH(8)
1/2
pulse width
Serial input
SM0DA0(P16),
SM0DA1(P14)
• Must be specified with
Data hold time
• See Fig. 9.
thDI(4)
0.03
respect to rising edge of
SIOCLK.
2.7 to 5.5
0.03
Output delay
Serial output
tsDI(4)
unit
2/3
selected.
• See Fig. 9.
pulse width
Data setup time
max
2/3
Frequency
High level
min
4/3
2.7 to 5.5
pulse width
High level
Specification
VDD[V]
pulse width
Output clock
Serial clock
Parameter
time
tdDO(6)
SM0DO(P15),
SM0DA0(P16),
SM0DA1(P14)
μs
• Must be specified with
respect to falling edge of
SIOCLK.
• Must be specified as the
time to the beginning of
2.7 to 5.5
(1/3)tCYC
+0.05
output state change.
• See Fig. 9.
Note 4-4-1: These specifications are theoretical values. Margins must be allowed according to the actual operating
conditions.
No.A2197-21/35
LC87F1K64A
2
4-2. SMIIC0 I C Mode I/O Characteristics (Note 4-5-1)
Input clock
Symbol
Pin/Remarks
Frequency
tSCL
SM0CK0(P17),
Low level
tSCLL
SM0CK1(P13)
Conditions
Specification
VDD[V]
See Fig. 11.
2.7 to 5.5
pulse width
High level
tSCLH
typ
tSCLx
SM0CK0(P17),
Must be specified as the time up
Low level
tSCLLx
SM0CK1(P13)
to the beginning of output state
change.
pulse width
Tfilt
10
1/2
2.7 to 5.5
tSCL
1/2
pulse width
tsp
unit
2.5
tSCLHx
SM0CK, SM0DA pin
max
2
Frequency
HIghlevel
min
5
pulse width
Output clock
Serial clock
Parameter
SM0CK0(P17),
input spike suppression
SM0CK1(P13),
time
SM0DA0(P16),
See Fig. 11.
2.7 to 5.5
1
Tfilt
SM0DA1(P14)
between start and
stop
tBUF
SM0CK0(P17),
See Fig. 11.
SM0CK1(P13),
input
Bus relinquish time
2.5
SM0DA0(P16),
Tfilt
SM0DA1(P14)
tBUFx
• Standard clock mode
• Must be specified as the time up
Output
to the beginning of output state
2.7 to 5.5
5.5
change.
μs
• High-speed clock mode
• Must be specified as the time up
1.6
to the beginning of output state
change.
Start, restart
tHD; STA
condition hold time
SM0CK0(P17),
input
SM0CK1(P13),
• When SMIIC register control bit
SHDS=0
SM0DA0(P16),
• See Fig. 11.
SM0DA1(P14)
• When SMIIC register control bit
2.0
Tfilt
SHDS=1
2.5
• See Fig. 11.
tHD; STAx
• Standard clock mode
• Must be specified as the time up
2.7 to 5.5
4.1
Output
to the beginning of output state
change.
μs
• High-speed clock mode
• Must be specified as the time up
1.0
to the beginning of output state
change.
SM0CK0(P17),
See Fig. 11.
SM0CK1(P13),
1.0
SM0DA0(P16),
Tfilt
SM0DA1(P14)
tSU; STAx
• Standard clock mode
• Must be specified as the time up
to the beginning of output state
Output
setup time
tSU; STA
input
Restart condition
2.7 to 5.5
5.5
change.
μs
• High-speed clock mode
• Must be specified as the time up
to the beginning of output state
1.6
change.
Continued on next page.
No.A2197-22/35
LC87F1K64A
Continued from preceding page.
Stop condition
setup time
input
Parameter
Symbol
Pin/Remarks
tSU; STO
SM0CK0(P17),
Specification
Conditions
VDD[V]
min
typ
max
unit
See Fig. 11.
SM0CK1(P13),
1.0
Tfilt
SM0DA0(P16),
tSU; STOx
SM0DA1(P14)
• Standard clock mode
• Must be specified as the time up
Output
to the beginning of output state
2.7 to 5.5
4.9
change.
μs
• High-speed clock mode
• Must be specified as the time up
1.1
to the beginning of output state
Input
change.
Data hold time
tHD; DAT
SM0CK0(P17),
See Fig. 11.
SM0CK1(P13),
0
Data setup time
Input
Output
SM0DA0(P16),
tHD; DATx
SM0DA1(P14)
Must be specified as the time up
Tfilt
1
to the beginning of output state
1.5
change.
tSU; DAT
SM0CK0(P17),
See Fig. 11.
SM0CK1(P13),
1
SM0DA0(P16),
Output
2.7 to 5.5
tSU; DATx
SM0DA1(P14)
Must be specified as the time up
2.7 to 5.5
Tfilt
1tSCL-
to the beginning of output state
1.5Tfilt
change.
Note 4-5-1: These specifications are theoretical values. Margins must be allowed according to the actual operating
conditions.
Note 4-5-2: The value of Tfilt is determined by bits 7 and 6 (BRP1 and BRP0) of the SMIC0BRG register and the system
clock frequency.
BRP1
BRP0
Tfilt
0
0
(1/3) tCYC×1
0
1
(1/3) tCYC×2
1
0
(1/3) tCYC×3
1
1
(1/3) tCYC×4
Set the value of the BRP1 and BRP0 bits so that the value of Tfilt falls within the following value range:
250ns ≥ Tfilt > 140ns
Note 4-5-3: For standard clock mode operation, set up the SMIC0BRG register so that the following conditions are
satisfied:
250ns ≥ Tfilt > 140ns
BRDQ (bit5) = 1
SCL frequency value ≤ 100kHz
For high-speed clock mode operation, set up the SMIC0BRG register so that the following conditions are
satisfied:
250ns ≥ Tfilt > 140ns
BRDQ (bit5) = 1
SCL frequency value ≤ 400kHz
No.A2197-23/35
LC87F1K64A
Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
High/low level
tPIH(1)
INT0(P70),
pulse width
tPIL(1)
INT1(P71),
INT2(P72),
INT4(P20 to P23),
Conditions
Specification
VDD[V]
min
typ
max
unit
• Interrupt source flag can be
set.
• Event inputs for timer 0/1 are
enabled.
2.7 to 5.5
1
2.7 to 5.5
2
2.7 to 5.5
64
2.7 to 5.5
256
2.7 to 5.5
4
2.7 to 5.5
200
INT5(P24 to P25),
INT6(P20),
INT7(P24)
tPIH(2)
INT3(P73) when
tPIL(2)
noisefilter time constant
is 1/1.
• Interrupt source flag can be
set.
• Event inputs for timer 0 are
tCYC
enabled.
tPIH(3)
INT3(P73) when
tPIL(3)
noisefilter time constant
• Interrupt source flag can be
set.
is 1/32.
• Event inputs for timer 0 are
tPIH(4)
INT3(P73) when
• Interrupt source flag can be
tPIL(4)
noisefilter time constant
enabled.
set.
is 1/128.
• Event inputs for timer 0 are
RMIN(P73)
Recognized as a signal by
enabled.
tPIL(5)
infrared remote control
receiver circuit
tPIL(6)
RES
Resetting is enabled.
RMCK
(Note 5-1)
μs
Note 5-1: Denotes the reference frequency of the infrared remote control receiver circuit (1tCYC to 128tCYC or source
oscillation frequency of the subclock)
No.A2197-24/35
LC87F1K64A
AD Converter Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
<12-bit AD Converter Mode>
Parameter
Symbol
Pin/Remarks
Resolution
N
AN0(P00)
Absolute accuracy
ET
to AN7(P07)
Conversion time
TCAD
VAIN
VDD[V]
min
typ
3.0 to 5.5
AN8(P70)
AN9(P71)
unit
bit
3.0 to 5.5
See conversion time
4.0 to 5.5
32
115
3.0 to 5.5
64
115
3.0 to 5.5
VSS
VDD
(Note 6-2)
AN11(XT2)
max
12
(Note 6-1)
calculation formulas.
AN10(XT1)
Analog input
Specification
Conditions
voltage range
Analog port input
IAINH
VAIN=VDD
3.0 to 5.5
current
IAINL
VAIN=VSS
3.0 to 5.5
±16
1
-1
LSB
μs
V
μA
<8-bit AD Converter Mode>
Parameter
Symbol
Pin/Remarks
Resolution
N
AN0(P00)
Absolute accuracy
ET
to AN7(P07)
Conversion time
TCAD
VAIN
VDD[V]
min
typ
3.0 to 5.5
AN8(P70)
AN9(P71)
unit
8
bit
3.0 to 5.5
See conversion time
4.0 to 5.5
20
90
3.0 to 5.5
40
90
3.0 to 5.5
VSS
VDD
(Note 6-2)
AN11(XT2)
max
(Note 6-1)
calculation formulas.
AN10(XT1)
Analog input
Specification
Conditions
voltage range
A Analog port input
IAINH
VAIN=VDD
3.0 to 5.5
current
IAINL
VAIN=VSS
3.0 to 5.5
±1.5
1
-1
LSB
μs
V
μA
Conversion time calculation formulas :
12-bits AD Converter Mode : TCAD (Conversion time) = ((52/(AD division ratio))+2) × (1/3) × tCYC
8-bits AD Converter Mode : TCAD (Conversion time) = ((32/(AD division ratio))+2) × (1/3) × tCYC
<Recommended Operating Conditions>
External
Supply Voltage
System Clock
Cycle Time
AD Frequency
Oscillator
Range
Division
tCYC [ns]
Division Ratio
FmCF[MHz]
VDD[V]
4.0 to 5.5
(SYSDIV)
1/1
250
1/8
34.8
21.5
3.0 to 5.5
1/1
250
1/16
69.5
42.8
12
Conversion Time (TCAD)[μs]
12-bit AD
8-bit AD
(ADDIV)
Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be
measured in the microcontroller’s state in which no I/O operations occur at the pins adjacent to the analog input
channel.
Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process until the
time the conversion result register is loaded with a complete digital conversion value corresponding to the
analog input value.
The conversion time is doubled in the following cases:
• The AD conversion is carried out in the 12-bit AD conversion mode for the first time after a system reset.
• The AD conversion is carried out for the first time after the AD conversion mode is switched from 8-bit to
12-bit AD conversion mode.
No.A2197-25/35
LC87F1K64A
Power-on Reset (POR) Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Conditions
Option
selected voltage
POR release voltage
Detection voltage
PORRL
POUKS
unknown state
Power supply rise
min
typ
PORIS
unit
Select from option
1.67V
1.55
1.67
1.79
(Note 7-1)
1.97V
1.85
1.97
2.09
2.07V
1.95
2.07
2.19
2.37V
2.25
2.37
2.49
2.57V
2.45
2.57
2.69
2.87V
2.75
2.87
2.99
3.86V
3.73
3.86
3.99
4.35V
4.21
4.35
4.49
0.7
0.95
See Fig. 13
(Note 7-2)
time
max
Power supply rise time from
100
VDD=0V to 1.6V
V
ms
Note 7-1: The POR release level can be selected out of 8 levels only when LDV reset function is disabled.
Note 7-2: POR is in unknown state before transistors start operation.
Low Voltage Detection (LVD) Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Conditions
Option
selected voltage
LVD reset voltage
LVDET
(Note 8-2)
LVUKS
Low voltage
detection
1.81
1.91
2.01
2.01V
1.91
2.01
2.11
2.31V
2.21
2.31
2.41
2.51V
2.41
2.51
2.61
2.81V
2.71
2.81
2.91
3.79V
3.69
3.79
3.89
4.28V
4.18
4.28
4.38
minimum width
1.91V
55
2.01V
55
2.31V
55
2.51V
55
2.81V
55
3.79V
60
4.28V
65
See Fig. 14.
0.7
(Note 8-4)
TLVDW
unit
1.91V
LVHYS
unknown state
max
See Fig. 14.
(Note 8-3)
Detection voltage
typ
Select from option.
(Note 8-1)
LVD hysteresis width
min
V
mV
0.95
V
LVDET-0.5V
See Fig. 15.
0.2
ms
(Reply sensitivity)
Note 8-1: The LVD reset level can be selected out of 7 levels only when the LVD reset function is enabled.
Note 8-2: LVD reset voltage specification values do not include hysteresis voltage.
Note 8-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large
current flows through port.
Note 8-4: LVD is in an unknown state before transistors start operation.
No.A2197-26/35
LC87F1K64A
Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Normal mode
IDDOP(1)
Pin/
Conditions
Remarks
consumption
VDD1
=VDD2
• FsX'tal=32.768kHz crystal oscillation mode
current
=VDD3
• System clock set to 12MHz side
Specification
VDD[V]
min
typ
max
4.5 to 5.5
9.8
18
3.0 to 3.6
5.7
11
4.5 to 5.5
15
28
3.0 to 3.6
8.1
15
4.5 to 5.5
6.7
12
3.0 to 3.6
4.2
7.1
2.7 to 3.0
3.5
5.8
4.5 to 5.5
0.77
2.8
3.0 to 3.6
0.46
1.5
2.7 to 3.0
0.39
1.3
4.5 to 5.5
28
170
3.0 to 3.6
18
100
2.7 to 3.0
16
87
4.5 to 5.5
45
124
3.0 to 3.6
18
60
2.7 to 3.0
14
48
4.5 to 5.5
4.0
7.0
unit
• FmCF=12MHz ceramic oscillation mode
(Note 9-1)
• Internal PLL oscillation stopped
(Note 9-2)
• Internal low-/medium-speed RC oscillation
stopped
• USB circuit stopped
• 1/1 frequency division ratio
IDDOP(2)
• FmCF=12MHz ceramic oscillation mode
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal PLL oscillation mode active
• Internal low-/medium-speed RC oscillation
stopped
• USB circuit active
mA
• 1/1 frequency division ratio
IDDOP(3)
• FmCF=12MHz ceramic oscillation mode
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 6MHz side
• Internal low-/medium-speed RC oscillation
stopped
• 1/2 frequency division ratio
IDDOP(4)
• External oscillation FmCF stopped
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to internal medium-speed RC
oscillation
• Internal low-speed RC oscillation stopped
• 1/2 frequency division ratio
IDDOP(5)
• External oscillation FsX'tal /FmCF stopped
• System clock set to internal low-speed RC
oscillation
• Internal medium-speed RC oscillation stopped
• 1/1 frequency division ratio
IDDOP(6)
• External oscillation FmCF stopped
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal low-/medium-speed RC oscillation
stopped
• 1/2 frequency division ratio
HALT mode
IDDHALT(1)
μA
• HALT mode
consumption
• FmCF=12MHz ceramic oscillation mode
current
• FsX'tal=32.768kHz crystal oscillation mode
(Note 9-1)
• System clock set to 12MHz side
(Note 9-2)
• Internal PLL oscillation stopped
mA
• Internal low-/medium-speed RC oscillation
stopped
3.0 to 3.6
2.2
3.8
• USB circuit stopped
• 1/1 frequency division ratio
Note 9-1: The consumption current value do not include current that flows into the output transistors and internal pull-up
resistors.
Note 9-2: The consumption current values do not include operational current of LVD (Low Voltage Detection) function if
not specified.
Continued on next page.
No.A2197-27/35
LC87F1K64A
Continued from preceding page.
Parameter
HALT mode
Symbol
IDDHALT(2)
Pin/
Conditions
Remarks
Specification
VDD[V]
min
typ
max
4.5 to 5.5
9.2
18
3.0 to 3.6
4.7
8.6
4.5 to 5.5
2.5
4.5
3.0 to 3.6
1.3
2.3
2.7 to 3.0
1.1
1.8
4.5 to 5.5
0.41
1.5
3.0 to 3.6
0.20
0.72
2.7 to 3.0
0.17
0.53
4.5 to 5.5
7.2
95
3.0 to 3.6
4.0
51
2.7 to 3.0
3.4
43
4.5 to 5.5
30
112
3.0 to 3.6
8.4
51
2.7 to 3.0
5.8
40
• HOLD mode
4.5 to 5.5
0.28
67
• CF1=VDD or open
3.0 to 3.6
0.22
35
2.7 to 3.0
0.21
30
4.5 to 5.5
2.8
70
3.0 to 3.6
2.3
38
2.7 to 3.0
2.1
33
4.5 to 5.5
0.98
68
3.0 to 3.6
0.62
36
2.7 to 3.0
0.51
31
unit
• HALT mode
consumption
VDD1
=VDD2
• FmCF=12MHz ceramic oscillation mode
current
=VDD3
• FsX'tal=32.768kHz crystal oscillation mode
(Note 9-1)
• System clock set to 12MHz side
(Note 9-2)
• Internal PLL oscillation active
• Internal low-/medium-speed RC oscillation
stopped
• USB circuit active
•1/1 frequency division ratio
IDDHALT(3)
• HALT mode
• FmCF=12MHz ceramic oscillation mode
mA
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 6MHz side
• Internal low-/medium-speed RC oscillation
stopped
• 1/2 frequency division ratio
IDDHALT(4)
• HALT mode
• External oscillation FmCF stopped
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to internal medium-speed RC
oscillation
• Internal low-speed RC oscillation stopped
•1/2 frequency division ratio
IDDHALT(5)
• HALT mode
• External oscillation FsX'tal /FmCF stopped
• System clock set to internal low-speed RC
oscillation
• Internal medium-speed RC oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(6)
• HALT mode
• External oscillation FmCF stopped
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal low-/medium-speed RC oscillation
stopped.
• 1/2 frequency division ratio
HOLD mode
IDDHOLD(1)
consumption
current
(Note 9-1)
(Note 9-2)
(External clock mode)
IDDHOLD(2)
• HOLD mode
• LVD option selected
• CF1=VDD or open
(External clock mode)
IDDHOLD(3)
• HOLD mode
• Internal timer type watchdog timer active
(Internal low-speed RC oscillation circuit active)
• CF1=VDD or open
(External clock mode)
X'tal HOLD
IDDHOLD(4)
mode
consumption
(Note 9-2)
4.5 to 5.5
26
106
3.0 to 3.6
6.1
49
• FsX'tal=32.768kHz crystal oscillation mode
2.7 to 3.0
3.8
38
• X'tal HOLD mode
4.5 to 5.5
1.0
68
3.0 to 3.6
0.64
36
2.7 to 3.0
0.53
31
(External clock mode)
current
(Note 9-1)
• X'tal HOLD mode
• CF1=VDD or open
IDDHOLD(5)
• CF1=VDD or open
(External clock mode)
• FmSRC=30kHz internal low-speed RC oscillation
mode
μA
Note 9-1: The consumption current value do not include current that flows into the output transistors and internal pull-up
resistors.
Note 9-2: The consumption current values do not include operational current of LVD (Low Voltage Detection) function if
not specified.
No.A2197-28/35
LC87F1K64A
USB Characteristics and Timing at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Conditions
Pin/Remarks
min
typ
max
unit
High level output
VOH(USB)
• 15kΩ±5% to GND
2.8
3.6
V
Low level output
VOL(USB)
• 1.5kΩ±5% to 3.6V
0.0
0.3
V
Output signal crossover voltage
VCRS
1.3
2.0
V
Differential input sensitivity
VDI
• |(UHAD+) – (UHAD–)|
0.2
• |(UHBD+) – (UHBD–)|
V
Differential input common mode range
VCM
0.8
2.5
V
High level input
VIH(USB)
2.0
3.6
V
Low level input
VIL(USB)
0.0
0.8
V
Rise time (full-speed)
tFR
RS=33Ω, CL=50pF
4
20
ns
Fall time (full-speed)
tFF
RS=33Ω, CL=50pF
4
20
ns
Rise time (low-speed)
tLR
RS=33Ω, CL=200 to 600pF
75
300
ns
Fall time (low-speed)
tLF
RS=33Ω, CL=200 to 600pF
75
300
ns
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Onboard
Symbol
IDDFW(1)
programming
Pin/Remarks
VDD1
Conditions
VDD[V]
min
typ
max
unit
• Excluding power dissipation in
the microcontroller block
current
Programming time
Specification
tFW(1)
• Erase operation
tFW(2)
• Write operation
3.0 to 5.5
3.0 to 5.5
5
10
mA
20
30
ms
40
60
μs
No.A2197-29/35
LC87F1K64A
Main System Clock Oscillation
The characteristics of a sample main system clock oscillator circuit shown in Table 1 are measured using a Our
specification oscillation characteristics evaluation board and external components with circuit constant values with which
the resonator vendor confirmed normal and stable oscillation.
Table 1 shows the characteristics of a oscillator circuit when USB host function is not used. If USB host function is to be
used, it is absolutely recommended to use a resonator that satisfies the precision and stability according to the USB
standards (±500ppm)
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Resonator
Circuit Constant
Nominal
Vendor Name
Frequency
Resonator Name
Operating
Oscillation
Voltage
Stabilization Time
C1
C2
Rd1
Range
typ
max
[pF]
[pF]
[Ω]
[V]
[ms]
[ms]
(33)
(33)
470
3.0 to 5.5
0.1
0.5
Remarks
C1 and C2
12MHz
MURATA
CSTCE12M0GH5L**-R0
integrated
SMD type
The oscillation stabilization time is required for the oscillator to get stabilized in the following cases (see Figure 4):
• Until oscillation is stabilized after VDD goes above the operating voltage lower limit
• Until oscillation is stabilized after the instruction for starting the main clock oscillator circuit is executed
• Until oscillation is stabilized after HOLD mode is released.
• Until oscillation is stabilized after X'tal HOLD mode is released with CFSTOP (OCR register, bit 0) set to 0 and
oscillation is started.
Subsystem Clock Oscillation
Table 2 shows the characteristics of a sample subsystem clock oscillator circuit that are measured using a Our
specification oscillation characteristics evaluation board and external components with circuit constant values with
which the resonator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Resonator
Nominal
Vendor Name
Frequency
Circuit Constant
Resonator
Name
Operating
Oscillation
Voltage
Stabilization Time
C3
C4
Rf
Rd2
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[s]
[s]
18
18
Open
680k
2.7 to 5.5
1.1
3.0
Remarks
Applicable CL
32.768kHz
EPSON TOYOCOM
MC-306
value=12.5pF
SMD type
The oscillation stabilization time is required for the oscillator to get stabilized in the following cases (see Figure 4):
• Until oscillation is stabilized after the instruction for starting the subclock oscillator circuit is executed
• Until oscillation is stabilized after HOLD mode is released with EXTOSC (OCR register, bit 6) set to 1 and oscillation
is started.
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
XT1
CF2
Rf
Rd1
C1
C2
XT2
C3
Rd2
C4
CF
X’tal
Figure 1 CF Oscillator Circuit
Figure 2 Crystal Oscillator Circuit
No.A2197-30/35
LC87F1K64A
0.5VDD
Figure 3 AC Timing Measurement Point
VDD
Operating VDD lower limit
Power supply
GND
Reset time
RES
Internal
medium-speed
RC oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Execute oscillation enable instruction
Operating mode
Unknown
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD release signal
HOLD release signal valid
Internal
medium-speed
RC oscillation
tmsCF
CF1, CF2
tmsX’tal
* If operation is enabled before
entry into HOLD mode
XT1, XT2
Operating mode
HOLD
HALT
HOLD Release Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Time
No.A2197-31/35
LC87F1K64A
P34/UFILT
When using the internal PLL circuit to generate the 48MHz
clock for USB, it is necessary to connect a filter circuit as
shown in the left figure to the P34/UFILT pin.
After PLL is set, stabilization time of 20ms or longer must be
secured.
Rd
0kΩ
+
-
Cd
2.2μF
Figure 5 External Filter Circuit for the Internal USB-dedicated PLL Circuit
P33/AFILT
+ Cp
1μF
-
Rd
150Ω
+
-
Cd
4.7μF
To generate the master clock for the audio
interface using the internal PLL circuit, it is
necessary to connect a filter circuit as shown in
the left figure to the P33 pin.
Figure 6 External Filter Circuit for Audio Interface (Used with Internal PLL Circuit)
33Ω
UHAD+
/ UHBD+
5pF
15kΩ
It is necessary to adjust the circuit constant of the USB
port peripheral circuit for each mounting board.
33Ω
UHAD/ UHBD5pF
15kΩ
Figure 7 USB Port Peripheral Circuit
No.A2197-32/35
LC87F1K64A
VDD
RRES
RES
Note:
The external circuit differs depending on which of the power-on
reset and low-voltage reset functions is to be used. Refer to the
section on the reset functions in the user's manual.
CRES
Figure 8 Sample Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM transfer
period (SIO0, 4 only)
tSCK
tSCKL
tSCKH
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM transfer
period (SIO0, 4 only)
tSCKHA
tSCKL
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 9 Serial I/O Waveform
tPIL
tPIH
Figure 10 Pulse Input Timing Waveform
No.A2197-33/35
LC87F1K64A
P
SDA
S
Sr
P
tBUF
tHD;STA
tR
tF
tHD;STA
tsp
SCK
tLOW
tHIGH
tHD;DAT
tSU;DAT
tSU;STA
tSU;STO
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 11 I2C Timing
Voh
tr
D+
tr
90%
90%
Vcrs
10%
Vol
10%
D-
Figure 12 USB Data Signal Timing and Voltage Levels
(a)
POR release voltage
(PORRL)
(b)
VDD
Reset period
100μs or longer
Reset period
Reset unknown state
(POUKS)
RES
Figure 13 Sample Waveforms for POR-only (LVD deselected) Operation (Reset pin: Pull-up resistor PRES only)
• The POR function generates a reset only when the power is turned on starting at the VSS level.
• No stable reset will be generated if power is turned on again if the power level does not go down to the VSS level as
shown in (a). If such a case is anticipated, use the LVD function together with the POR function as explained below or
implement an external reset circuit.
• A reset is generated only when power level goes down to the VSS level as shown in (b) and power is turned on again
after this condition continues for 100μs or longer.
No.A2197-34/35
LC87F1K64A
LVD hysteresis width
(LVHYS)
LVD release voltage
(LVDET+LVHY)
VDD
Reset period
Reset period
Reset period
LVD detection voltage
(LVDET)
Reset unknown state
(LVUKS)
RES
Figure 14 Sample Waveforms for POR+LVD Operation (Reset pin: Pull-up Resistor PRES Only)
• A reset is generated both when power is turned on and when the power level lowers.
• A hysteresis width (LVHYS) is provided to prevent repetitions of reset release and entry cycles near the detection
level.
VDD
LVD reset voltage
LVD detection voltage
LVDET-0.5V
TLVDW
VSS
Figure 15 Minimum Low Voltage Detection Width (Sample Temporary Power Interruption/Fluctuation Waveform)
ORDERING INFORMATION
Device
LC87F1K64AUWA-2H
Package
SQFP48(7X7)
(Pb-Free / Halogen Free)
Shipping (Qty / Packing)
250 / Tray Foam
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PS No.A2197-35/35