a LC2MOS (8+4) Loading Dual 12-Bit DAC AD7937 FUNCTIONAL BLOCK DIAGRAM FEATURES Two 12-Bit DACs in One Package DAC Ladder Resistance Matching: 0.5% Surface-Mount Package 4-Quadrant Multiplication Low Gain Error (3 LSB max Over Temperature) Byte Loading Structure Fast Interface Timing APPLICATIONS Automatic Test Equipment Programmable Filters Audio Applications Synchro Applications Process Control VDD AD7937 DAC A MS INPUT REG DAC A LS INPUT REG 4 8 DAC A REGISTER UPD 12 IOUTA DAC A A1 AGNDA RFBA A0 VREFA CONTROL LOGIC VREFB CS RFBB GENERAL DESCRIPTION The AD7937 contains two 12-bit current output DACs on one monolithic chip. A separate reference input is provided for each DAC. The dual DAC saves valuable board space, and the monolithic construction ensures excellent thermal tracking. Both DACs are guaranteed 12-bit monotonic over the full temperature range. The AD7937 has a 2-byte (eight LSBs, four MSBs) loading structure. It is designed for right-justified data format. The control signals for register loading are A0, A1, CS, WR, and UPD. Data is loaded to the input registers when CS and WR are low. To transfer this data to the DAC registers, UPD must be taken low with WR. Added features on the AD7937 include an asynchronous CLR line which is very useful in calibration routines. When this is taken low, all registers are cleared. The double buffering of the data inputs allows simultaneous update of both DACs. Also, each DAC has a separate AGND line. This increases the device versatility; for instance, one DAC may be operated with AGND biased while the other is connected in the standard configuration. The AD7937 is manufactured using the Linear Compatible CMOS (LC2MOS) process. It is speed compatible with most microprocessors and accepts TTL, 74HC, and 5 V CMOS logic level inputs. WR IOUTB DAC B AGNDB 12 CLR DAC B REGISTER DB7–DB0 4 8 DAC B MS INPUT REG DAC B LS INPUT REG DGND PRODUCT HIGHLIGHTS 1. DAC-to-DAC Matching Since both DACs are fabricated on the same chip, precise matching and tracking is inherent. Many applications that are not practical using two discrete DACs are now possible. Typical matching: 0.5%. 2. Small Package Size The AD7937 is packaged in a small 24-lead SOIC. 3. Wide Power Supply Tolerance The device operates on a 5 V VDD, with ± 10% tolerance on this nominal figure. All specifications are guaranteed over this range. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 (VDD = 5 V 10%, VREFA = VREFB = 10 V; IOUTA = AGNDA = 0 V, IOUTB = AGNDB = 0 V. All MIN to TMAX unless otherwise noted.) AD7937–SPECIFICATIONS specifications T Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Temperature Coefficient2; ∆Gain/∆Temperature Output Leakage Current IOUTA IOUTB REFERENCE INPUT Input Resistance VREFA, VREFB Input Resistance Match DIGITAL INPUTS VIH (Input High Voltage) VIL (Input Low Voltage) IIN (Input Current) +25°C TMIN to TMAX CIN (Input Capacitance)2 POWER SUPPLY VDD IDD A Version B Version Unit Test Conditions/Comments 12 ±1 ±1 ±6 12 ± 1/2 ±1 ±3 Bits LSB max LSB max LSB max All grades guaranteed monotonic over temperature. Measured using RFBA, RFBB. Both DAC registers loaded with all 1s. ±5 ±5 ppm/°C max Typical value is 1 ppm/°C. 5 10 5 10 5 10 5 10 nA max nA max nA max nA max DAC A Register loaded with all 0s. 9 20 9 20 kΩ min kΩ max Typical Input Resistance = 14 kΩ. ±3 ±3 % max Typically ± 0.5%. 2.4 0.8 2.4 0.8 V min V max ±1 ± 10 10 ±1 ± 10 10 µA max µA max pF max 4.5/5.5 2 0.1 4.5/5.5 2 0.1 V min/V max mA max mA typ DAC B Register loaded with all 0s. VIN = VDD. AC PERFORMANCE CHARACTERISTICS These characteristics are included for Design Guidance only and are not subject to test. (VDD = 5 V; VREFA = VREFB = 10 V; IOUTA = AGNDA = 0 V, IOUTB = AGNDB = 0 V. Output Amplifiers are AD644 except where noted.) Parameter TA = 25C Unit Test Conditions/Comments Output Current Settling Time 1 µs max To 0.01% of full-scale range. IOUT load = 100 Ω, CEXT = 13 pF. DAC output measured from falling edge of WR. Typical Value of Settling Time is 0.6 µs. Digital-to-Analog Glitch lmpulse 2.5 nV-s typ Measured with VREFA = VREFB = 0 V. IOUTA, IOUTB load = 100 Ω, CEXT = 13 pF. DAC registers alternately loaded with all 0s and all 1s. AC Feedthrough VREFA to IOUTA VREFB to IOUTB –70 –70 dB max dB max VREFA, VREFB = 20 V p-p 10 kHz sine wave. DAC registers loaded with all 0s. Power Supply Rejection ∆Gain/∆VDD ± 0.01 % per % max ∆VDD = VDD max – VDD min. Output Capacitance COUTA COUTB COUTA COUTB 70 70 140 140 pF max pF max pF max pF max DAC A, DAC B loaded with all 0s. Channel-to-Channel Isolation VREFA to IOUTB VREFB to IOUTA –84 –84 dB typ dB typ VREFA = 20 V p-p 10 kHz sine wave, VREFB = 0 V. Both DACs loaded with all 1s. VREFB = 20 V p-p 10 kHz sine wave, VREFA = 0 V. Both DACs loaded with all 1s. Digital Crosstalk 2.5 nV-s typ Measured for a Code Transition of all 0s to all 1s. IOUTA, IOUTB load = 100 Ω, CEXT = 13 pF. Output Noise Voltage Density (10 Hz–100 kHz) 25 nV/√Hz typ Measured between RFBA and IOUTA or RFBB and IOUTB. Frequency of measurement is 10 Hz–100 kHz. Total Harmonic Distortion –82 dB typ VIN = 6 V rms, 1 kHz. Both DACs loaded with all 1s. DAC A, DAC B loaded with all 1s. NOTES 1 Temperature range as follows: A, B Versions: –40°C to +85°C. 2 Sample tested at 25°C to ensure compliance. Specifications subject to change without notice. –2– REV. 0 AD7937 TIMING CHARACTERISTICS (VDD = 5 V 10%, VREFA = VREFB = 10 V; IOUTA = AGNDA = 0 V, IOUTB = AGNDB = 0 V.) Parameter Limit at TA = 25C Limit at TA = –40C to +85C Unit Test Conditions/Comments t1 t2 t3 t4 t5 t6 t7 t8 10 10 20 30 0 0 115 90 10 10 40 30 0 0 125 100 ns min ns min ns min ns min ns min ns min ns min ns min Address Valid to Write Setup Time Address Valid to Write Hold Time Data Setup Time Data Hold Time Chip Select or Update to Write Setup Time Chip Select or Update to Write Hold Time Write Pulsewidth Clear Pulsewidth Specifications subject to change without notice. t2 t1 ABSOLUTE MAXIMUM RATINGS* 5V A0–A1 (TA = 25°C unless otherwise noted) 0V t3 VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V VREFA, VREFB to AGNDA, AGNDB . . . . . . . . . . . . . . . . ± 25 V VRFBA, VRFBB to AGNDA, AGNDB . . . . . . . . . . . . . . . . ± 25 V Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD +0.3 V IOUTA, IOUTB to DGND . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V AGNDA, AGNDB to DGND . . . . . . . . . –0.3 V, VDD +0.3 V SOIC Package θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 72°C/W Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C IR Ref Low Peak Temperature . . . . . . . . . . . . . . . . . . 220°C Operating Temperature Range Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . –65°C to +150°C t4 5V DATA 0V t5 t6 5V CS, UPD 0V t7 5V WR 0V t8 CLR 5V 0V NOTES 1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF +5V. t r = t f = 20ns. VIH + VIL 2. TIMING MEASUREMENT REFERENCE LEVELS IS 2 Figure 1. Timing Diagram *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Range Relative Accuracy Gain Error Package Description Option AD7937AR AD7937BR –40°C to +85°C –40°C to +85°C ± 1 LSB ± 1/2 LSB ± 6 LSB ± 3 LSB Small Outline Small Outline R-24 R-24 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7937 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– WARNING! ESD SENSITIVE DEVICE AD7937 PIN FUNCTION DESCRIPTIONS R R VREFA Pin Mnemonic Description 1 2 3 4 5 6–11 13, 14 12 15 16 17 AGNDA IOUTA RFBA VREFA CS DB0–DB7 Analog Ground for DAC A. Current output terminal of DAC A. Feedback resistor for DAC A. Reference input to DAC A. Chip Select Input Active low. Eight data inputs, DB0–DB7. DGND A0 A1 CLR 18 19 WR UPD 20 VDD 21 22 23 24 VREFB RFBB IOUTB AGNDB Digital Ground. Address Line 0. Address Line 1. Clear Input. Active low. Clears all registers. Write Input. Active low. Updates DAC Registers from inputs registers. Power supply input. Nominally 5 V to 15 V, with ± 10% tolerance. Reference input to DAC B. Feedback resistor for DAC B. Current output terminal of DAC B. Analog Ground for DAC B. 24 AGNDB IOUTA 2 23 IOUTB RFBA 3 22 RFBB VREFA 4 21 VREFB 20 VDD 19 UPD CS 5 DB0 6 DB1 7 DB2 AD7937 8 17 CLR 16 A1 DB4 10 15 A0 DB5 11 14 DB7 DGND 12 13 DB6 2R S11 S10 S0 2R RFBA IOUTA AGNDA Figure 2. Simplified Circuit Diagram for DAC A EQUIVALENT CIRCUIT ANALYSIS Figure 3 shows the equivalent circuit for one of the D/A converters (DAC A) in the AD7937. A similar equivalent circuit can be drawn for DAC B. R RFBA IOUTA VREFA D.VREF R R RO ILKG COUT AGNDA Figure 3. Equivalent Analog Circuit for DAC A COUT is the output capacitance due to the N-channel switches and varies from about 50 pF to 100 pF with digital input code. The current source ILKG is composed of surface and junction leakages and approximately doubles every 10°C. RO is the equivalent output resistance of the device which varies with input code. DIGITAL CIRCUIT INFORMATION The digital inputs are designed to be both TTL and 5 V CMOS compatible. All logic inputs are static protected MOS gates with typical input currents of less than 1 nA. Table I. AD7937 Truth Table CLR UPD CS WR A1 A0 Function TOP VIEW (Not to Scale) 18 WR DB3 9 2R R PIN CONFIGURATION SOIC AGNDA 1 2R CIRCUIT INFORMATION – D/A SECTION The AD7937 contains two identical 12-bit multiplying D/A converters. Each DAC consists of a highly stable R-2R ladder and 12 N-channel current steering switches. Figure 2 shows a simplified D/A circuit for DAC A. In the R-2R ladder, binary weighted currents are steered between IOUTA and AGNDA. The current flowing in each ladder leg is constant, irrespective of switch state. The feedback resistor RFBA is used with an op amp (see Figures 4 and 5) to convert the current flowing in IOUTA to a voltage output. 1 1 0 1 1 1 X 1 1 X X 0 X 1 X 0 X X X 0 X X X 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 0 X X 1 0 0 0 X X No Data Transfer No Data Transfer All Registers Cleared DAC A LS Input Register Loaded with DB7–DB0 (LSB) DAC A MS Input Register Loaded with DB3 (MSB)–DB0 DAC B LS Input Register Loaded with DB7–DB0 (LSB) DAC B MS Input Register Loaded with DB3 (MSB)–DB0 DAC A, DAC B Registers Updated Simultaneously from Input Registers DAC A, DAC B Registers are Transparent NOTE: X = Don’t care –4– REV. 0 AD7937 UNIPOLAR BINARY OPERATION (2-QUADRANT MULTIPLICATION) BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) Figure 4 shows the circuit diagram for unipolar binary operation. With an ac input, the circuit performs 2-quadrant multiplication. The code table for Figure 4 is given in Table II. The recommended circuit diagram for bipolar operation is shown in Figure 5. Offset binary coding is used. Operational amplifiers A1 and A2 can be in a single package (AD644, AD712) or separate packages (AD544, AD711, AD OP27). Capacitors C1 and C2 provide phase compensation to help prevent overshoot and ringing when high-speed op amps are used. For zero offset adjustment, the appropriate DAC register is loaded with all 0s and amplifier offset adjusted so that VOUTA or VOUTB is 0 V. Full-scale trimming is accomplished by loading the DAC register with all 1s and adjusting R1 (R3) so that VOUTA (VOUTB) = –VIN (4095/4096). For high temperature operation, resistors and potentiometers should have a low Temperature Coefficient. In many applications, because of the excellent Gain T.C. and Gain Error specifications of the AD7937, Gain Error trimming is not necessary. In fixed reference applications, full scale can also be adjusted by omitting R1, R2, R3, R4 and trimming the reference voltage magnitude. With the appropriate DAC register loaded to 1000 0000 0000, adjust R1 (R3) so that VOUTA (VOUTB) = 0 V. Alternatively, R1, R2 (R3, R4) may be omitted and the ratios of R6, R7 (R9, R10) varied for VOUTA (VOUTB) = 0 V. Full-scale trimming can be accomplished by adjusting the amplitude of VIN or by varying the value of R5 (R8). If R1, R2 (R3, R4) are not used, then resistors R5, R6, R7 (R8, R9, R10) should be ratio matched to 0.01% to ensure gain error performance to the data sheet specification. When operating over a wide temperature range, it is important that the resistors be of the same type so that their temperature coefficients match. The code table for Figure 5 is given in Table III. R2 47 C1 33pF IOUTA RFBB DAC B DGND VOUTB 1/2 AD712 DGND R3 100 C2 33pF 1/2 AD712 A3 AGNDB R9 10k A2 AGNDB 1/2 AD712 R4 RFBB 47 IOUTB DB0 R10 20k R3 100 VINB 1/2 AD712 A1 AGNDA C2 33pF IOUTB DAC B VOUTA 1/2 AD712 R4 47 DAC A AD7937* DATA INPUT A1 AGNDA AD7937* DB0 DB7 A2 C1 33pF IOUTA RFBA DATA INPUT VOUTA R7 10k R2 RFBA 47 R1 100 DB7 R6 20k R1 100 VDD VINA DAC A R5 20k VDD VINA *CONTROL CIRCUITRY R8 20k VOUTB A4 1/2 AD712 OMITTED FOR CLARITY *CONTROL CIRCUITRY Figure 5. Bipolar Operation (Offset Binary Coding) OMITTED FOR CLARITY VINB Table III. Bipolar Code Table for Offset Binary Circuit of Figure 5 Figure 4. Unipolar Binary Operation Table II. Unipolar Binary Code Table for Circuit of Figure 4 Binary Number in DAC Register MSB LSB 1111 1111 1111 Binary Number in DAC Register MSB LSB Analog Output, VOUTA or VOUTB 4095 −V IN 4096 Analog Output, VOUTA or VOUTB 1111 1111 1111 2047 +V IN 2048 1000 0000 0001 1 +V IN 2048 1000 0000 0000 0V 1000 0000 0000 2048 −V IN = − 12 V IN 4096 0111 1111 1111 0000 0000 0001 1 −V IN 4096 1 −V IN 2048 0000 0000 0000 0V 0000 0000 0000 2048 −V IN = −V IN 2048 REV. 0 –5– AD7937 SEPARATE AGND PINS PROGRAMMABLE OSCILLATOR The DACs in the AD7937 have separate AGND lines taken to pins AGNDA and AGNDB on the package. This increases the applications versatility of the part. Figure 6 is an example of this. DAC A is connected in standard fashion as a programmable attenuator. AGNDA is at ground potential. DAC B is operating with AGND B biased to 5 V by the AD584. This gives an output range of 5 V to 10 V. Figure 7 shows a conventional state variable oscillator in which the AD7937 controls the programmable integrators. The frequency of oscillation is given by: f= RFBA f= IOUTA VREFA DAC A AGNDA A1 VOUTA Since REQ = DB7 DATA INPUT AD7937* DB0 RFBB IOUTB VREFB DAC B AGNDB DGND VOUTB = 5V TO 10V 5V 1 REQ1 × REQ2 (N / 2n )2 RLAD1 × RLAD2 1 1 × 2π C = 1 D × 2π C = 1 D × 2 π C × RLAD 1 RLAD1 × RLAD2 N D= n 2 VDD AD584 SIGNAL GROUND 1 1 × 2π C 2n × RLAD , (RLAD = DAC ladder resistance). N f= A2 R6 × 1 R5 C1× C2 × REQ1 × REQ2 where REQ1 and REQ2 are the equivalent resistances of the DACs. The same digital code is loaded into both DACs. If C1 = C2 and R5 = R6, the expression reduces to VDD = 5V 20V p–p 1 2π *CONTROL CIRCUITRY OMITTED FOR CLARITY Figure 6. DACs Used in Different Modes m where m is the DAC ladder resistance mismatch ratio, typically 1.005. With the values shown in Figure 7, the output frequency varies from 0 Hz to 1.38 kHz. The amplitude of the output signal at the A3 output is 10 V peak-to-peak and is constant over the entire frequency span. FREQUENCY SELECT CODE R5 10k R4 200k R6 10k C1 10,000pF C2 10,000pF 1/2 AD7937 A1 AD711 VREFA IOUTA 1/2 AD7937 A2 VREFB AGNDA DAC A 1/2 AD712 IOUTB A3 AGNDB DAC B VOUT 1/2 AD712 5.1V NOTE DAC CONTROL INPUTS OMITTED FOR CLARITY 10k Figure 7. Programmable State Variable Oscillator –6– REV. 0 AD7937 APPLICATION HINTS MICROPROCESSOR INTERFACING Output Offset: CMOS D/A converters in circuits such as Figures 4 and 5 exhibit a code-dependent output resistance which in turn can cause a code-dependent error voltage at the output of the amplifier. The maximum amplitude of this error, which adds to the D/A converter nonlinearity, depends on VOS, where VOS is the amplifier input offset voltage. To maintain specified operation, it is recommended that VOS be no greater than (25 ⫻ 10–6) (VREF) over the temperature range of operation. Suitable op amps are the AD711C and its dual version, the AD712C. These op amps have a wide bandwidth and high slew rate and are recommended for wide bandwidth ac applications. AD711/AD712 settling time to 0.01% is typically 3 µs. The byte loading structure of the AD7937 makes it very easy to interface the device to any 8-bit microprocessor system. Figure 8 shows an example 8-bit interface between the AD7937 and a generic 8-bit microcontroller/DSP processor. Pins D7 to D0 of the processor are connected to pins D7 to D0 of the AD7937. When writing to the DACs, the lower 8 bits must be written first, followed by the upper four bits. The upper four bits should be output on data lines D0 to D3. CONTROLLER/ DSP PROCESSOR * Temperature Coefficients: The gain temperature coefficient of the AD7937 has a maximum value of 5 ppm/°C and typical value of 1 ppm/°C. This corresponds to worst case gain shifts of 2 LSBs and 0.4 LSBs respectively over a 100°C temperature range. When trim resistors R1 (R3) and R2 (R4) are used to adjust full scale range as in Figure 4, the temperature coefficient of R1 (R3) and R2 (R4) should also be taken into account. AD7937* CLR D7 D7 D0 D0 DATA BUS UPPER BITS OF ADDRESS BUS High Frequency Considerations: AD7937 output capacitance works in conjunction with the amplifier feedback resistance to add a pole to the open-loop response. This can cause ringing or oscillation. Stability can be restored by adding a phase compensation capacitor in parallel with the feedback resistor. This is shown as C1 and C2 in Figures 4 and 5. ADDRESS DECODE CS UPD A0 A0 A1 A1 R/W WR *ADDITIONAL PINS OMITTED FOR CLARITY Figure 8. AD7937 8-Bit Interface Feedthrough: The dynamic performance of the AD7937 depends upon the gain and phase stability of the output amplifier, together with the optimum choice of PC board layout and decoupling components. REV. 0 FROM SYSTEM RESET –7– AD7937 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Small Outline SOIC (R-24) 24 C01010–2.5–7/00 (rev. 0) 0.6141 (15.60) 0.5985 (15.20) 13 0.2992 (7.60) 0.2914 (7.40) PIN 1 0.0118 (0.30) 0.0500 0.0040 (0.10) (1.27) BSC 12 0.4193 (10.65) 0.3937 (10.00) 0.1043 (2.65) 0.0926 (2.35) 8 0 0.0192 (0.49) SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23) 0.0291 (0.74) 45 0.0098 (0.25) 0.0500 (1.27) 0.0157 (0.40) PRINTED IN U.S.A. 1 –8– REV. 0