AD AD8220BRMZ

JFET Input Instrumentation Amplifier with
Rail-to-Rail Output in MSOP Package
AD8220
FEATURES
Medical instrumentation
Precision data acquisition
Transducer interface
GENERAL DESCRIPTION
The AD8220 is the first single-supply JFET input
instrumentation amplifier available in an MSOP package.
Designed to meet the needs of high performance, portable
instrumentation, the AD8220 has a minimum common-mode
rejection ratio (CMRR) of 86 dB at dc and a minimum CMRR
of 80 dB at 5 kHz for G = 1. Maximum input bias current is 10
pA and typically remains below 300 pA over the entire
industrial temperature range. Despite the JFET inputs, the
AD8220 typically has a noise corner of only 10 Hz.
With the proliferation of mixed-signal processing, the number of
power supplies required in each system has grown. The AD8220 is
designed to alleviate this problem. The AD8220 can operate on a
±18 V dual supply, as well as on a single +5 V supply. Its rail-to-rail
output stage maximizes dynamic range on the low voltage supplies
common in portable applications. Its ability to run on a single 5 V
supply eliminates the need to use higher voltage, dual supplies. The
AD8220 draws a maximum of 750 μA of quiescent current, making
it ideal for battery-powered devices.
AD8220
1
8
+VS
RG
2
7
VOUT
RG
3
6
REF
+IN
4
5
–VS
03579-005
–IN
TOP VIEW
(Not to Scale)
Figure 1.
10n
1n
IBIAS
100p
10p
IOS
1p
0.1p
–50
03579-059
APPLICATIONS
PIN CONFIGURATION
INPUT BIAS CURRENT (A)
Low input currents
10 pA maximum input bias current (B grade)
0.6 pA maximum input offset current (B grade)
High CMRR
100 dB CMRR (minimum), G = 10 (B grade)
80 dB CMRR (minimum) to 5 kHz, G = 1 (B grade)
Excellent ac specifications and low power
1.5 MHz bandwidth (G = 1)
14 nV/√Hz input noise (1 kHz)
Slew rate 2 V/μs
750 μA quiescent supply current (maximum)
Versatile
MSOP package
Rail-to-rail output
Input voltage range to below negative supply rail
4 kV ESD protection
4.5 V to 36 V single supply
±2.25 V to ±18 V dual supply
Gain set with single resistor (G = 1 to 1000)
–25
0
25
50
75
100
125
150
TEMPERATURE (°C)
Figure 2. Input Bias Current and Offset Current Temperature
Gain is set from 1 to 1000 with a single resistor. Increasing the
gain increases the common-mode rejection. Measurements that
need higher CMRR when reading small signals benefit when
the AD8220 is set for large gains.
A reference pin allows the user to offset the output voltage. This
feature is useful when interfacing with analog-to-digital
converters.
The AD8220 is available in an MSOP that takes roughly half the
board area of an SOIC. Performance is specified over the
industrial temperature range of −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD8220
TABLE OF CONTENTS
Features .............................................................................................. 1
Reference Terminal .................................................................... 21
Applications....................................................................................... 1
Power Supply Regulation and Bypassing ................................ 21
General Description ......................................................................... 1
Input Bias Current Return Path ............................................... 21
Pin Configuration............................................................................. 1
Input Protection ......................................................................... 21
Revision History ............................................................................... 2
RF Interference ........................................................................... 22
Specifications..................................................................................... 3
Common-Mode Input Voltage Range ..................................... 22
Absolute Maximum Ratings............................................................ 8
Driving an Analog-to-Digital Converter ................................ 22
ESD Caution.................................................................................. 8
Applications..................................................................................... 23
Pin Configuration and Function Descriptions............................. 9
AC-Coupled Instrumentation Amplifier ................................ 23
Typical Performance Characteristics ........................................... 10
Differential Output .................................................................... 23
Theory of Operation ...................................................................... 19
Electrocardiogram Signal Conditioning ................................. 25
Gain Selection ............................................................................. 20
Outline Dimensions ....................................................................... 26
Layout........................................................................................... 20
Ordering Guide .......................................................................... 26
REVISION HISTORY
4/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD8220
SPECIFICATIONS
VS+ = +15 V, VS− = −15 V, VREF = 0 V, TA = +25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
Table 1.
Parameter
Test Conditions
COMMON-MODE REJECTION
RATIO (CMRR)
CMRR DC to 60 Hz with 1 kΩ
Source Imbalance
G=1
VCM = ±10 V
Min
A Grade
Typ
Max
Min
B Grade
Typ
Max
Unit
78
86
dB
G = 10
94
100
dB
G = 100
94
100
dB
94
100
dB
G=1
74
80
dB
G = 10
84
90
dB
G = 100
84
90
dB
84
90
dB
G = 1000
CMRR at 5 kHz
VCM = ±10 V
G = 1000
NOISE
RTI noise = √(eni2 + (eno/G)2)
Voltage Noise, 1 kHz
Input Voltage Noise, eni
VIN+, VIN− = 0 V
14
14
17
nV√Hz
Output Voltage Noise, eno
VIN+, VIN− = 0 V
90
90
100
nV√Hz
G=1
5
5
μV p-p
G = 1000
0.8
0.8
μV p-p
1
1
fA/√Hz
RTI, 0.1 Hz to 10 Hz
Current Noise
f = 1 kHz
VOLTAGE OFFSET
Input Offset, VOSI
250
125
10
5
μV/°C
750
500
μV
10
5
μV/°C
G=1
86
86
dB
G = 10
96
100
dB
G = 100
96
100
dB
G = 1000
96
100
dB
Average TC
T = −40°C to +85°C
Output Offset, VOSO
Average TC
Offset RTI vs. Supply (PSR)
T = −40°C to +85°C
μV
INPUT CURRENT
Input Bias Current
25
10
T = −40°C to +85°C
300
Input Offset Current
Over Temperature
DYNAMIC RESPONSE
T = −40°C to +85°C
5
5
pA
pA
1500
1500
kHz
G = 10
800
800
kHz
G = 100
120
120
kHz
G = 1000
14
14
kHz
Small Signal Bandwidth –
3 dB
G=1
300
pA
Over Temperature
2
Rev. 0 | Page 3 of 28
pA
0.6
AD8220
Parameter
Settling Time 0.01%
Test Conditions
Min
A Grade
Typ
Max
Min
B Grade
Typ
Max
Unit
10 V step
G=1
5
5
G = 10
4.3
4.3
μs
G = 100
8.1
8.1
μs
58
58
μs
G=1
6
6
μs
G = 10
4.6
4.6
μs
G = 100
9.6
9.6
μs
G = 1000
74
74
μs
G = 1000
Settling Time 0.001%
μs
10 V step
Slew Rate
G = 1 to 100
GAIN
2
Gain Range
Gain Error
2
V/μs
G = 1 + (49.4 kΩ/RG)
1
1000
1
1000
V/V
VOUT = ±10 V
G=1
0.06
0.04
%
G = 10
0.3
0.2
%
G = 100
0.3
0.2
%
G = 1000
0.3
0.2
%
Gain Nonlinearity
VOUT = −10 V to +10 V
G=1
RL = 10 kΩ
10
15
10
15
ppm
G = 10
RL = 10 kΩ
5
10
5
10
ppm
G = 100
RL = 10 kΩ
30
60
30
60
ppm
G = 1000
RL = 10 kΩ
400
500
400
500
ppm
G=1
RL = 2 kΩ
10
15
10
15
ppm
G = 10
RL = 2 kΩ
10
15
10
15
ppm
G = 100
RL = 2 kΩ
50
75
50
75
ppm
3
10
2
5
ppm/°C
−50
ppm/°C
Gain vs. Temperature
G=1
G > 10
−50
INPUT
Impedance (Pin to Ground)1
Input Operating Voltage
Range2
Over Temperature
104||5
104||5
GΩ||pF
VS = ±2.25 V to ±18 V for
dual supplies
T = −40°C to +85°C
−VS − 0.1
+VS − 2
−VS − 0.1
+VS − 2
V
−VS − 0.1
+VS − 2.1
−VS − 0.1
+VS − 2.1
V
RL = 2 kΩ
−14.3
+14.3
−14.3
+14.3
V
T = −40°C to +85°C
−14.3
+14.1
−14.3
+14.1
V
RL = 10 kΩ
−14.7
+14.7
−14.7
+14.7
V
T = −40°C to +85°C
−14.6
+14.6
−14.6
+14.6
V
OUTPUT
Output Swing
Over Temperature
Output Swing
Over Temperature
Short-Circuit Current
15
15
mA
REFERENCE INPUT
RIN
IIN
Voltage Range
Gain to Output
40
VIN+, VIN− = 0 V
40
70
−VS
+VS
1 ± 0.0001
Rev. 0 | Page 4 of 28
kΩ
70
−VS
+VS
1 ± 0.0001
μA
V
V/V
AD8220
Parameter
Test Conditions
Min
A Grade
Typ
Max
Min
±18
±2.253
B Grade
Typ
Max
Unit
POWER SUPPLY
±2.253
Operating Range
Quiescent Current
Over Temperature
T = −40°C to +85°C
±18
V
750
750
μA
850
850
μA
TEMPERATURE RANGE
For Specified Performance
−40
+85
−40
+85
°C
Operational4
−40
+125
−40
+125
°C
1
Differential and common-mode input impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2.
The AD8220 can operate up to a diode drop below the negative supply but the bias current increases sharply. The input voltage range reflects the maximum
allowable voltage where the input bias current is within the specification.
3
At this supply voltage, ensure that the input common-mode voltage is within the input voltage range specification.
4
The AD8220 is characterized from −40°C to +125°C. See the Typical Performance Characteristics section for expected operation in this temperature range.
2
VS + = 5 V, VS− = 0 V, VREF = 2.5 V, TA = +25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
Table 2.
Parameter
COMMON-MODE REJECTION
RATIO (CMRR)
CMRR DC to 60 Hz with
1 kΩ Source Imbalance
G=1
G = 10
G = 100
G = 1000
CMRR at 5 kHz
G=1
G = 10
G = 100
G = 1000
NOISE
Voltage Noise, 1 kHz
Input Voltage Noise, eni
Output Voltage Noise, eno
RTI, 0.1 Hz to 10 Hz
G=1
G = 1000
Current Noise
VOLTAGE OFFSET
Input Offset, VOSI
Average TC
Output Offset, VOSO
Average TC
Test Conditions
Min
A Grade
Typ
Max
Min
B Grade
Typ
Max
Unit
VCM = 0 to 2.5 V
78
94
94
94
86
100
100
100
dB
dB
dB
dB
74
84
84
84
80
90
90
90
dB
dB
dB
dB
RTI noise = √(eni2 +
(eno/G)2)
VIN+, VIN− = 0 V, VREF = 0 V
VIN+, VIN− = 0 V, VREF = 0 V
14
90
14
90
f = 1 kHz
5
0.8
1
5
0.8
1
17
100
nV√Hz
nV√Hz
μV p-p
μV p-p
fA/√Hz
T = −40°C to +85°C
300
10
800
200
5
600
μV
μV/°C
μV
T = −40°C to +85°C
10
5
μV/°C
86
96
96
96
86
100
100
100
dB
dB
dB
dB
Offset RTI vs. Supply (PSR)
G=1
G = 10
G = 100
G = 1000
Rev. 0 | Page 5 of 28
AD8220
Parameter
Test Conditions
Min
A Grade
Typ
Max
Min
B Grade
Typ
Max
Unit
10
pA
pA
0.6
INPUT CURRENT
Input Bias Current
Over Temperature
Input Offset Current
Over Temperature
DYNAMIC RESPONSE
Small Signal Bandwidth –
3 dB
G=1
G = 10
G = 100
G = 1000
Settling Time 0.01%
G=1
G = 10
G = 100
G = 1000
Settling Time 0.001%
G=1
G = 10
G = 100
G = 1000
Slew Rate
G = 1 to 100
GAIN
Gain Range
Gain Error
G=1
G = 10
G = 100
G = 1000
Nonlinearity
G=1
G = 10
G = 100
G = 1000
G=1
G = 10
G = 100
Gain vs. Temperature
G=1
25
T = −40°C to +85°C
300
T = −40°C to +85°C
5
5
pA
pA
1500
800
120
14
1500
800
120
14
kHz
kHz
kHz
kHz
3 V step
4 V step
4 V step
2.5
2.5
7.5
2.5
2.5
7.5
μs
μs
μs
4 V step
30
30
μs
3 V step
4 V step
4 V step
4 V step
3.5
3.5
8.5
37
3.5
3.5
8.5
37
μs
μs
μs
μs
2
2
2
V/μs
G = 1 + (49.4 kΩ/RG)
1
1000
1
1000
V/V
0.04
0.2
0.2
0.2
%
%
%
%
50
50
75
750
50
50
75
ppm
ppm
ppm
ppm
ppm
ppm
ppm
VOUT = 0.3 V to 2.9 V for
G=1
VOUT = 0.3 V to 3.8 V for
G>1
0.06
0.3
0.3
0.3
VOUT = 0.3 V to 2.9 V for
G=1
VOUT = 0.3 V to 3.8 V for
G>1
RL = 10 kΩ
RL = 10 kΩ
RL = 10 kΩ
RL = 10 kΩ
RL = 2 kΩ
RL = 2 kΩ
RL = 2 kΩ
35
35
50
650
35
35
50
50
50
75
750
50
50
75
35
35
50
650
35
35
50
3
10
2
G > 10
INPUT
Impedance (Pin to Ground)1
Input Voltage Range2
Over Temperature
300
−50
104||6
T = −40°C to +85°C
−0.1
−0.1
Rev. 0 | Page 6 of 28
5
ppm/°C
−50
ppm/°C
+VS − 2
+VS − 2.1
GΩ||pF
V
V
104||6
+VS − 2
+VS − 2.1
−0.1
−0.1
AD8220
Parameter
Test Conditions
Min
RL = 2 kΩ
T = −40°C to +85°C
RL = 10 kΩ
T = −40°C to +85°C
0.25
0.3
0.15
0.2
A Grade
Typ
Max
Min
4.75
4.70
4.85
4.80
0.25
0.3
0.15
0.2
B Grade
Typ
Max
Unit
4.75
4.70
4.85
4.80
V
V
V
V
mA
OUTPUT
Output Swing
Over Temperature
Output Swing
Over Temperature
Short-Circuit Current
15
REFERENCE INPUT
RIN
IIN
Voltage Range
40
VIN+, VIN− = 0 V
−VS
+4.5
1 ± 0.0001
+36
+4.5
750
850
T = −40°C to +85°C
−40
−40
+85
+125
1
70
+VS
−VS
1 ± 0.0001
POWER SUPPLY
Operating Range
TEMPERATURE RANGE
For Specified Performance
Operational3
40
70
+VS
Gain to Output
Quiescent Current
Over Temperature
15
−40
−40
V/V
+36
V
750
850
μA
μA
+85
+125
°C
°C
Differential and common-mode impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2.
The AD8220 can operate up to a diode drop below the negative supply but the bias current increases sharply. The input voltage range reflects the maximum
allowable voltage where the input bias current is within the specification.
3
The AD8220 is characterized from −40°C to +125°C. See the Typical Performance Characteristics section for expected operation in that temperature range.
2
Rev. 0 | Page 7 of 28
kΩ
μA
V
AD8220
ABSOLUTE MAXIMUM RATINGS
1
2
Rating
±18 V
See Figure 3
Indefinite1
±Vs
±Vs
−65°C to +125°C
−40°C to +125°C
300°C
140°C
135°C/W
140°C
4 kV
1 kV
0.4 kV
Assumes the load is referenced to mid-supply.
Temperature for specified performance is −40°C to +85°C. For performance
to +125°C, see the Typical Performance Characteristics section.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the MSOP on a 4-layer
JEDEC standard board. θJA values are approximations.
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
–40
03579-045
Parameter
Supply Voltage
Power Dissipation
Output Short Circuit Current
Input Voltage (Common Mode)
Differential Input Voltage
Storage Temperature
Operating Temperature Range2
Lead Temperature Range (Soldering 10 sec)
Junction Temperature
θJA (4-layer JEDEC Standard Board)
Package Glass Transition Temperature
ESD (Human Body Model)
ESD (Charge Device Model)
ESD (Machine Model)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION (W)
Table 3.
–20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 8 of 28
100
120
AD8220
AD8220
–IN
1
8
+VS
RG
2
7
VOUT
RG
3
6
REF
+IN
4
5
–VS
TOP VIEW
(Not to Scale)
03579-005
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2, 3
4
5
6
7
8
Mnemonic
−IN
RG
+IN
−VS
REF
VOUT
+VS
Description
Negative Input Terminal (true differential input).
Gain Setting Terminals (place resistor across the RG pins).
Positive Input Terminal (true differential input).
Negative Power Supply Terminal.
Reference Voltage Terminal (drive this terminal with a low impedance voltage source to level shift the output.)
Output Terminal.
Positive Power Supply Terminal.
Rev. 0 | Page 9 of 28
AD8220
TYPICAL PERFORMANCE CHARACTERISTICS
1600
1200
1400
1000
NUMBER OF UNITS
NUMBER OF UNITS
1200
800
600
400
1000
800
600
400
–40
–20
0
20
200
03579-063
0
03579-060
200
0
40
0
1
2
CMRR (µV/V)
3
4
5
IBIAS (pA)
Figure 5. Typical Distribution of CMRR (G = 1)
Figure 8. Typical Distribution of Input Bias Current
1200
1000
800
NUMBER OF UNITS
600
400
200
600
400
200
03579-061
0
800
–200
–100
0
100
0
200
03579-064
NUMBER OF UNITS
1000
–0.2
–0.1
0
0.1
0.2
IOS (pA)
VOSI 15VS (µV)
Figure 6. Typical Distribution of Input Offset Voltage
Figure 9. Typical Distribution of Input Offset Current
1000
1000
100
(nV/ Hz)
GAIN = 1
600
GAIN = 10
GAIN = 100/GAIN = 1000
10
400
GAIN = 1000 BANDWIDTH ROLL-OFF
0
–1000
–500
0
500
1000
1
03579-042
200
03579-062
NUMBER OF UNITS
GAIN = 100 BANDWIDTH ROLL-OFF
800
1
10
100
1k
10k
FREQUENCY (Hz)
VOSO 15VS (µV)
Figure 10. Voltage Spectral Density vs. Frequency
Figure 7. Typical Distribution of Output Offset Voltage
Rev. 0 | Page 10 of 28
100k
AD8220
XX
150
GAIN = 1000
130
PSRR (dB)
XXX (X)
BANDWIDTH
LIMITED
GAIN = 100
110
GAIN = 10
90
GAIN = 1
70
50
10
XX
03579-035
1s/DIV
XX
XX
30
03579-024
5µV/DIV
10
1
100
XXX (X)
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)
Figure 14. Positive PSRR vs. Frequency, RTI
XX
150
130
XXX (X)
PSRR (dB)
110
GAIN = 1000
90
GAIN = 1
70
GAIN = 10
50
GAIN = 100
1s/DIV
10
XX
03579-040
03579-025
1µV/DIV
XX
XX
30
10
1
100
XXX (X)
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)
Figure 15. Negative PSRR vs. Frequency, RTI
8
0.3
INPUT BIAS CURRENT (pA)
5
4
3
2
0.1
7
0
5
–15.1V
1
0
0.1
1
10
100
1k
TIME (s)
–0.1
–0.2
3
–5.1V
INPUT BIAS
CURRENT ±15
INPUT BIAS
CURRENT ±5
1
03579-009
∆ VOSI (µV)
6
0.2
INPUT OFFSET
CURRENT ±5
–0.4
–1
–16
–12
–8
–4
0
4
8
12
COMMON-MODE VOLTAGE (V)
Figure 13. Change in Input Offset Voltage vs. Warm Up Time
Figure 16. Input Current vs. Common-Mode Voltage
Rev. 0 | Page 11 of 28
–0.3
16
–0.5
03579-050
7
INPUT OFFSET
CURRENT ±15
INPUT OFFSET CURRENT (pA)
9
AD8220
160
140
IBIAS
120
100p
10p
IOS
1p
0
25
50
75
100
125
BANDWIDTH
LIMITED
GAIN = 1
GAIN = 10
60
03579-059
–25
GAIN = 100
100
80
0.1p
–50
GAIN = 1000
40
150
03579-051
1n
CMRR (dB)
INPUT BIAS CURRENT (A)
10n
10
1
100
TEMPERATURE (°C)
1k
10k
100k
FREQUENCY (Hz)
Figure 17. Input Bias Current and Offset Current Temperature,
VS = ±15 V, VREF = 0 V
Figure 20. CMRR vs. Frequency, 1 kΩ Source Imbalance
10
8
10n
6
4
IBIAS
∆ CMRR (µV/V)
100p
10p
IOS
1p
2
0
–2
–4
–6
03579-065
0.1p
–50
–25
0
25
50
75
100
125
03579-034
CURRENT (A)
1n
–8
–10
–50
150
–30
–10
TEMPERATURE (°C)
70
90
110
130
70
60
GAIN = 1000
GAIN = 1000
50
40
GAIN = 100
GAIN = 100
GAIN = 10
GAIN (dB)
30
BANDWIDTH
LIMITED
100
GAIN = 1
20
GAIN = 10
10
0
80
GAIN = 1
–10
40
10
100
1k
10k
100k
FREQUENCY (Hz)
03579-022
–20
60
03579-023
CMRR (dB)
50
Figure 21. Change in CMRR vs. Temperature, G = 1
160
120
30
TEMPERATURE (°C)
Figure 18. Input Bias Current and Offset Current vs. Temperature,
VS = +5 V, VREF = 2.5 V
140
10
–30
–40
100
1k
10k
100k
FREQUENCY (Hz)
Figure 19. CMRR vs. Frequency
Figure 22. Gain vs. Frequency
Rev. 0 | Page 12 of 28
1M
10M
VS = ±15V
–10
–8
–6
RLOAD = 10kΩ
–4
–2
0
2
4
6
8
03579-029
XXX
RLOAD = 10kΩ
NONLINEARITY (500ppm/DIV)
RLOAD = 2kΩ
RLOAD = 2kΩ
03579-026
XXX
NONLINEARITY (5ppm/DIV)
AD8220
VS = ±15V
10
–10
–8
–6
–4
VIN (V)
–2
0
2
4
6
8
10
OUTPUT VOLTAGE (V)
Figure 23. Gain Nonlinearity, G = 1
Figure 26. Gain Nonlinearity, G = 1000
RLOAD = 10kΩ
VS = ±15V
–10
–8
–6
–4
–2
0
2
4
6
8
+13V
12
6
0
–14.8V, +5.5V
+14.9V, +5.5V
+3V
–4.8V, +0.6V
+4.95V, +0.6V
±5V SUPPLIES
–4.8V, –3.3V
–6
+4.95V, –3.3V
–14.8V, –8.3V
+14.9V, –8.3V
–5.3V
–12
–18
–16
10
±15V SUPPLIES
03579-037
INPUT COMMON-MODE VOLTAGE (V)
RLOAD = 2kΩ
03579-027
XXX
NONLINEARITY (5ppm/DIV)
18
–15.3V
–12
–8
–4
0
4
8
12
16
OUTPUT VOLTAGE (V)
VIN (V)
Figure 24. Gain Nonlinearity, G = 10
Figure 27. Input Common-Mode Voltage Range vs. Output Voltage,
G = 1, VREF = 0 V
RLOAD = 10kΩ
VS = ±15V
–10
–8
–6
–4
–2
0
2
4
6
8
10
+3V
3
2
+0.1V, +1.7V
+4.9V, +1.7V
+5V SINGLE SUPPLY,
VREF = +2.5V
1
+0.1V, +0.5V
+4.9V, +0.5V
0
–0.3V
–1
–1
0
1
2
03579-036
INPUT COMMON-MODE VOLTAGE (V)
RLOAD = 2kΩ
03579-028
XXX
NONLINEARITY (50ppm/DIV)
4
3
4
5
6
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 28. Input Common-Mode Voltage Range vs. Output Voltage,
G = 1, VS = +5 V, VREF = 2.5 V
Figure 25. Gain Nonlinearity, G = 100
Rev. 0 | Page 13 of 28
AD8220
VS+
–1
+13V
±15V SUPPLIES
6
+3V
–14.9V, +5.4V
+14.9V, +5.4V
–4.9V, +0.4V
0
–40°C
–2
OUTPUT SWING (V)
12
+4.9V, +0.5V
±5V SUPPLIES
–4.9V, –4.1V
+4.9V, –4.1V
–6
–5.3V
–14.8V, –9V
+14.9V, –9V
–3
+125°C
–4
+4
+3
–18
–16
–12
–8
–4
0
+125°C
4
8
12
+1
VS–
16
2
4
6
OUTPUT VOLTAGE (V)
12
14
–40°C
16
18
Figure 32. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ, G = 10,
VREF = 0 V
4
VS+
–0.2
+3V
3
+125°C
2
+0.1V, +1.7V
+4.9V, +1.7V
+5V SINGLE SUPPLY,
VREF = +2.5V
1
0
+0.4
–1
–1
0
1
+4.9V, –0.5V
–0.3V
2
3
4
+25°C
–40°C
5
+125°C
+85°C
+25°C
–40°C
03579-054
+0.1V, –0.5V
+85°C
OUTPUT SWING (V)
–0.4
03579-038
+0.2
VS–
6
2
4
6
OUTPUT VOLTAGE (V)
8
10
12
14
16
18
DUAL SUPPLY VOLTAGE (±V)
Figure 30. Input Common-Mode Voltage Range vs. Output Voltage,
G = 100, VS = +5 V, VREF = 2.5 V
Figure 33. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ, G = 10,
VREF = 0 V
VS+
15
–1
–40°C
+125°C
10
VOLTAGE SWING (V)
–2
+25°C
+85°C
NOTES
1. THE AD8220 CAN OPERATE UP TO A VBE BELOW
THE NEGATIVE SUPPLY, BUT THE BIAS CURRENT
WILL INCREASE SHARPLY.
+1
–40°C
+25°C
+85°C
6
8
10
+125°C
0
+125°C
–5
–10
03579-052
4
+85°C
5
+85°C
+125°C
VS–
2
–40°C
+25°C
12
14
16
–15
100
18
VOLTAGE SUPPLY (V)
Figure 31. Input Voltage Limit vs. Supply Voltage, G = 1, VREF =0 V
+25°C
–40°C
03579-055
INPUT COMMON-MODE VOLTAGE (V)
10
+25°C
DUAL SUPPLY VOLTAGE (±V)
Figure 29. Input Common-Mode Voltage Range vs. Output Voltage,
G = 100, VREF = 0 V
INPUT VOLTAGE (V)
8
+85°C
03579-053
–15.3V
–1
+85°C
+25°C
+2
–12
03579-039
INPUT COMMON-MODE VOLTAGE (V)
18
1k
10k
RLOAD (Ω)
Figure 34. Output Voltage Swing vs. Load Resistance VS = ±15 V, VREF = 0 V
Rev. 0 | Page 14 of 28
AD8220
5
XX
–40°C
+25°C
47pF
NO LOAD
+85°C
100pF
+125°C
XXX (X)
3
+125°C
1
+25°C
+85°C
–40°C
0
100
20mV/DIV
XX
XX
10k
1k
03579-018
2
03579-056
VOLTAGE SWING (V)
4
5µs/DIV
XX
RLOAD (Ω)
XXX (X)
Figure 35. Output Voltage Swing vs. Load Resistance VS = +5 V, VREF = 2.5 V
Figure 38. Small Signal Pulse Response for Various Capacitive Loads,
VS = ±15 V, VREF = 0 V
VS+
XX
–40°C
+125°C
–2
47pF
100pF
NO LOAD
+85°C
+25°C
–3
XXX (X)
–4
+4
+3
+125°C
+85°C
+25°C
+1
VS–
–40°C
0
2
4
6
8
10
12
14
20mV/DIV
XX
XX
16
03579-019
+2
03579-057
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
–1
5µs/DIV
XX
IOUT (mA)
XXX (X)
Figure 36. Output Voltage Swing vs. Output Current, VS = ±15 V, VREF = 0 V
Figure 39. Small Signal Pulse Response for Various Capacitive Loads,
VS = +5 V, VREF = 2.5 V
+85°C
+25°C
+125°C
–2
+2
+125°C
+1
+85°C
+25°C
–40°C
VS–
0
2
4
6
8
10
12
14
30
25
GAIN = 10, 100, 1000
GAIN = 1
20
15
10
5
0
100
16
IOUT (mA)
03579-021
–1
OUTPUT VOLTAGE SWING (V p-p)
35
03579-058
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
VS+
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 37. Output Voltage Swing vs. Output Current, VS = +5 V, VREF = 2.5 V
Figure 40. Output Voltage Swing vs. Large Signal Frequency Response
Rev. 0 | Page 15 of 28
AD8220
XX
XX
5V/DIV
XXX (X)
XXX (X)
5V/DIV
0.002%/DIV
20µs/DIV
XX
XX
58µs TO 0.01%
74µs TO 0.001%
03579-049
5µs TO 0.01%
6µs TO 0.001%
03579-046
0.002%/DIV
200µs/DIV
XX
XX
XX
XX
XXX (X)
XXX (X)
Figure 41. Large Signal Pulse Response and Settle Time, G = 1,
RL = 10 kΩ, VS = ±15 V, VREF = 0 V
Figure 44. Large Signal Pulse Response and Settle Time, G = 1000,
RL = 10 kΩ, VS = ±15 V, VREF = 0 V
XX
XXX
XXX (X)
5V/DIV
4.3µs TO 0.01%
4.6µs TO 0.001%
20µs/DIV
XX
XX
03579-016
20mV/DIV
03579-047
0.002%/DIV
4µs/DIV
XX
XXX
XXX (X)
Figure 45. Small Signal Pulse Response, G = 1, RL = 2 kΩ, CL = 100 pF,
VS = ±15 V, VREF = 0 V
Figure 42. Large Signal Pulse Response and Settle Time, G = 10,
RL = 10 kΩ, VS = ±15 V, VREF = 0 V
XX
XXX
XXX (X)
5V/DIV
8.1µs TO 0.01%
9.6µs TO 0.001%
20µs/DIV
XX
XX
03579-014
20mV/DIV
03579-048
0.002%/DIV
4µs/DIV
XX
XXX
XXX (X)
Figure 43. Large Signal Pulse Response and Settle Time, G = 100,
RL = 10 kΩ, VS = ±15 V, VREF = 0 V
Figure 46. Small Signal Pulse Response, G = 10, RL = 2 kΩ, CL = 100 pF,
VS = ±15 V, VREF = 0 V.
Rev. 0 | Page 16 of 28
XXX
XXX
AD8220
03579-015
20mV/DIV
03579-012
20mV/DIV
4µs/DIV
4µs/DIV
Figure 47 Small Signal Pulse Response, G = 100, RL = 2 kΩ, C L= 100 pF,
VS = ±15 V, VREF =0 V
Figure 50. Small Signal Pulse Response, G = 10, RL = 2 kΩ, CL = 100 pF,
VS = +5 V, VREF = 2.5 V
XXX
XXX
XXX
XXX
20mV/DIV
03579-010
03579-013
20mV/DIV
4µs/DIV
40µs/DIV
XXX
XXX
Figure 51. Small Signal Pulse Response, G = 100, RL = 2 kΩ, CL = 100 pF,
VS = +5 V, VREF = 2.5 V
XXX
XXX
Figure 48. Small Signal Pulse Response, G = 1000, RL = 2 kΩ, CL = 100 pF,
VS = ±15 V, VREF = 0 V
20mV/DIV
03579-017
03579-011
20mV/DIV
40µs/DIV
4µs/DIV
XXX
XXX
Figure 49. Small Signal Pulse Response, G = 1, RL = 2 kΩ, CL = 100 pF,
VS = +5 V, VREF = 2.5 V
Figure 52. Small Signal Pulse Response, G = 1000,RL = 2 kΩ, CL = 100 pF,
VS = +5 V, VREF = 2.5 V
Rev. 0 | Page 17 of 28
AD8220
10
SETTLED TO 0.001%
SETTLED TO 0.01%
5
0
0
5
10
15
10
SETTLED TO 0.01%
1
20
OUTPUT VOLTAGE STEP SIZE (V)
Figure 53. Settling Time vs. Step Size (G = 1) ±15 V, VREF = 0 V
SETTLED TO 0.001%
03579-041
SETTLING TIME (µs)
100
03579-043
SETTLING TIME (µs)
15
1
10
100
1000
GAIN (V/V)
Figure 54. Settling Time vs. Gain for a 10 V Step, VS = ±15 V, VREF = 0 V
Rev. 0 | Page 18 of 28
AD8220
THEORY OF OPERATION
+VS
+VS
+VS
NODE A
R1
24.7kΩ
+VS
NODE B
RG
–VS
20kΩ
R2
24.7kΩ
–VS
NODE F
+VS
20kΩ
OUTPUT
20kΩ
+VS
+VS
NODE C
J1 Q1
+IN
–VS
A3
VPINCH
NODE E
NODE D
C1
C2
A1
A2
Q2
–IN
J2
VPINCH
+VS
–VS
REF
20kΩ
–VS
–VS
VB
I
03579-006
I
–VS
Figure 55. Simplified Schematic
Using JFET transistors, the AD8220 offers extremely high input
impedance, extremely low bias currents of 10 pA maximum,
low offset current of 0.6 pA maximum, and no input bias
current noise. In addition, input offset is less than 125 μV and
drift is less than 5 μV/°C. Ease of use and robustness were
considered. A common problem for instrumentation amplifiers
is that at high gains, when the input is overdriven,3 an excessive
milliampere input bias current can result and the output can
undergo phase reversal. The AD8220 has none of these
problems; its input bias current is limited to less than 10 μA and
the output does not phase reverse under overdrive fault
conditions.
The AD8220 has extremely low load induced nonlinearity. All
amplifiers that comprise the AD8220 have rail-to-rail output
capability for enhanced dynamic range. The input of the AD8220
can amplify signals with wide common-mode voltages even
slightly lower than the negative supply rail. The AD8220 operates
over a wide supply voltage range. It can operate from either a
single +4.5 V to +36 V supply or a dual ±2.25 V to ±18 V. The
transfer function of the AD8220 is
G =1+
49.4 kΩ
RG
Users can easily and accurately set the gain using a single,
standard resistor. Since the input amplifiers employ a current
feedback architecture, the AD8220 gain-bandwidth product
increases with gain, resulting in a system that does not suffer as
much bandwidth loss as voltage feedback architectures at higher
gains. A unique pinout enables the AD8220 to meet a CMRR
specification of 80 dB through 5 kHz (G = 1). The balanced
pinout, shown in Figure 56, reduces parasitics that adversely
affect CMRR performance. In addition, the new pinout
simplifies board layout because associated traces are grouped
together. For example, the gain setting resistor pins are adjacent
to the inputs, and the reference pin is next to the output.
AD8220
–IN
1
8
+VS
RG
2
7
VOUT
RG
3
6
REF
+IN
4
5
–VS
TOP VIEW
(Not to Scale)
Figure 56. Pin Configuration
3
Overdriving the input at high gains refers to when the input signal is within
the supply voltages but the amplifier cannot output the gained signal. For
example, at a gain of 100, driving the amplifier with 10 V on ±15 V
constitutes overdriving the inputs since the amplifier cannot output 100 V.
Rev. 0 | Page 19 of 28
03579-005
The AD8220 is a JFET input, monolithic instrumentation amplifier
based on the classic three op amp topology (see Figure 55). Input
Transistor J1 and Input Transistor J2 are biased at a fixed current,
so that any input signal forces the output voltages of A1 and A2 to
change accordingly; the input signal creates a current through RG
that flows in R1 and R2 such that the outputs of A1 and A2 provide
the correct, gained signal. Topologically, J1, A1, R1 and J2, A2, R2
can be viewed as precision current feedback amplifiers that have a
gain bandwidth of 1.5 MHz. The common-mode voltage and
amplified differential signal from A1 and A2 are applied to a
difference amplifier that rejects the common-mode voltage but
amplifies the differential signal. The difference amplifier employs
20 kΩ laser trimmed resistors that result in an in-amp with gain
error less than 0.04%. New trim techniques were developed to
ensure that CMRR exceeds 86 dB (G = 1).
AD8220
GAIN SELECTION
Placing a resistor across the RG terminals sets the AD8220 gain,
which can be calculated by referring to Table 5 or by using the
gain equation
RG =
49.4 kΩ
G −1
Table 5. Gains Achieved Using 1% Resistors
Calculated Gain
1.990
4.984
9.998
19.93
50.40
100.0
199.4
495.0
991.0
03579-102
1% Standard Table Value of RG (Ω)
49.9 k
12.4 k
5.49 k
2.61 k
1.00 k
499
249
100
49.9
Figure 58. Example Layout. Bottom Layer of the AD8220 Evaluation Board
Common-Mode Rejection
The AD8220 defaults to G = 1 when no gain resistor is used.
Gain accuracy is determined by the absolute tolerance of RG.
The TC of the external gain resistor increases the gain drift of
the instrumentation amplifier. Gain error and gain drift are kept
to a minimum when the gain resistor is not used.
LAYOUT
A well implemented layout helps to maintain the AD8220’s high
CMRR over frequency. Input source impedance and capacitance
should be closely matched. In addition, source resistance and
capacitance should be placed as close to the inputs as possible.
Grounding
The AD8220’s output voltage is developed with respect to the
potential on the reference terminal. Care should be taken to tie
REF to the appropriate local ground (see Figure 59).
In mixed-signal environments, low level analog signals need to
be isolated from the noisy digital environment. Many ADCs
have separate analog and digital ground pins. Although it is
convenient to tie both grounds to a single ground plane, the
current traveling through the ground wires and PC board can
cause a large error. Therefore, separate analog and digital
ground returns should be used to minimize the current flow
from sensitive points to the system ground.
03579-101
Careful board layout maximizes system performance. In
applications that need to take advantage of the AD8220’s low
input bias current, avoid placing metal under the input path to
minimize leakage current. To maintain high CMRR over
frequency, layout the input traces symmetrically and layout the
RG resistor’s traces symmetrically. Ensure that the traces maintain
resistive and capacitive balance; this holds for additional PCB
metal layers under the input and RG pins. Traces from the gain
setting resistor to the RG pins should be kept as short as possible
to minimize parasitic inductance. An example layout is shown in
Figure 57 and Figure 58. To ensure the most accurate output, the
trace from the REF pin should either be connected to the
AD8220 local ground (see Figure 59) or connected to a voltage
that is referenced to the AD8220 local ground.
The AD8220 has high CMRR over frequency which gives it
greater immunity to disturbances such as line noise and its
associated harmonics in contrast to typical in-amps whose
CMRR falls off around 200 Hz. These in-amps often need
common-mode filters at the inputs to compensate for this
shortcoming. The AD8220 is able to reject CMRR over a greater
frequency range, reducing the need for input common-mode
filtering.
Figure 57. Example Layout. Top Layer of the AD8220 Evaluation Board
Rev. 0 | Page 20 of 28
AD8220
REFERENCE TERMINAL
INPUT BIAS CURRENT RETURN PATH
The reference terminal, REF, is at one end of a 20 kΩ resistor
(see Figure 55). The instrumentation amplifier’s output is
referenced to the voltage on the REF terminal; this is useful
when the output signal needs to be offset to voltages other than
common. For example, a voltage source can be tied to the REF
pin to level-shift the output so that the AD8220 can interface
with an ADC. The allowable reference voltage range is a
function of the gain, common-mode input, and supply voltages.
The REF pin should not exceed either +VS or −VS by more than
0.5 V.
The AD8220 input bias current is extremely small at less than
10 pA. Nonetheless, the input bias current must have a return
path to common. When the source, such as a transformer,
cannot provide a return current path, one should be created
(see Figure 60).
+VS
AD8220
For best performance, especially in cases where the output is
not measured with respect to the REF terminal, source
impedance to the REF terminal should be kept low, since
parasitic resistance can adversely affect CMRR and gain
accuracy.
REF
–VS
TRANSFORMER
POWER SUPPLY REGULATION AND BYPASSING
The AD8220 has high PSRR. However, for optimal
performance, a stable dc voltage should be used to power the
instrumentation amplifier. Noise on the supply pins can
adversely affect performance. As in all linear circuits, bypass
capacitors must be used to decouple the amplifier.
+VS
C
R
1
fHIGH-PASS = 2πRC
A 0.1 µF capacitor should be placed close to each supply pin. A
10 µF tantalum capacitor can be used further away from the
part (see Figure 59). In most cases, it can be shared by other
precision integrated circuits.
AD8220
C
REF
–VS
+VS
AC-COUPLED
03579-002
R
Figure 60. Creating an IBIAS Path
0.1µF
10µF
INPUT PROTECTION
+IN
VOUT
AD8220
LOAD
0.1µF
–VS
10µF
03579-001
REF
–IN
Figure 59. Supply Decoupling, REF and Output Referred to Ground
All terminals of the AD8220 are protected against ESD.4 In
addition, the input structure allows for dc overload conditions a
diode drop above the positive supply and a diode drop below
the negative supply. Voltages beyond a diode drop of the
supplies cause the ESD diodes to conduct and enable current to
flow through the diode. Therefore, an external resistor should
be used in series with each of the inputs to limit current for
voltages above +Vs. In either scenario, the AD8220 safely
handles a continuous 6 mA current at room temperature.
For applications where the AD8220 encounters extreme
overload voltages, as in cardiac defibrillators, external series
resistors and low leakage diode clamps such as BAV199Ls,
FJH1100s, or SP720s should be used.
4
ESD protection is guaranteed to 4 kV (human body model).
Rev. 0 | Page 21 of 28
AD8220
+15V
RF INTERFERENCE
FilterFreq DIFF =
1
2πRCG
FilterFreqCM =
1
2πRCG
–IN
AD8220
0.1µF
R
REF
–IN
4.02kΩ
1nF
10µF
DRIVING AN ANALOG-TO-DIGITAL CONVERTER
VOUT
An instrumentation amplifier is often used in front of an analog-todigital converter to provide CMRR and additional conditioning
such as a voltage level shift and gain (see Figure 63). In this
example, a 2.7 nF capacitor and a 1 kΩ resistor create an antialiasing filter for the AD7685. The 2.7 nF capacitor also serves to
store and deliver necessary charge to the switched capacitor input
of the ADC. The 1 kΩ series resistor reduces the burden of the
2.7 nF load from the amplifier. However, large source impedance in
front of the ADC can degrade THD.
REF
10µF
–15V
To eliminate high frequency common-mode signals while using
smaller source resistors, a low-pass R-C network can be placed
at the input of the instrumentation amplifier (see Figure 62).
The filter limits the input signal bandwidth according to the
following relationship:
FilterFreqCM
VOUT
AD8220
10nF
The common-mode input voltage range is a function of the
input range and the outputs of Internal Amplifier A1, Internal
Amplifier A2, and Internal Amplifier A3, the reference voltage,
and the gain. Figure 27, Figure 28, Figure 29, and Figure 30
show common-mode voltage ranges for various supply voltages
and gains.
Figure 61. RFI Filtering Without External Capacitors
FilterFreq DIFF =
CD
COMMON-MODE INPUT VOLTAGE RANGE
CG
CG
–VS
+IN
4.02kΩ
–15V
+IN
R
1nF
Figure 62. RFI Suppression
10µF
–VS
10µF
0.1µF
03579-030
R
CC
R
CC
+15V
0.1µF
0.1µF
03579-003
RF rectification is often a problem in applications where there are
large RF signals. The problem appears as a small dc offset voltage.
The AD8220 by its nature has a 5 pF gate capacitance, CG, at its
inputs. Matched series resistors form a natural low-pass filter that
reduces rectification at high frequency (see Figure 61). The
relationship between external, matched series resistors and the
internal gate capacitance is expressed as follows:
The example shown in Figure 63 is for sub-60 kHz applications.
For higher bandwidth applications where THD is important, the
series resistor needs to be small. At worst, a small series resistor
can load the AD8220, potentially causing the output to overshoot
or ring. In such cases, a buffer amplifier, such as the AD8615,
should be used after the AD8220 to drive the ADC.
+5V
1
2πR(2 CD + CC + CG )
10µF
0.1µF
ADR435
+5V
1
=
2πR(CC + CG )
4.7µF
+IN
±50mV
1kΩ
AD8220
1.07kΩ
REF
2.7nF
AD7685
–IN
Rev. 0 | Page 22 of 28
+2.5V
03579-033
Mismatched CC capacitors result in mismatched low-pass filters.
The imbalance causes the AD8220 to treat what would have
been a common-mode signal as a differential signal. To reduce
the effect of mismatched external CC capacitors, select a value of
CD greater than 10 times CC. This sets the differential filter
frequency lower than the common-mode frequency.
Figure 63. Driving an ADC in a Low Frequency Application
AD8220
APPLICATIONS
Measuring small signals that are in the amplifier’s noise or offset
can be a challenge. Figure 64 shows a circuit that can improve
the resolution of small ac signals. The large gain reduces the
referred input noise of the amplifier to 14 nV/√Hz. Thus,
smaller signals can be measured since the noise floor is lower.
DC offsets that would have been gained by 100 are eliminated
from the AD8220 output by the integrator feedback network.
At low frequencies, the OP1177 forces the AD8220 output to
0 V. Once a signal exceeds fHIGH-PASS, the AD8220 outputs the
amplified input signal.
When using this circuit to drive a differential ADC, VREF can be
set using a resistor divider from the ADC’s reference to make
the output ratiometric with the ADC as shown in Figure 66.
+VS
0.1µF
+IN
R
499Ω
fHIGH-PASS =
AD8220
R
15.8kΩ
REF
DIFFERENTIAL OUTPUT
C
–IN
In certain applications, it is necessary to create a differential
signal. New high resolution analog-to-digital converters often
require a differential input. In other cases, transmission over a
long distance can require differential processing for better
immunity to interference.
Figure 65 shows how to configure the AD8220 to output a
differential signal. An OP1177 op amp is used to create a
differential voltage. Errors from the op amp are common to
both outputs and are thus common mode. Likewise, errors from
using mismatched resistors cause a common-mode dc offset
error. Such errors are rejected in differential signal processing
by differential input ADCs or instrumentation amplifiers.
Rev. 0 | Page 23 of 28
1
2πRC
1µF
0.1µF
+VS
0.1µF
–VS
OP1177
+VS
10µF
–VS
10µF
0.1µF
–VS
Figure 64. AC-Coupled Circuit
VREF
03579-004
AC-COUPLED INSTRUMENTATION AMPLIFIER
AD8220
+15V
AMPLITUDE
0.1µF
+5V
TIME
–5V
+IN
VOUTA = +VIN + VREF
2
AD8220
±5V
AMPLITUDE
+5.0V
+2.5V
+0V
REF
4.99kΩ
–IN
TIME
0.1µF
–15V
–15V
OP1177
+15V
4.99kΩ
0.1µF
0.1µF
10µF
AMPLITUDE
+5.0V
+2.5V
+0V
VREF
2.5V
TIME
03579-008
+5V
VOUTB = –VIN + VREF
2
Figure 65. Differential Output with Level Shift
+15V
0.1µF
+IN
VOUTA = +VIN + VREF
2
AD8220
±5V
TO 0V TO +5V ADC
REF
4.99kΩ
–IN
+5V FROM REFERENCE
VREF
2.5V
0.1µF
+5V
10µF
–15V
–15V
+5V FROM REFERENCE
4.99kΩ
0.1µF
OP1177
4.99kΩ
+15V
+AIN
10nF
4.99kΩ
REF
–AIN
0.1µF
TO 0V TO +5V ADC
VOUTB = –VIN + VREF
2
Figure 66. Configuring the AD8220 to Output A Ratiometric, Differential Signal
Rev. 0 | Page 24 of 28
03579-031
TIME
AD8220
ELECTROCARDIOGRAM SIGNAL CONDITIONING
In addition, the AD8220 JFET inputs have ultralow input bias
current and no current noise, making it useful for ECG
applications where there are often large impedances. The MSOP
package and the AD8220’s optimal pinout allow smaller
footprints and more efficient layout, paving the way for next
generation portable ECGs.
The AD8220 makes an excellent input amplifier for next
generation ECGs. Its small size, high CMRR over frequency,
rail-to-rail output, and JFET inputs are well suited for this
application. Potentials measured on the skin range from 0.2 mV
to 2 mV. The AD8220 solves many of the typical challenges of
measuring these body surface potentials. The AD8220’s high
CMRR helps reject common-mode signals that come in the
form of line noise or high frequency EMI from equipment in
the operating room. Its rail-to-rail output offers wide dynamic
range allowing for higher gains than would be possible using
other instrumentation amplifiers. JFET inputs offer a large
input capacitance of 5 pF. A natural RC filter is formed reducing
high frequency noise when series input resistors are used in
front of the AD8220 (see the RF Interference section).
INSTRUMENTATION
AMPLIFIER
G = +14
+5V
2.2pF
B
15kΩ
AD8220
14kΩ
–5V +5V
47nF
HIGH-PASS FILTER 0.033Hz
+5V
4.12kΩ
24.9kΩ
2.2pF
19.3kΩ
2.5V
+5V
14.5kΩ
500Ω
AD7685
ADC
REF
+5V
1.15kΩ
33nF
2.5V
OP2177
AD8618
2.7nF
1MΩ
+5V
–5V
68nF
+5V
AD8618
220pF
–5V
14.5kΩ
AD8618
+5V
AD8618
4.7µF
10kΩ
33nF
19.3kΩ
14kΩ
24.9kΩ
10pF
C
2.5V
57.6kΩ
+5V
10kΩ
LOW-PASS FIFTH ORDER FILTER AT 157Hz
G = +50
1.18kΩ
2.5V
4.99kΩ
22nF
4.7µF
REFERENCE
ADR435
2.5V
–5V
OP AMPS
68pF
12.7kΩ
866kΩ
+5V
499kΩ
OP2177
03579-032
A
Figure 67 shows an example ECG schematic. Following the
AD8220 is a 0.03 Hz high-pass filter, formed by the 4.7 μF
capacitor and the 1 MΩ resistor, which removes the dc offset
that develops between the electrodes. An additional gain of 50,
provided by the AD8618, makes use of the 0 V to 5 V input
range of the ADC. An active, fifth order, low-pass Bessel filter
removes signals greater than approximately 160 Hz. An OP2177
buffers, inverts, and gains the common-mode voltage taken at
the mid-point of the AD8220 gain setting resistors. This right
leg drive circuit helps cancel common-mode signals by
inverting the common-mode signal and driving it back into the
body. A 499 kΩ series resistor at the output of the OP2177
limits the current driven into the body.
–5V
Figure 67. Example ECG Schematic
Rev. 0 | Page 25 of 28
AD8220
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5
5.15
4.90
4.65
4
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
0.23
0.08
8°
0°
0.80
0.60
0.40
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 68. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8220ARMZ2
AD8220ARMZ-RL1
AD8220ARMZ-R72
AD8220BRMZ2
AD8220BRMZ-RL2
AD8220BRMZ-R72
AD8220-EVAL
1
2
Temperature Range1
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
Evaluation Board
See the Typical Performance Characteristics section for expected operation from 85°C to 125°C.
Z = Pb-free part.
Rev. 0 | Page 26 of 28
Package Option
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
Branding
H01
H01
H01
H0P
H0P
H0P
AD8220
NOTES
Rev. 0 | Page 27 of 28
AD8220
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03579-0-4/06(0)
Rev. 0 | Page 28 of 28