AD AD9410/PCB

a
FEATURES
SNR = 54 dB with 99 MHz Analog Input
500 MHz Analog Bandwidth
On-Chip Reference and Track/Hold
1.5 V p-p Differential Analog Input Range
5.0 V and 3.3 V Supply Operation
3.3 V CMOS/TTL Outputs
Power: 2.1 W Typical at 210 MSPS
Demultiplexed Outputs Each at 105 MSPS
Output Data Format Option
Data Sync Input and Data Clock Output Provided
Interleaved or Parallel Data Output Option
APPLICATIONS
Communications and Radar
Local Multipoint Distribution Service (LMDS)
High-End Imaging Systems and Projectors
Cable Reverse Path
Point-to-Point Radio Link
10-Bit, 210 MSPS
A/D Converter
AD9410
FUNCTIONAL BLOCK DIAGRAM
REFIN
REFOUT
AGND DGND VD VDD VCC
AD9410
REFERENCE
PORT
A
AIN
AIN
DS
DS
ENCODE
ENCODE
ADC
10-BIT
CORE
T/H
10
ORA
D9A–D0A
10
PORT
B
10
ORB
D9B–D0B
TIMING AND
SYNCHRONIZATION
DCO
DCO
DFS
I/P
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9410 is a 10-bit monolithic sampling analog-to-digital
converter with an on-chip track-and-hold circuit and is optimized for high-speed conversion and ease of use. The product
operates at a 210 MSPS conversion rate, with outstanding
dynamic performance over its full operating range.
High Resolution at High Speed—The architecture is specifically
designed to support conversion up to 210 MSPS with outstanding dynamic performance.
The ADC requires a 5.0 V and 3.3 V power supply and up to a
210 MHz differential clock input for full performance operation.
No external reference or driver components are required for many
applications. The digital outputs are TTL/CMOS-compatible,
and separate output power supply pins also support interfacing
with 3.3 V logic.
Output Data Clock—The AD9410 provides an output data
clock synchronous with the output data, simplifying the timing
between data and other logic.
The clock input is differential and TTL/CMOS-compatible. The
10-bit digital outputs can be operated from 3.3 V (2.5 V to 3.6 V)
supplies. Two output buses support demultiplexed data up to
105 MSPS rates, and binary or two’s complement output coding
format is available. A data sync function is provided for timingdependent applications. An output clock simplifies interfacing to
external logic. The output data bus timing is selectable for parallel
or interleaved mode, allowing for flexibility in latching output data.
Demultiplexed Output—Output data is decimated by two and
provided on two data ports for ease of data transport.
Data Synchronization—A DS input is provided to allow for
synchronization of two or more AD9410s in a system, or
to synchronize data to a specific output port in a single
AD9410 system.
Fabricated on an advanced BiCMOS process, the AD9410
is available in an 80-lead surface-mount plastic package
(PowerQuad®2) specified over the industrial temperature range
(–40°C to +85°C).
PowerQuad is a registered trademark of Amkor Electronics, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD9410–SPECIFICATIONS
(VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = –0.5 dBFS; Clock input = 210 MSPS;
DC SPECIFICATIONS T = 25C; unless otherwise noted.)
A
Parameter
Temp
Test
Level
Min
RESOLUTION
Integral Nonlinearity
Gain Error
Gain Tempco
ANALOG INPUT
Input Voltage Range (With Respect to AIN)
Common-Mode Voltage
Input Offset Voltage
POWER SUPPLY
Power Dissipation AC2
Power Dissipation DC3
IVCC3
IVD3
Power Supply Rejection Ratio PSRR
Max
10
DC ACCURACY
No Missing Codes1
Differential Nonlinearity
Reference Voltage
Reference Tempco
Input Resistance
Input Capacitance
Analog Bandwidth, Full Power
Typ
Full
25°C
Full
25°C
Full
25°C
Full
IV
I
VI
I
VI
I
V
Full
Full
25°C
Full
Full
Full
Full
25°C
25°C
V
V
I
VI
VI
V
VI
V
V
25°C
Full
Full
Full
25°C
V
VI
VI
VI
I
–1.0
–1.0
–2.5
–3.0
–6.0
–15
–20
2.4
610
–7.5
Guaranteed
± 0.5
± 1.65
0
130
± 768
3.0
+3
2.5
50
875
3
500
2.1
2.0
128
401
+0.5
Unit
Bits
+1.25
+1.5
+2.5
+3.0
+6.0
+15
+20
2.6
1250
2.4
145
480
+7.5
LSB
LSB
LSB
LSB
% FS
ppm/°C
mV p-p
V
mV
mV
V
ppm/°C
Ω
pF
MHz
W
W
mA
mA
mV/V
NOTES
1
Package heat slug should be attached when operating at greater than 70 °C ambient temperature.
2
Encode = 210 MSPS, A IN = –0.5 dBFS 10 MHz sine wave, I VDD = 31 mA typical at C LOAD = 5 pF.
3
Encode = 210 MSPS, A IN = dc, outputs not switching.
Specifications subject to change without notice.
(VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = –0.5 dBFS; Clock
SWITCHING SPECIFICATIONS input = 210 MSPS; T = 25C; unless otherwise noted.)
A
Parameter
Temp
Test
Level
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Encode Pulsewidth High (tEH)
Encode Pulsewidth Low (tEL)
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Output Valid Time (tV)
Output Propagation Delay (tPD)
Output Rise Time (tR)
Output Fall Time (tF)
CLKOUT Propagation Delay1 (tCPD)
Data to DCO Skew (tPD–tCPD)
DS Setup Time (tSDS)
DS Hold Time (tHDS)
Interleaved Mode (A, B Latency)
Parallel Mode (A, B Latency)
Full
Full
25°C
25°C
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
VI
IV
IV
IV
V
V
VI
VI
V
V
VI
IV
IV
IV
VI
VI
Min
Typ
Max
210
100
1.2
1.2
2.4
2.4
1.0
0.65
3.0
7.4
2.6
0
0.5
0
1.8
1.4
4.8
1
A = 6, B = 6
A = 7, B = 6
6.4
2
Unit
MSPS
MSPS
ns
ns
ns
ps rms
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
Cycles
NOTES
1
CLOAD = 5 pF.
Specifications subject to change without notice.
–2–
REV. 0
DIGITAL SPECIFICATIONS
AD9410
(VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = –0.5 dBFS;
Clock input = 210 MSPS; TA = 25C; unless otherwise noted.)
Parameter
Temp
Test
Level
DIGITAL INPUTS
DFS, Input Logic “1” Voltage
DFS, Input Logic “0” Voltage
DFS, Input Logic “1” Current
DFS, Input Logic “0” Current
I/P Input Logic “1” Current1
I/P Input Logic “0” Current1
ENCODE, ENCODE Differential Input Voltage
ENCODE, ENCODE Differential Input Resistance
ENCODE, ENCODE Common-Mode Input Voltage2
DS, DS Differential Input Voltage
DS, DS Common-Mode Input Voltage
Digital Input Pin Capacitance
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
IV
IV
V
V
V
V
IV
V
V
IV
V
V
4
Full
Full
VI
VI
VDD – 0.05
DIGITAL OUTPUTS
Logic “1” Voltage (VDD = 3.3 V)
Logic “0” Voltage (VDD = 3.3 V)
Output Coding
Min
Typ
Max
1
50
50
400
1
0.4
1.6
1.5
0.4
1.5
3
0.05
Binary or Two’s Complement
Unit
V
V
µA
µA
µA
µA
V
kΩ
V
V
V
pF
V
V
NOTES
1
I/P pin Logic “1” = 5 V, Logic “0” = GND. It is recommended to place a series 2.5 k Ω (± 10%) resistor to V DD when setting to Logic “1” to limit input current.
2
See Encode Input section in Applications section.
Specifications subject to change without notice.
AC SPECIFICATIONS
(VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = –0.5 dBFS; Clock input = 210 MSPS;
TA = 25C; unless otherwise noted.)
Parameter
DYNAMIC PERFORMANCE
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
fIN = 10.3 MHz
fIN = 82 MHz
fIN = 160 MHz
Signal-to-Noise Ratio (SINAD)
(With Harmonics)
fIN = 10.3 MHz
fIN = 82 MHz
fIN = 160 MHz
Effective Number of Bits
fIN = 10.3 MHz
fIN = 82 MHz
fIN = 160 MHz
Second Harmonic Distortion
fIN = 10.3 MHz
fIN = 82 MHz
fIN = 160 MHz
Third Harmonic Distortion
fIN = 10.3 MHz
fIN = 82 MHz
fIN = 160 MHz
Spurious Free Dynamic Range (SFDR)
fIN = 10.3 MHz
fIN = 82 MHz
fIN = 160 MHz
Two-Tone Intermod Distortion IMD1
fIN1 = 80.3 MHz, fIN2 = 81.3 MHz
Temp
Test
Level
25°C
25°C
V
V
25°C
25°C
25°C
I
I
V
25°C
25°C
25°C
Typ
Max
Unit
2
2
ns
ns
52.5
52
55
54
53
dB
dB
dB
I
I
V
51
50
54
53
52
dB
dB
dB
25°C
25°C
25°C
I
I
V
8.3
8.1
8.8
8.6
8.4
Bits
Bits
Bits
25°C
25°C
25°C
I
I
V
–56
–55
–65
–63
–65
dBc
dBc
dBc
25°C
25°C
25°C
I
I
V
–58
–57
–69
–67
–62
dBc
dBc
dBc
25°C
25°C
25°C
I
I
V
56
54
61
60
58
dBc
dBc
dBc
25°C
V
58
dBFS
NOTES
1
IN1, IN2 level = –7 dBFS.
Specifications subject to change without notice.
REV. 0
Min
–3–
–4–
DCO
STATIC
STATIC
PORT B
D7D0
DCO
STATIC
STATIC
PORT B
D7D0
PORT A
D7D0
STATIC
tHDS
SAMPLE N–2
PORT A
D7D0
DS
DS
ENCODE
ENCODE
AIN
tEH
SAMPLE N–1
tEL
tA
SAMPLE N+1
INVALID
INVALID
INVALID
PARALLEL DATA OUT
INVALID
INVALID
INVALID
INVALID
SAMPLE N+3
SAMPLE N+2
INTERLEAVED DATA OUT
tSDS
1/fS
SAMPLE N
INVALID
SAMPLE N+4
tCPD
INVALID
INVALID
INVALID
INVALID
tPD
SAMPLE N+6
SAMPLE N+5
DATA N
INVALID
DATA N
DATA N+1
DATA N+2
DATA N+1
DATA N+2
DATA N+3
tV
AD9410
Figure 1. Timing Diagram
REV. 0
AD9410
ABSOLUTE MAXIMUM RATINGS 1
EXPLANATION OF TEST LEVELS
Test Level
VD, VCC, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . 0 V to VCC + 0.5 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . 0 V to VDD + 0.5 V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VD + 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature2 . . . . . . . . . . . . . . . . 150°C
I.
100% production tested.
II. 100% production tested at 25°C and sample tested at
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability. Stresses
above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions outside of those indicated in the operation sections
of this specification is not implied.
2
Typical θJA = 22°C/W (heat slug not soldered), typical θJA = 16°C/W (heat slug
soldered), for multilayer board in still air with solid ground plane.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range.
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
AD9410BSQ
AD9410/PCB
–40°C to +85°C
25°C
PowerQuad 2
Evaluation Board
SQ-80
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9410 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. 0
–5–
WARNING!
ESD SENSITIVE DEVICE
AD9410
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1, 2, 8, 9, 12, 13, 16, 17, 20, 21, 24,
27, 28, 29, 30, 71, 72, 73, 74, 77, 78
3, 7, 14, 15
4
5
6
10
11
18
19
22
23
AGND
Analog Ground.
VCC
REFOUT
REFIN
DNC
AIN
AIN
ENCODE
ENCODE
DS
DS
25, 26, 31, 32, 69, 70, 75, 76
33, 40, 49, 52, 59, 68
34, 41, 48, 53, 60, 67
35–39
42–46
47
50
51
54–58
61–65
66
79
80
VD
DGND
VDD
DB0–DB4
DB5–DB9
ORB
DCO
DCO
DA0–DA4
DA5 –DA9
ORA
DFS
I/P
5 V Supply. (Regulate to within ± 5%.)
Internal Reference Output.
Internal Reference Input.
Do Not Connect.
Analog Input—True.
Analog Input—Complement.
Clock Input—True.
Clock Input—Complement.
Data Sync (Input)—True. Tie LOW if not used.
Data Sync (Input)—Complement. Float and decouple with 0.1 µF
capacitor if not used.
3.3 V Analog Supply. (Regulate to within ± 5%.)
Digital Ground.
3.3 V Digital Output Supply. (2.5 V to 3.6 V)
Digital Data Output for Channel B. (LSB = DB0.)
Digital Data Output for Channel B. (MSB = DB9.)
Data Overrange for Channel B.
Clock Output—Complement.
Clock Output—True.
Digital Data Output for Channel A. (LSB = DA0.)
Digital Data Output for Channel A. (MSB = DA9.)
Data Overrange for Channel A.
Data Format Select. HIGH = Two’s Complement, LOW = Binary.
Interleaved or Parallel Output Mode. Low = Parallel Mode, High =
Interleaved Mode. If tying high, use a current limiting series resistor
(2.5 kΩ) to the 5 V supply.
–6–
REV. 0
AD9410
AGND
AGND
AGND
VD
VD
DGND
74
73
72
71
70
69
68
DA5
AGND
75
DA6
VD
76
DA7
VD
77
DA8
AGND
78
DA9 (MSB)
AGND
79
VDD
DFS
80
ORA
I/P
PIN CONFIGURATION
67
66
65
64
63
62
61
60
VDD
59
DGND
VCC 3
58
DA4
REFOUT 4
57
DA3
REFIN 5
56
DA2
55
DA1
AGND 1
AGND 2
PIN 1
IDENTIFIER
DNC 6
VCC 7
54
DA0 (LSB)
AGND 8
53
VDD
AGND 9
52
DGND
AD9410
51
DCO
TOP VIEW
80-Lead PowerQuad2
(Not to Scale)
50
DCO
AGND 12
49
DGND
AGND 13
48
VDD
VCC 14
47
ORB
VCC 15
46
DB9 (MSB)
AGND 16
45
DB8
AGND 17
44
DB7
ENCODE 18
43
DB6
ENCODE 19
42
DB5
AGND 20
41
VDD
AIN 10
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
AGND
DS
DS
AGND
VD
VD
AGND
AGND
AGND
AGND
VD
VD
DGND
VDD
(LSB) DB0
DB1
DB2
DB3
DB4
DGND
AIN 11
DNC DO NOT CONNECT
REV. 0
–7–
AD9410
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog
signal frequency drops by no more than 3 dB below the
guaranteed limit.
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Maximum Conversion Rate
Aperture Delay
The encode rate at which parametric testing is performed.
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog
input is sampled.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Out-of-Range Recovery Time
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
Out-of-range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
positive full scale to 10% above negative full scale, or from 10%
below negative full scale to 10% below positive full scale.
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a
network analyzer.
Noise (For Any Range Within the ADC)
Differential Analog Input Voltage Range
 FSdBm − SIGNALdBFS 



10
The peak-to-peak differential voltage that must be applied to the
converter to generate a full-scale response. Peak differential voltage
is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of
phase. Peak-to-peak differential is computed by rotating the
inputs phase 180 degrees and taking the peak measurement
again. The difference is then computed between both peak
measurements.
VNOISE = | Z | ×0.001 × 10
Where Z is the input impedance, FS is the full scale of the device
for the frequency in question, SNR is the value for the particular
input level, and SIGNAL is the signal level within the ADC
reported in dB below full scale. This value includes both thermal
and quantization noise.
Power Supply Rejection Ratio
The deviation of any code width from an ideal 1 LSB step.
The ratio of a change in input offset voltage to a change in
power supply voltage.
Effective Number of Bits
Signal-to-Noise-and-Distortion (SINAD)
The effective number of bits (ENOB) is calculated from the
measured SINAD based on the equation.
The ratio of the rms signal amplitude (set 0.5 dB below full
scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc.
Differential Nonlinearity
 Full Scale Amplitude 
SINADMEASURED – 1.76 dB + 20 log 

 Input Amplitude 
ENOB =
6.02
Signal-to-Noise Ratio (Without Harmonics)
The ratio of the rms signal amplitude (set at 0.5 dB below full
scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic 1 state to achieve
rated performance; pulsewidth low is the minimum time
ENCODE pulse should be left in low state. See timing implications of changing tENCH in text. At a given clock rate, these specs
define an acceptable ENCODE duty cycle.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered), or dBFS (always
related back to converter full scale).
Full-Scale Input Power
Transient Response Time
Expressed in dBm. Computed using the following equation:
POWERFULL SCALE
 V 2 FULL SCALErms

Z INPUT
= 10 log 

0.001


Transient response time is defined as the time it takes for the
ADC to reacquire the analog input after a transient from 10%
above negative full scale to 10% below positive full scale.






Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.
Harmonic Distortion, Second
Two-Tone SFDR
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).
Integral Nonlinearity
Worst Other Spur
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least-square curve fit.
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.
Harmonic Distortion, Third
–8–
REV. 0
AD9410
Table I. Output Coding (VREF = 2.5 V)
Step
AIN–AIN
Digital Outputs
Offset Binary
Digital Outputs
Two’s Complement
ORA, ORB
1023
•
•
513
512
511
•
•
0
> 0.768
0.768
•
•
0.0015
0.0
–0.0015
•
•
–0.768
< –0.768
11 1111 1111
11 1111 1111
•
•
10 0000 0001
10 0000 0000
01 1111 1111
•
•
00 0000 0000
00 0000 0000
01 1111 1111
01 1111 1111
•
•
00 0000 0001
00 0000 0000
11 1111 1111
•
•
10 0000 0000
10 0000 0000
1
0
•
•
0
0
0
•
•
0
1
VCC
VCC
1.5k
1.5k
AIN
AIN
2.25k
VREFOUT
2.25k
Figure 6. Equivalent Reference Output Circuit
Figure 2. Equivalent Analog Input Circuit
VCC
VCC
DFS
100k
VREFIN
Figure 7. Equivalent DFS Input Circuit
Figure 3. Equivalent Reference Input Circuit
VCC
17.5k
VCC
300
300
DS
17k
450
450
17k
7.5k
ENCODE
ENCODE
100
DS
100
8k
8k
Figure 8. Equivalent DS Input Circuit
Figure 4 Equivalent Encode Input Circuit
VCC
17.5k
VDD
300
I/P
DIGITAL
OUTPUT
7.5k
Figure 9. Equivalent I/P Input Circuit
Figure 5. Equivalent Digital Output Circuit
REV. 0
–9–
AD9410 –Typical Performance Characteristics
55
0
ENCODE = 210MSPS
AIN = 40MHz @ –0.5dBFS
SNR = 54.5dB
SINAD = 53.5dB
–20
54
53
SNR
52
–40
dB
dB
51
–60
50
49
–80
48
SINAD
47
–100
46
45
–120
0
105
0
50
100
MHz
TPC 1. Single Tone at 40 MHz, Encode = 210 MSPS
150
AIN – MHz
200
250
TPC 4. SNR/SINAD vs. AIN Encode = 210 MSPS
0
55.0
ENCODE = 210MSPS
AIN = 100MHz @ –0.5dBFS
SNR = 53.5dB
SINAD = 52.5dB
–20
54.5
SNR
54.0
53.5
–40
dB
dB
53.0
–60
52.5
SINAD
52.0
–80
51.5
51.0
–100
50.5
–120
50.0
100
105
0
120
140
160
MHz
180
200
220
240
MHz
TPC 2. Single Tone at 100 MHz, Encode = 210 MSPS
TPC 5. SNR/SINAD vs. FS AIN = 70 MHz
60
0
ENCODE = 210MSPS
AIN = 160MHz @ –0.5dBFS
SNR = 53dB
SINAD = 52dB
–20
55
SNR
SINAD
50
dB
dB
–40
–60
45
–80
40
–100
35
–120
30
105
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
ns
MHz
TPC 3. Single Tone at 160 MHz, Encode = 210 MSPS
TPC 6. SNR/SINAD vs. Encode Positive Pulsewidth
(FS = 210 MSPS, AIN = 70 MHz)
–10–
REV. 0
AD9410
0
2.52
ENCODE = 210MSPS
AIN1, AIN2 = –7dBFS
SFDR = 62dBFS
–20
2.51
2.50
VOLTS
dB
–40
–60
2.49
–80
2.48
–100
2.47
–120
2.46
4.0
105
0
4.2
4.4
MHz
4.6
4.8
5.0
5.2
5.4
5.6
ANALOG SUPPLY
TPC 7. Two Tone Test AIN 1 = 80.3 MHz, AIN 2 = 81.3 MHz
TPC 10. VREFOUT vs. Analog 5 V Supply
55.5
460
55.0
410
IAhi3
360
54.5
310
54.0
260
mA
dB
SNR
53.5
210
53.0
160
52.5
IAhi5
110
SINAD
52.0
60
51.5
–40
10
100
Ivdd
–20
0
20
40
60
80
100
120
120
140
160
MSPS
TEMPERATURE – C
TPC 8. SNR/SINAD vs. Temperature,
Encode = 210 MSPS, AIN = 70 MHz
180
200
220
TPC 11. Power Supply Currents vs. Encode
74
2.55
72
2.50
H2
70
2.45
VOLTS
dB
68
66
H3
2.40
64
2.35
62
2.30
60
58
–40
2.25
–20
0
20
40
60
80
100
120
0
TPC 9. Second and Third Harmonics vs. Temperature;
AIN = 70 MHz, Encode = 210 MSPS
REV. 0
0.5
1.0
1.5
mA
TEMPERATURE – C
TPC 12. VREFOUT vs. ILOAD
–11–
2.0
2.5
AD9410
2.503
5.1
2.502
4.9
TPD
TV
2.501
2.500
ns
VOLTS
4.7
4.5
2.499
TCPD
4.3
2.498
4.1
2.497
2.496
–40
–20
0
20
40
TEMPERATURE – C
60
3.9
–40
80
TPC 13. VREFOUT vs. Temperature
–20
0
20
40
TEMPERATURE – C
60
80
TPC 14. TPD, TV, TCPD vs. Temperature
–12–
REV. 0
AD9410
APPLICATION NOTES
Analog Input
THEORY OF OPERATION
The analog input to the AD9410 is a differential buffer. For
best dynamic performance, impedances at AIN and AIN should
match. The analog input has been optimized to provide superior
wideband performance and requires that the analog inputs be
driven differentially. SNR and SINAD performance will degrade
significantly if the analog input is driven with a single-ended
signal. A wideband transformer such as Minicircuits ADT1-1WT
can be used to provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Both
analog inputs are self-biased by an on-chip resistor divider to a
nominal 3 V. (See Equivalent Circuits section.)
USING THE AD9410
ENCODE Input
Any high-speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A Track/Hold
circuit is essentially a mixer, and any noise, distortion, or timing
jitter on the clock will be combined with the desired signal at the
A/D output. For that reason, considerable care has been taken
in the design of the ENCODE input of the AD9410, and the
user is advised to give commensurate thought to the clock source.
To limit SNR degradation to less than 1 dB, a clock source with
less than 1.25 ps rms jitter is required for sampling at Nyquist.
(Valpey Fisher VF561 is an example.) Note that required jitter
accuracy is a function of input frequency and amplitude. Consult
Analog Devices’ application note AN-501, “Aperture Uncertainty and ADC System Performance,” for more information.
Special care was taken in the design of the Analog Input section
of the AD9410 to prevent damage and corruption of data when the
input is overdriven. The nominal input range is 1.5 V diff p-p.
The nominal differential input range is 768 mV p-p × 2.
3.384
VOLTS
The AD9410 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated high bandwidth
track-and-hold circuit that samples the signal prior to quantization by the flash 10-bit core. For ease of use the part includes
an onboard reference and input logic that accepts TTL, CMOS,
or PECL levels.
The ENCODE input is fully TTL/CMOS-compatible. The
clock input can be driven differentially or with a single-ended
signal. Best performance will be obtained when driving the clock
differentially. Both ENCODE inputs are self-biased to 1/3 × VCC
by a high impedance resistor divider. (See Equivalent Circuits
section.) Single-ended clocking, which may be appropriate for
lower frequency or nondemanding applications, is accomplished
by driving the ENCODE input directly and placing a 0.1 µF
capacitor at ENCODE.
AIN
3.000
2.616
AIN
Figure 12. Typical Analog Input Levels
Digital Outputs
AD9410
ENCODE
TTL/CMOS
GATE
ENCODE
0.1F
Figure 10. Driving Single-Ended Encode Input at
TTL/CMOS Levels
An example where the clock is obtained from a PECL driver is
shown in Figure 11. Note that the PECL driver is ac-coupled to
the ENCODE inputs to minimize input current loading. The
AD9410 can be dc-coupled to PECL logic levels resulting in the
ENCODE input currents increasing to approximately 8 mA
typically. This is due to the difference in dc bias between the
ENCODE inputs and a PECL driver. (See Equivalent Circuits section.)
0.1F
ENCODE
PECL
GATE
510
510
0.1F
AD9410
ENCODE
GND
Figure 11. Driving the Encode Inputs Differentially
REV. 0
The digital outputs are TTL/CMOS-compatible for lower power
consumption. The outputs are biased from a separate supply
(VDD), allowing easy interface to external logic. The outputs are
CMOS devices which will swing from ground to VDD (with no
dc load). It is recommended to minimize the capacitive load the
ADC drives by keeping the output traces short (<1 inch, for a
total CLOAD < 5 pF). It is also recommended to place low value
(20 Ω) series damping resistors on the data lines to reduce switching transient effects on performance.
Clock Outputs (DCO, DCO)
The input ENCODE is divided by two and available off-chip at
DCO and DCO. These clocks can facilitate latching off-chip,
providing a low skew clocking solution (see timing diagram).
These clocks can also be used in multiple AD9410 systems to
synchronize the ADCs. Depending on application, DCO or
DCO can be buffered and used to drive the DS inputs on a
second AD9410, ensuring synchronization. The on-chip clock
buffers should not drive more than 5 pF–7 pF of capacitance to
limit switching transient effects on performance.
Voltage Reference
A stable and accurate 2.5 V voltage reference is built into the
AD9410 (VREF OUT). The input range can be adjusted by
varying the reference voltage. No appreciable degradation in
performance occurs when the reference is adjusted ±5%. The fullscale range of the ADC tracks reference voltage changes linearly
within the ± 5% tolerance.
–13–
AD9410
Timing
Data Sync (DS)
The AD9410 provides latched data outputs, with six pipeline
delays in interleaved mode (see Figure 1). In parallel mode, the
A Port has one additional cycle of latency added on-chip to line
up transitions at the data ports—resulting in a latency of seven
cycles for the A Port. The length of the output data lines and
loads placed on them should be minimized to reduce transients
within the AD9410; these transients can detract from the
converter’s dynamic performance.
The minimum guaranteed conversion rate of the AD9410 is
100 MSPS. At internal clock rates below 100 MSPS, dynamic
performance may degrade. Note that lower effective sampling
rates can be obtained simply by sampling just one output port—
decimating the output by two. Lower sampling frequencies can
also be accommodated by restricting the duty cycle of the clock
such that the clock high pulsewidth is a maximum of 5 ns.
The Data Sync input, DS, can be used in applications requiring that a given sample will appear at a specific output Port A or
B. When DS is held high, the ADC data outputs and clock do not
switch and are held static. Synchronization is accomplished by the
assertion (falling edge) of DS, within the timing constraints
TSDS and THDS relative to an encode rising edge. (On initial
synchronization THDS is not relevant.) If DS falls within the
required setup time (TSDS) before a given encode rising edge N,
the analog value at that point in time will be digitized and available at Port B six cycles later (interleaved mode). The very next
sample, N+1, will be sampled by the next rising encode edge and
available at Port A six cycles after that encode edge (interleaved
mode). In dual parallel mode the A Port has a seven cycle latency,
the B Port has a six cycle latency, but data is available at the
same time.
EVALUATION BOARD
REFERENCE
The AD9410 evaluation board offers an easy way to test the
AD9410. The board requires an analog input, clock, and 3 V,
5 V power supplies. The digital outputs and output clocks are
available at a standard 80-lead header P2, P3. The board has
several different modes of operation, and is shipped in the following configuration:
The AD9410 has an on-chip reference of 2.5 V available at
REFOUT (Pin 4). Most applications will simply tie this output
to the REFIN input (Pin 5). This is accomplished by placing a
jumper at E1, E6. An external reference can be used placing a
jumper at E1, E3.
• Output Timing = Parallel Mode
• Output Format = Offset Binary
• Internal Voltage Reference
The chip has two timing modes (see timing diagram). Interleaved mode is selected by Jumper E11, E7. Parallel mode is
selected by Jumper E11, E14.
Power Connector
Data Format Select
Power is supplied to the board via detachable 4-pin power strips
P1, P4, P5.
Data Format Select sets the output data format that the ADC
outputs. Setting DFS (Pin 79) low at E12, E10 sets the output
format to be offset binary; setting DFS high at E12, E16 sets the
output to be two’s complement.
VDAC – Optional DAC Supply Input (3.3 V)
EXT REF – Optional External VREF Input (2.5 V)
VDD – Logic Supply (3.3 V)
3.3 VA – Analog Supply (3.3 V)
5 V – Analog Supply (5 V)
Analog Inputs
The evaluation board accepts a 1.5 V p-p analog input signal
centered at ground at SMB J8. This input is terminated to 50 Ω
on the board at the transformer secondary, but can be terminated at the SMB if an alternative termination is desired. The
input is ac-coupled prior to the transformer. The transformer is
band limited to frequencies between approximately 1 MHz and
400 MHz.
Output Timing
DS Pin
The DS, DS inputs are available at SMB connectors J9X and
J10X. The board is shipped with DS pulled to ground by R26.
DS is floating (R25X is not placed).
DAC Outputs
Each channel is reconstructed by an on-board dual channel
DAC, an AD9751 to assist in debug. The performance of the
DAC has not been optimized and will not give an accurate
measure of the full performance of the ADC. It is a current
output DAC with on-board 50 Ω termination resistors. The
outputs are available at J3 and J4.
Encode
The encode input to the board is at SMB connector J1. The
input is terminated on the board with 50 Ω to ground. The
(>0.5 V p-p) input is ac-coupled and drives a high-speed
differential line receiver (MC10EL16). This receiver provides
sub- nanosecond rise times at its outputs—a requirement for
the ADC clock inputs for optimum performance. The EL16
outputs are PECL levels and are ac-coupled to meet the commonmode dc levels at the AD9410 encode inputs.
–14–
REV. 0
AD9410
GND
GND
C1
10F
C3
10F
C5
10F
5V
C4
10F
VDAC
GND
2
GND
3
EXT REF
4
GND
1
GND
2
GND
3
VDD/3.3V
R4
2.5k
66
65
64
63
62
61
DA7
DA6
DA5
C12
0.1F
VDD 60
VDD
DGND 59
GND
3
VCC
DA4 58
DA4
4
REFOUT
DA3 57
DA3
5
REFIN
DA2 56
DA2
6
DNC
DA1 55
DA1
7
VCC
DA0 54
DA0
8
AGND
9
AGND
10
AIN
11
AIN
12
AGND
13
AGND
14
VCC
15
VCC
DB9 46
DB9
16
AGND
DB8 45
DB8
17
AGND
DB7 44
DB7
ENCT
18
ENCODE
DB6 43
DB6
ENCC
19
ENCODE
DB5 42
DB5
GND
20
AGND
VDD 41
GND
VD
DGND
VDD
DB0
DB1
DB2
DB3
DB4
DGND
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
3.3VA
GND
GND
DB0
DB1
GND
R26
50
J10X
GND
R25X
50
3.3VA
C16
3.3VA 0.1F
Figure 13a. PCB Schematic
–15–
DB3
C19
0.1F
VDD
GND
GND
DB2
3.3VA
C15
0.1F
DB4
GND
VDD
C22
0.1F
DBOR
ORB 47
GND
GND
GND
VDD 48
VD
GND
DGND 49
AGND
5V
DCOC
AGND
GND
DCOT
DCO 50
AGND
C24
0.1F
VDD
C21
0.1F
GND
DCO 51
AGND
GND GND
AD9410
U3
VD
R27
50
VDD 53
DGND 52
VD
GND
J9X
REV. 0
GND
67
DA8
68
DA9
69
DGND
AGND
70
VD
AGND
71
VD
I/P
72
AGND
GND
GND
73
AGND
C25
0.1F
74
AGND
C26
0.1F
1:1
R23
50
75
DS
3
76
AGND
77
AGND
78
AGND
79
AGND
80
DA6
DA5
DAOR
2
6
5
4
GND
GND
DS
2
DA7
3.3VA
GND
AGND
GND
T1
DA8
GND
3.3VA
NOTE:
R3, R6, R7, R24 OPTIONAL
(CAN BE ZERO )
DA9
1
5V
GND
GND
GND
E3 E1
AIN
C14
0.1F
3.3VA
GND
C28
0.1F
5V
J8
C8
0.1F
R15
330
GND
GND
C11
0.1F
R7
100
E7
E11
GND
GND
1
ENCC
VEE 5
GND
E12
R3
100
C27
0.1F
GND
C7
0.1F
VBB
ENCT
Q 6
VDD
R24
100
5V
GND
EXT
REF
C10
0.1F
E16
E14
E6
4
Q
U1
ORA
R6
100
DFS
3.3VA
GND
D
C7
0.1F
7
VDD
GND
GND
4
3
3.3VA
2
5V
D
5V
1
3
2
R11
330
5V
VCC 8
GND GND
E10
P5
NC
GND
GND
4
1
GND
VD
P1
R9
24k
R18
24k
C40
0.1F
MC10EL16
R14
8.2k
VD
1
C6
0.1F
R8
50
GND
5V
R19
8.2k
J1
VDAC
EXT REF
VDD
3.3VA
5V
P4
C2
10F
GND
VDD
C18
0.1F
GND
–16–
GND
VDD
GND
VDD
GND
VDD
GND
VDD
XORA
R2
100
R17
00
R16
00
E23 R43
100
E25
XORD
E22
R42
E20 100
E19
XORC
E21
R37
E26 100
E27
XORB
E28
E18
E17
E24
DCOC
DCOT
GND
C32
0.1F
VDD
DCOTA
XORD
DCOCA
XORC
XORB
DCOTA
DCOTA
XORA
DCOCA
DCOTA
U9
U9
U9
74AC86
9
10
74AC86
12
13
74AC86
4
5
U9
6
CLKA
DRA
R44
3 00
8
CLKB
DRB
R45
11 00
74AC86
2
1
6B 11
7B 10
6 6A
7 7A
DA5
DA4
4 4A
6B 11
7B 10
8B 9
6 6A
7 7A
8 8A
4B 13
4 4A
DB0
DB1
8 8A
7 7A
6 6A
5 5A
DB3
3 3A
2 2A
1 1A
4 4A
DB2
8B 9
7B 10
6B 11
R39
8B 9
7B 10
6B 11
5B 12
4B 13
3B 14
2B 15
1B 16
RPACK
8 8A
7 7A
6 6A
5B 12
3B 14
3 3A
5 5A
2B 15
2 2A
R29
1B 16
1 1A
RPACK
5B 12
5 5A
DB4
DB5
DB6
DB7
DB8
DB9
DBOR
3 3A
DA0
R40
3B 14
4B 13
2 2A
DA1
2B 15
1 1A
DA2
1B 16
RPACK
8B 9
5B 12
5 5A
DA6
8 8A
4B 13
4 4A
DA7
DA3
3B 14
3 3A
DA8
R32
2B 15
2 2A
DA9
1B 16
1 1A
DAOR
RPACK
DY0
DY1
DY2
DY3
DY4
DY5
DY6
DY7
DY8
DY9
DYOR
DX0
DX1
DX2
DX3
DX4
DX5
DX6
DX7
DX8
DX9
DXOR
GND
DY0
DY1
DY2
DY3
DY4
DY5
DY6
DY7
DY8
DY9
GND
GND
DX0
DX1
DX2
CLK 13
Y9 14
Y8 15
Y7 16
Y6 17
Y5 18
Y4 19
Y3 20
Y2 21
Y1 22
Y0 23
VCC 24
U5
12 GND
11 X9
10 X8
9 X7
8 X6
7 X5
6 X4
5 X3
4 X2
3 X1
2 X0
1 DE
CLKA
D0A
D1A
D2A
D3A
CLKB
D0B
D1B
D2B
D3B
D4B
D5B
D6B
D7B
D8B
D9B
VDD
C39
0.1F
GND
CLK 13
Y9 14
Y8 15
Y7 16
74LCXB21
12 GND
11 X9
10 X8
9 X7
Y6 17
DX4
8 X6
D4A
Y5 18
7 X5
DX5
DX3
D5A
Y4 19
U4
D6A
Y3 20
D7A
D8A
D9A
6 X4
Y2 21
Y1 22
Y0 23
VCC 24
5 X3
4 X2
3 X1
2 X0
1 DE
C37
0.1F
VDD
DX6
DX7
DX8
DX9
GND
74LCXB21
GND
4 4A
5 5A
6 6A
D7A
D6A
D5A
8 8A
NC
6 6A
D2B
D0B
8 8A
7 7A
5 5A
4 4A
D4B
D3B
3 3A
2 2A
D6B
D5B
1 1A
D1B
R36
8B 9
7B 10
6B 11
5B 12
4B 13
3B 14
2B 15
1B 16
R28
8B 9
7B 10
6B 11
5B 12
4B 13
3B 14
2B 15
1B 16
R38
8B 9
7B 10
6B 11
5B 12
4B 13
3B 14
2B 15
1B 16
RPACK
8 8A
7 7A
6 6A
5 5A
4 4A
3 3A
2 2A
1 1A
D7B
D8B
D9B
NC
NC
NC
NC
NC
8B 9
7B 10
6B 11
5B 12
4B 13
RPACK
7 7A
6 6A
NC
NC
5 5A
NC
4 4A
3 3A
D0A
1 1A
2 2A
NC
R34
3B 14
2B 15
1B 16
RPACK
8 8A
D1A
D2A
D3A
7 7A
3 3A
D8A
D4A
2 2A
D9A
1 1A
RPACK
DN0
DN1
DN2
DN3
DN4
DN5
DN6
DN7
DN8
DN9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
DM9
GND
GND
40
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
HEADER 40
P3
HEADER 40
P2
39
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
GND
GND
GND
GND
GND
GND
GND
DN0
DN1
DN2
DN3
DN4
DN5
DN6
DN7
DN8
DN9
GND
DRB
GND
GND
GND
GND
GND
GND
GND
GND
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
DM9
GND
DRA
GND
AD9410
Figure 13b. PCB Schematic (Continued)
REV. 0
AD9410
J3
GND
C3
0.1F
R1
50
GND
J4
VDAC
GND
R12
50
GND
C23
0.1F
GND
R5
392
VDAC
GND
GND
VDAC
C20
0.1F
R10
2k
C33
1F
E2
R13
392
E5
GND
E31
VDAC
VDAC
E4
GND GND
E29
GND
E30
GND
48
46
47
45
44
43
42
41
40
38
39
37
E32
VDAC
1
36
DCOCA
2
35
DCOTA
3
34
GND
4
33
E34
E33
GND
5
32
DN0
E35
6
31
DN1
DM9
7
30
DN2
DM8
8
29
DN3
DM7
9
28
DN4
DM6
10
27
DN5
DM5
11
26
DN6
DM4
12
25
DN7
VDAC
C13
0.1F
GND
AD9751
U2
13
DM3
14
15
16
17
18
19
20
DM1
DM0
21
23
22
GND
DM2
24
DN8
DN9
C17
0.1F
GND
VDAC
Figure 13c. PCB Schematic (Continued)
TROUBLESHOOTING
If the board does not seem to be working correctly, try the
following:
• Verify power at IC pins.
• Check that all jumpers are in the correct position for the
desired mode of operation.
• Verify VREF is at 2.5 V.
REV. 0
• Try running encode clock and analog input at low speeds
(10 MSPS/1 MHz) and monitor latch outputs, DAC outputs,
and ADC outputs for toggling.
The AD9410 Evaluation Board is provided as a design example
for customers of Analog Devices, Inc. ADI makes no warranties,
express, statutory, or implied, regarding merchantability or
fitness for a particular purpose.
–17–
AD9410
EVALUATION BOARD LAYOUT
Figure 14. Top Silkscreen
Figure 17. Bottom Components and Routing
Figure 15. Split Power Plane
Figure 18. Bottom Silkscreen
Figure 16. Ground Plane
Figure 19. Top Components and Routing
–18–
REV. 0
AD9410
AD9410 Evaluation Board Bill of Material
Quantity
Reference Description
Device
Package
Value
5
29
1
31
6
3
C1–C5
C6–C30, C32, C37, C39, C40
C33
E1–E7, E10–E12, E14, E16–E35
J1, J3, J4, J8, J9X, J10X
P1, P4, P5
TAJD
603
1206
10 µF
0.1 µF
1 µF
25.531.3425.0
25.602.5453.0
Wieland
2
7
8
1
1
2
1
2
2
5
8
P2, P3
R1, R8, R12, R23*, R25X, R26, R27
R2, R3, R4, R6, R24, R37, R42, R43
R13
R7
R9, R18
R10
R11, R15
R14, R19
R5, R16, R17, R44, R45
R28, R29, R32, R34, R36, R38–R40
Capacitor
Capacitor
Capacitor
Ehole
SMB
4-Pin Power
Connector
40-Pin Header
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
RPACK
50 Ω
100 Ω
392 Ω
100 Ω
24 kΩ
2 kΩ
330 Ω
8.2 kΩ
0Ω
CTS
1
1
1
1
2
1
T1
U1
U2
U3
U4, U5
U9
Transformer (1:1)
MC10EL16
AD9751
AD9410
74LCX821
74AC86
1206
1206
1206
1206
1206
1206
1206
1206
1206
766163220G
22 Ω
ADT1-1WT
SOIC8
LQFP48
LQFP80
SOIC24
SOIC14
*Optional R23 not placed on board (50 Ω termination resistor).
REV. 0
–19–
Minicircuits
AD9410
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
80-Lead PowerQuad 2 (LQFP_ED)
(SQ-80)
C01679–4.5–10/00 (rev. 0)
0.630 (16.00) SQ
0.063 (1.60)
MAX
0.030 (0.75)
0.024 (0.60)
0.018 (0.45)
0.551 (14.00) SQ
80
61
SEATING
PLANE
80
61
60
1
60
1
0.120 (3.04) 45C CHAMFER
4 PLACES
PIN 1
BOTTOM
VIEW
TOP VIEW
0.413 (10.50)
0.394 (10.00) REF
0.374 (9.50)
(PINS DOWN)
NICKEL PLATED
XX
COPLANARITY
0.004 (0.10)
MAX
20
41
21
40
0.006 (0.15)
0.002 (0.05)
0.008 (0.20)
0.004 (0.09)
0.0256 (0.65)
BSC
0.015 (0.38)
0.013 (0.32)
0.009 (0.22)
20
41
0.057 (1.45)
0.055 (1.40)
0.053 (1.35)
7
0
40
21
0.413 (10.50)
0.394 (10.00) REF
0.374 (9.50)
CONTROLLING DIMENSION IN MILLIMETERS.
CENTER FIGURES ARE TYPICAL UNLESS
OTHERWISE NOTED.
PRINTED IN U.S.A.
NOTE
The AD9410 has a conductive heat slug to help dissipate heat
and ensure reliable operation of the device over the full industrial temperature range. The slug is exposed on the bottom of
the package. It is recommended that no PCB traces or vias be
located under the package that could come in contact with the
conductive slug. Attaching the slug to a ground plane while not
required in most applications will reduce the junction temperature of the device which may be beneficial in high temperature
environments.
–20–
REV. 0