ETC AD9617AQ

a
FEATURES
Usable Closed-Loop Gain Range: 61 to 640
Low Distortion: –67 dBc (2nd) at 20 MHz
Small Signal Bandwidth: 190 MHz (AV = +3)
Large Signal Bandwidth: 150 MHz at 4 V p-p
Settling Time: 10 ns to 0.1%; 14 ns to 0.02%
Overdrive and Output Short Circuit Protected
Fast Overdrive Recovery
DC Nonlinearity 10 ppm
APPLICATIONS
Driving Flash Converters
D/A Current-to-Voltage Converters
IF, Radar Processors
Baseband and Video Communications
Photodiode, CCD Preamps
GENERAL DESCRIPTION
The AD9617 is a current feedback amplifier which utilizes a
proprietary architecture to produce superior distortion and dc
precision. It achieves this along with fast settling, very fast slew
rate, wide bandwidth (both small signal and large signal) and
exceptional signal fidelity. The device achieves –67 dBc 2nd
harmonic distortion at 20 MHz while maintaining 190 MHz
small signal and 150 MHz large signal bandwidths.
These attributes position the AD9617 as an ideal choice for
driving flash ADCs and buffering the latest generation of
DACs. Optimized for applications requiring gain between ± 1
to ± 15, the AD9617 is unity gain stable without external
compensation.
Low Distortion, Precision,
Wide Bandwidth Op Amp
AD9617
PIN CONFIGURATION
NC 1
AD9617
8
*
–INPUT 2
7 +VS
+INPUT 3
6 OUTPUT
–VS 4
5
**
NC = NO CONNECT
*OPTIONAL +VS **OPTIONAL –VS
NOTE:
FOR BEST SETTLING TIME AND DISTORTION
PERFORMANCE, USE OPTIONAL SUPPLY
CONNECTIONS. PERFORMANCE INDICATED
IN SPECIFICATIONS IS BASED ON SUPPLY
CONNECTIONS TO THESE PINS.
The AD9617 offers outstanding performance in high fidelity,
wide bandwidth applications in instrumentation ranging from
network and spectrum analyzers to oscilloscopes, and in military
systems such as radar, SIGINT and ESM systems. The superior
slew rate, low overshoot and fast settling of the AD9617 allow the
device to be used in pulse applications such as communications
receivers and high speed ATE. Most monolithic op amps suffer
in these precision pulse applications due to slew rate limiting.
The AD9617J operates over the range of 0°C to +70°C and is
available in either an 8-lead plastic DIP or an 8-1ead plastic
small outline package (SOIC).
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD9617–SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS 1
NOTES
1
Absolute maximum ratings are limiting values to be applied individually and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2
Output is short circuit protected to ground, but not to supplies. Continuous
short circuit to ground may affect device reliability.
3
Typical thermal impedances (part soldered onto board):
Plastic DIP: θJA = 140°C/W; θJC = 30°C/W. SOIC Package: θJA = 155°C/W;
θJC = 40°C/W.
Supply Voltages (± VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . ± Vs
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3 V
Continuous Output Current2 . . . . . . . . . . . . . . . . . . . . . 70 mA
Operating Temperature Ranges
AD9617JN/JR . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature
AD9617JN/JR . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Junction Temperature3
AD9617JN/JR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Lead Soldering Temperature (10 Seconds) . . . . . . . . . +300°C
DC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, A = +3; 6V
V
Parameter
Conditions
1, 2
Input Offset Voltage
Input Offset Voltage TC 2
Input Bias Current2
Inverting
Noninverting
Input Bias Current TC2
Noninverting
Inverting
Input Resistance
Noninverting
Input Capacitance
Noninverting
Common-Mode Input Range3
Common-Mode Rejection Ratio 4
Power Supply Rejection Ratio
Open Loop Gain
TO
Nonlinearity
Output Voltage Range
Output Impedance
Output Current (50 Ω Load)
At DC
At DC
At DC
T = +25°C to TMAX
T = TMIN
= 65 V; RF = 400 V; RLOAD = 100 V)
Test
Temp Level
AD9617JN/JR
AD9617AQ/SQ*
Min Typ Max Min Typ Max
AD9617BQ/TQ*
Min Typ Max
+25°C I
Full
IV
–1.1
–4
+0.5 +2.2 –1.1
+3
+25 –4
+0.5 +2.2
+3
+25
+0.0
–4
+0.5 +1.35 mV
+3
+25
µV/°C
+25°C I
+25°C I
–50
–25
0
+5
+50
+35
0
+5
+50
+35
–25
–15
0
+5
+25
+20
µA
µA
Full
Full
–50
–50
+30
+50
+125 –50
+150 –50
+30
+50
+125
+150
–50
–50
+30
+50
+125
+150
nA/°C
nA/°C
IV
IV
+25°C V
T = TMAX
T = TMIN to +25°C
T = TMIN to TMAX
T = TMIN to +25°C
∆VS = ± 5%
S
–50
–25
60
+25°C
←
←
←
←
Full
V
II
II
II
II
II
± 1.4
± 1.7
44
48
48
1.5
± 1.5
± 1.8
48
51
51
+25°C
+25°C
+25°C
+25°C
←
←
V
IV
II
V
II
II
500
10
± 3.4 ± 3.8
0.07
60
50
60
± 1.4
± 1.7
44
48
48
1.5
± 1.5
± 1.8
48
51
51
500
10
± 3.4 ± 3.8
0.07
60
50
Units
60
kΩ
± 1.4
± 1.7
44
48
48
1.5
± 1.5
± 1.8
48
51
51
pF
V
V
dB
dB
dB
± 3.4
500
10
+3.8
0.07
kΩ
ppm
V
Ω
mA
mA
60
50
NOTES
*Pending obsoletion: last-time buy October 25, 1999.
1
Measured with respect to the inverting input.
2
Typical is defined as the mean of the distribution.
3
Measured in voltage follower configuration.
4
Measured with V IN = +0.25 V.
Specifications subject to change without notice.
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–2–
REV. B
AD9617
AC ELECTRICAL CHARACTERISTICS
Parameter
Conditions
FREQUENCY DOMAIN
Bandwidth (–3 dB)
Small Signal
Large Signal
Bandwidth Variation vs. AV
Amplitude of Peaking (<50 MHz)
VOUT ≤ 2 V p-p
VOUT = 4 V p-p
AV = –1 to ± 15
T = TMIN to +25°C
T = TMAX
Amplitude of Peaking (>50 MHz) T = TMIN to +25°C
T = TMAX
Amplitude of Roll-Off (<60 MHz)
Phase Nonlinearity
DC to 75 MHz
2nd Harmonic Distortion
2 V p-p; 4.3 MHz
2 V p-p; 20 MHz
2 V p-p; 60 MHz
3rd Harmonic Distortion
2 V p-p; 4.3 MHz
2 V p-p; 20 MHz
2 V p-p; 60 MHz
Input Noise Voltage
10 MHz
Inverting Input Noise Current
10 MHz
Average Equivalent Integrated
Input Noise Voltage
0.1 MHz to 200 MHz
TIME DOMAIN
Slew Rate
Rise/Fall Time
VOUT = 2 V Step
VOUT = 4 V Step
VOUT = 4 V Step
Overshoot
Settling Time
To 0.1%
To 0.02%
To 0.1%
To 0.02%
2× Overdrive Recovery to
± 2 mV of Final Value
Propagation Delay
Differential Gain1
Differential Phase1
(Unless otherwise noted, AV = +3; 6VS = 65 V; RF = 400 V; RLOAD = 100 V)
Test
Temp Level
AD9617JN/JR
AD9617AQ/SQ*
Min Typ Max Min Typ Max
AD9617BQ/TQ*
Min Typ Max
Full
Full
+25°C
←
←
←
←
Full
+25°C
Full
Full
Full
Full
Full
Full
+25°C
+25°C
135
145
115
II
IV
V
II
II
II
II
II
V
IV
IV
II
IV
IV
II
V
V
145
115
–78
–59
–43
–75
–61
–46
190
150
40
0
0
0
0
0.1
0.5
–86
–67
–51
–83
–69
–54
1.2
29
0.3
0.6
0.8
1.0
0.6
–78
–59
–43
–75
–61
–46
0.3
0.6
0.8
1.0
0.6
–78
–59
–43
–75
–61
–46
MHz
MHz
MHz
dB
dB
dB
dB
dB
Degree
dBc
dBc
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
55
µV, rms
1400
V/µs
55
VOUT = 4 V Step
Full
IV
1400
T = +25°C to TMAX
T = TMIN
VOUT = 2 V Step
Full
←
←
Full
IV
IV
IV
IV
2.0
2.4
2.4
3
2.0
2.4
2.4
3
2.5
3.3
3.5
14
2.0
2.4
2.4
3
2.5
3.3
3.5
14
ns
ns
ns
%
VOUT = 2 V Step
VOUT = 2 V Step
VOUT = 4 V Step
VOUT = 4 V Step
Full
Full
Full
Full
IV
IV
IV
IV
10
14
11
16
10
14
11
16
15
23
16
24
10
14
11
16
15
23
16
24
ns
ns
ns
ns
VIN = 1.7 V Step
+25°C
+25°C
Full
Full
V
V
V
V
50
2
<0. 01
0.01
50
2
<0. 01
0.01
Full
Full
II
II
34
34
NOTES
*Pending obsoletion: last-time buy October 25, 1999.
1
Frequency = 4.3 MHz; R L = 150 Ω; AV = +3.
Specifications subject to change without notice.
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–3–
55
190
150
40
0
0
0
0
0.1
0.5
–86
–67
–51
–83
–69
–54
1.2
29
+25°C V
POWER SUPPLY REQUIREMENTS
Quiescent Current
+IS
–IS
REV. B
190
150
40
0
0
0
0
0.1
0.5
–86
–67
–51
–83
–69
–54
1.2
29
Units
1100 1400
48
48
34
34
1100
50
2
<0 .01
0.01
48
48
34
34
ns
ns
%
Degree
48
48
mA
mA
AD9617
EXPLANATION OF TEST LEVELS
Test Level
DIE CONNECTIONS
+VS
I - 100% production tested.
II - 100% production tested at +25°C and sample tested at
specified temperatures. AC testing of J grade devices done
on sample basis.
III - Sample tested only.
IV - Parameter is guaranteed by design and characterization
testing.
V - Parameter is a typical value only.
VI - All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature extremes for commercial/industrial devices.
+VS
–INPUT
TOP VIEW
(Not to Scale)
OUTPUT
+INPUT
–VS
–VS
DIE SIZE = 53 3 67 3 15 mils
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
AD9617JN
AD9617JR
AD9617JR-REEL
0°C to +70°C
0°C to +70°C
0°C to +70°C
Plastic DIP
SOIC
13" Tape and Reel
N-8
SO-8
SO-8
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–4–
REV. B
AD9617
Typical Performance Characteristics (A = +3; 6V = 65 V; R = 400 V, unless otherwise noted)
V
3
F
180
10
135
15
1
90
20
0
45
–1
0
–2
–45
–3
–90
40
–4
–135
45
–5
–180
50
AV = +5
AV = +1
PHASE – Degrees
25
30
dB
MAGNITUDE – dB
2
S
–6
–7
35
CMRR
55
PSRR
AV = +20
0
40
80
120
FREQUENCY – MHz
160
60
100
200
Figure 1. Noninverting Frequency Response
AV = –5
1
180
0.1
135
0.08
90
0.06
MAGNITUDE – dB
AV = –1
SETTLING PERCENTAGE – %
2
0
45
–1
0
–2
–45
–3
–90
–4
–135
–5
–180
AV = –20
0
40
80
100V
120
160
0.02
0
–0.02
–0.04
VOUT = 4V STEP
–0.06
–0.1
200
0
8
16
90
60
75
90
PHASE
60
120
TEST CIRCUIT
150
180
100V
6pF
0.02
0
–0.02
–0.04
–0.06
–0.1
0
1G
2
4
6
8
TIME – ms
Figure 3. Open Loop Transimpedance Gain
[T(s) Relative to 1 Ω]
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100V
0.04
–0.08
240
100M
0.06
VOUT = 4V STEP
210
15
TEST CIRCUIT
0.08
SETTLING PERCENTAGE – %
30
RELATIVE PHASE – Degrees
GAIN – dB
105
REV. B
40
0.1
0
1M
10M
FREQUENCY – Hz
32
Figure 5. Settling Time
GAIN
100k
24
TIME – ms
120
0
10k
6pF
0.04
Figure 2. Inverting Frequency Response
30
100M
TEST CIRCUIT
FREQUENCY – MHz
45
10M
–0.08
–6
–7
10k
100k
1M
FREQUENCY – Hz
Figure 4. CMRR and PSRR
PHASE – Degrees
3
1k
Figure 6. Long Term Settling Time
–5–
10
AD9617
40
50
VOUT = 2V p-p
= 2ND HARMONIC
= 3RD HARMONIC
50V
INTERCEPT – +dBm
50
–dBc
60
70
100V LOAD
500V LOAD
80
TEST
CIRCUIT
40
50V
30
90
100
0
2
4
6 8 10
20
FREQUENCY – MHz
40
60
20
100
0
MAGNITUDE – dB
RL = 500V
2.5
135
2.0
90
1.5
0
45
–1
0
–2
–45
–3
–90
–4
–135
RL = 50V
ANALOG INPUT – Volts
RL = 100V
180
PHASE – Degrees
3
1
–180
–5
120
150
AV = +3
1.0
0.5
0
TEST CIRCUIT
100V
6pF
–0.5
–1.0
–1.5
–2.0
–6
–7
60
90
FREQUENCY – MHz
Figure 10. Intermodulation Distortion (IMD)
Figure 7. Harmonic Distortion
2
30
AV = –3
–2.5
0
40
80
120
FREQUENCY – MHz
160
200
10ns/DIV
Figure 8. Frequency Response vs. RLOAD
115
Figure 11. Large Signal Pulse Response
7
AV = +3
100
6
70
4
nV/ Hz
5
85
pA/ Hz
ANALOG INPUT – Volts
pA/ Hz
(INVERTING)
nV/ Hz
55
3
40
1.0
0.5
0
TEST CIRCUIT
100V
6pF
–0.5
–1.0
2
AV = –3
25
100
1k
10k
FREQUENCY – MHz
1
100k
10ns/DIV
Figure 9. Equivalent Input Noise
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Figure 12. Small Signal Pulse Response
–6–
REV. B
AD9617
THEORY OF OPERATION
The AD9617 has been designed to combine the key attributes of
traditional “low frequency” precision amplifiers with exceptional
high frequency characteristics that are independent of closedloop gain. Previous “high frequency” closed-loop amplifiers have
low open loop gain relative to precision amplifiers. This results
in relatively poor dc nonlinearity and precision, as well as excessive high frequency distortion due to open loop gain roll-off.
Operational amplifiers use two basic types of feedback correction, each with advantages and disadvantages. Voltage feedback
topologies exhibit an essentially constant gain bandwidth product. This forces the closed-loop bandwidth to vary inversely with
closed-loop gain. Moreover, this type design typically slew rate
limits in a way that causes the large signal bandwidth to be
much lower than its small signal characteristics.
A newer approach is to use current feedback to realize better
dynamic performance. This architecture provides two key attributes over voltage feedback configurations: (1) avoids slew
rate limiting and therefore large signal bandwidth can approach
small signal performance; and (2) low bandwidth variation versus gain settings, due to the inherently low open loop inverting
input resistance (RS).
The AD9617 uses a new current feedback topology that overcomes these limitations and combines the positive attributes of
both current feedback and voltage feedback designs. These
devices achieve excellent high frequency dynamics (slew, BW
and distortion) along with excellent low frequency linearity and
good dc precision.
The major difference lies in the front end architecture. A voltage
feedback amplifier has symmetrical high resistance (buffered)
inputs. A current feedback amplifier has a high noninverting
resistance (buffered) input and a low inverting (buffer output)
input resistance. The feedback mechanics can be easily developed using current feedback and transresistance open loop gain
T(s) to describe the I/O relationship. (See typical specification
chart.)
DC closed-loop gain for the AD9617 can be calculated using
the following equations:
G=
V O −RF / RI
≈
V I 1 + 1 / LG
inverting
(1)
G=
V O 1 + RF / RI
≈
VN
1 + 1 / LG
noninverting
(2)
where
RS ( RF + RS i RI )
1
≈
LG
T ( s )( RS i RI )
(3)
Because the noninverting input buffer is not ideal, input resistance RS (at dc) is gain dependent and is typically higher for
noninverting operation than for inverting operation. RS will
approach the same value (<7 Ω) for both at input frequencies
above 50 MHz. Below the open loop corner frequency, the
noninverting RS can be approximated as:
RS ( noninverting ) ≈ 7 +
T (s)
T
= 7+ O
AO
AO
(4)
dc
where: AO = Open Loop Voltage Gain < G × 600
DC GAIN CHARACTERISTICS
A simplified equivalent schematic is shown below. When operating the device in the inverting mode, the input signal error
current (IE) is amplified by the open loop transimpedance gain
(TO). The output signal generated is equal to TO × IE. Negative
feedback is applied through RF such that the device operates at a
gain (G) equal to –RF/RI.
Inverting RS below the open loop corner frequency can be approximated as:
Noninverting operation is similar, with the input signal applied
to the high impedance buffer (noninverting) input. As before, an
output (buffer) error current (IE) is generated at the low impedance inverting input. The signal generated at the output is fed
back to the inverting input such that the external gain is (l + RF/
RI). The feedback mechanics are identical to the voltage feedback topology when exact equations are used.
where: AO = 40,000.
RS ( inverting ) ≈ 7 +
T (s )
T
= 7+ O
AO
AO
(5)
dc
The AD9617 approaches this condition. With TO = 1 × 106 Ω,
RL = 500 Ω and RS = 25 Ω (dc), a gain error no greater than
0.05% typically results for G = –1 and 0.15% for G = –40.
Moreover, the architecture linearizes the open loop gain over its
operating voltage range and temperature resulting in ≥16 bits of
linearity.
RL = 100V
+
CC
LS
TO
VO
RS
RI
VI
CI
0%
ERROR RELATIVE TO FS
0.0002%/DIVISION
VN
IE
–
RF
–2
Figure 13. Equivalent Circuit
–1
0
1
VOUT – Volts
Figure 14. DC Nonlinearity vs. VOUT
REV. B
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–7–
2
AD9617
specified BW, the following equations can be used to approximate RF and RI for any gain from ± l to ± 15.
AC GAIN CHARACTERISTICS
Closed-loop bandwidth at high frequencies is determined primarily by the roll-off of T(s). But circuit layout is critical to
minimize external parasitics which can degrade performance by
causing premature peaking and/or reduced bandwidth.
RF = 424 ± 8 G
(+ for inverting and – for noninverting)
The inverting and noninverting dynamic characteristics are similar.
When driving the noninverting input, the inverting input capacitance (CI ) will cause the noninverting closed-loop bandwidth to
be higher than the inverting bandwidth for gains less than two
(2). In the remaining cases, inverting and noninverting responses
are nearly identical.

st1 +


RS 

RI 
(9)
RI ≈
424 + 8 G
G −1
(inverting)
(10)
The closed loop bandwidth can be reduced by increasing RF.
Equations 6 and 7 can be used to determine the closed loop
bandwidth for any value RF. Do not connect a feedback capacitor across RF, as this will degrade dynamic performance and
possibly induce oscillation.
DC Precision and Noise
Output offset voltage results from both input bias currents and
input offset voltage. These input errors are multiplied by the
noise gain term (1 + RF/RI) and algebraically summed at the
output as shown below.
+1
(6)


R 
R 
V O = V IO × 1 + F  ± IBn × RN × 1 + F  ± IBi × RF
RI 
RI 


where: t = RF × CC = 0.9 ns (RF = 400 Ω)
∆V O
Slew Rate ≈
× e −τ/ RF KCC
RF KCC
(noninverting)
(11)
Since the inputs are asymmetrical, IBi and IBn do not correlate.
Canceling their output effects by making RN = RFiRI will not
reduce output offset errors, as it would for voltage feedback
amplifiers. Typically, IBn is 5 µA and VIO is +0.5 mV (I sigma =
0.3 mV), which means that the dc output error can be reduced
by making RN ≈ 100 Ω. Note that the offset drift will not change
significantly because the IBn TC is relatively small. (See specification table.)
(7)
R
S
where: K = 1 + R
I
Increasing Bandwidth at Low Gains
By reducing RF, wider bandwidth and faster pulse response can
be attained beyond the specified values, although increased
overshoot, settling time and possible ac peaking may result. As a
rule of thumb, overshoot and bandwidth will increase by 1%
and 8%, respectively, for a 5% reduction in RF at gains of ± 10.
Lower gains will increase these sensitivities.
RF
RI
IBi
RN
IBn
VOUT
Figure 15. Output Offset Voltage
Equations 6 and 7 are simplified and do not accurately model
the second order (open loop) frequency response term which is
the primary contributor to overshoot, peaking and nonlinear
bandwidth expansion. (See Open Loop Bode Plots.) The user
should exercise caution when selecting RF values much lower
than 400 Ω. Note that a feedback resistor must be used in all
situations, including those in which the amplifier is used in a
noninverting unity gain configuration.
10
1.0
IBn
IBi/IBn – mA
5
Increasing Bandwidth at High Gains
Closed loop bandwidth can be extended at high closed loop gain
by reducing RF. Bandwidth reduction is a result of the feedback
current being split between RS and RI. As the gain increases (for
a given RF), more feedback current is shunted through RI, which
reduces closed loop bandwidth (see Equation 6). To maintain
0.5
VIO
0
0
VIO – mA
RF
RI
424 − 8 G
G −1
Bandwidth Reduction
Closed-Loop Gain vs. Frequency:
(noninverting operation)
1+
RI ≈
G = Closed Loop Gain.
For best overall dynamic performance, the value of the feedback
resistor (RF) should be 400 ohms. Although bandwidth reduces
as closed-loop gain increases, the change is relatively small due
to low equivalent series input impedance, ZS. (See typical
performance charts.) The simplified equations governing the
device’s dynamic performance are shown below.
VO
≈
VI
(8)
IBi
–0.5
–5
–10
–558C
258C
–1.0
1258C
Figure 16. DC Accuracy
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–8–
REV. B
AD9617
The effective noise at the output of the amplifier can be determined by taking the root sum of the squares of Equation 11 and
applying the spectral noise values found in the typical graph
section. This applies to noise from the op amp only. Note that
both the noise figure and equivalent input offset voltages improve as the closed loop gain is increased (by keeping RF fixed
and reducing RI with RN = 0 Ω).
The superior frequency and time domain specifications of the
AD9617 make it an obvious choice for driving flash converters
and buffering the outputs of high speed DACs. Its outstanding
distortion and noise performance make it well suited as a driver
for analog to digital converters (ADCs) with resolutions as high
as 16 bits.
Typical circuits for inverting and noninverting applications are
shown in Figures 20 and 21.
400V
RSERIES
In
APPLYING THE AD9617
Closed-loop gain for noninverting configurations is determined
by the value of RI according to the equation:
CLI
RL
500V
CL
G =1+
Figure 17. Capacitive Load Figure
RF
RI
(12)
Capacitive Load Considerations
+VS
3.3mF
Due to the low inverting input resistance (RS) and output buffer
design, the AD9617 can directly handle input and/or output
load capacitances of up to 20 pF. See the chart below.
0.1mF
0.1mF
SETTLING TIME TO 0.02% – ns
A small series resistor can be used at the output of the amplifier
and outside of the feedback loop to facilitate driving larger capacitive loads or for obtaining faster settling time. For capacitive
loads above 20 pF, RSERIES should be considered.
VIN
RIN
VOUT
AD9617
35
30
VOUT = 4V STEP
CL = 0pF
400V
VOUT = 4V STEP
CLI = 0pF
RI
0.1mF
25
0.1mF
20
3.3mF
15
–VS
10
5pF
Figure 20. Noninverting Operation
4pF/DIV
25pF 10pF
4pF/DIV
30pF
INPUT CAPACITANCE – CLI
INPUT CAPACITANCE – CL
RSERIES = 0V
+VS
3.3mF
Figure 18. Input/Output Capacitance Comparisons
0.1mF
0.1mF
25
20
VOUT
RSERIES – V
AD9617
15
VIN
10
RI
400V
RTERM
0.1mF
5
0.1mF
3.3mF
0
–VS
0
20
40
60
80
100
Figure 21. Inverting Operation
CL – pF
Figure 19. Recommended RSERIES vs. CL
REV. B
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–9–
AD9617
As with all high performance amplifiers, printed circuit layout is
critical in obtaining optimum results with the AD9617. The
ground plane in the area of the amplifier should cover as much
of the component side of the board as possible. Each power
supply trace should be decoupled close to the package with at
least a 3.3 µF tantalum and a low inductance, 0.1 µF ceramic
capacitor.
All lead lengths for input, output and the feedback resistor
should be kept as short as possible. All gain setting resistors
should be chosen for low values of parasitic capacitance and
inductance, i.e., microwave resistors and/or carbon resistors.
Stripline techniques should be used for lead lengths in excess of
one inch. Sockets should be avoided if possible because of their
stray inductance and capacitance.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C1353b–0–9/99
LAYOUT CONSIDERATIONS
Small Outline Package
(SO-8)
0.198 (5.00)
0.188 (4.74)
0.158 (4.00)
0.150 (3.80)
8
5
1
4
0.244 (6.200)
0.228 (5.80)
PIN 1
0.205 (5.20)
0.181 (4.60)
0.050 (1.27)
BSC
0.069 (1.75)
0.053 (1.35)
0.010 (0.25)
0.004 (0.10)
SEATING
PLANE
88
0.015 (0.38) 08
0.007 (0.18)
0.018 (0.46)
0.014 (0.36)
0.045 (1.15)
0.020 (0.50)
Plastic DIP
(N-8)
0.430 (10.92)
0.348 (8.84)
8
5
0.280 (7.11)
0.240 (6.10)
1
4
0.325 (8.25)
0.300 (7.62)
PIN 1
0.100 (2.54)
BSC
0.210
(5.33)
MAX
0.200 (5.05)
0.125 (3.18)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
08–158
0.015 (0.381)
0.008 (0.204)
PRINTED IN U.S.A.
0.022 (0.558) 0.070 (1.77) SEATING
0.014 (0.356) 0.045 (1.15) PLANE
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–10–
REV. B