2.5 V/3.3 V, 2:1 Multiplexer/ Demultiplexer Bus Switch ADG3249 FEATURES 225 ps Propagation Delay through the Switch 4.5 Switch Connection between Ports Data Rate 1.244 Gbps 2.5 V/3.3 V Supply Operation Selectable Level Shifting/Translation Level Translation 3.3 V to 2.5 V 3.3 V to 1.8 V 2.5 V to 1.8 V Small Signal Bandwidth 610 MHz 8-Lead SOT-23 Package FUNCTIONAL BLOCK DIAGRAM ADG3249 A0 B A1 CONTROL LOGIC IN EN APPLICATIONS 3.3 V to 1.8 V Voltage Translation 3.3 V to 2.5 V Voltage Translation 2.5 V to 1.8 V Voltage Translation Docking Stations Memory Switching Analog Switch Applications GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG3249 is a 2.5 V or 3.3 V, high performance 2:1 multiplexer/demultiplexer bus switch. It is designed on a low voltage CMOS process, which provides low power dissipation yet gives high switching speed and very low on resistance. This allows the input to be connected to the output without additional propagation delay or generating additional ground bounce noise. 1. 2. 3. 4. 3.3 V or 2.5 V supply operation. Extremely low propagation delay through switch. 4.5 Ω switches connect inputs to outputs. Tiny SOT-23 package. Each switch of the ADG3249 conducts equally well in both directions when on. The ADG3249 exhibits break-before-make switching action, preventing momentary shorting when switching channels. This device is ideal for applications requiring level translation. When operated from a 3.3 V supply, level translation from 3.3 V inputs to 2.5 V outputs is allowed. Similarly, if the device is operated from 2.5 V supply and 2.5 V inputs are applied, the device will translate the outputs to 1.8 V. In addition, a level translating pin (SEL) is included. When SEL is low, VCC is reduced internally, allowing for level translating between 3.3 V inputs and 1.8 V outputs. The ADG3249 is available in a tiny 8-lead SOT-23 package. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. ADG3249–SPECIFICATIONS1 Parameter Symbol DC ELECTRICAL CHARACTERISTICS Input High Voltage VINH VINH Input Low Voltage VINL VINL Input Leakage Current II OFF State Leakage Current IOZ ON State Leakage Current Maximum Pass Voltage VP CAPACITANCE3 A Port Off Capacitance B Port Off Capacitance A, B Port On Capacitance Control Input Capacitance SWITCHING CHARACTERISTICS3 Propagation Delay A to B or B to A, tPD4 Propagation Delay Matching5 Bus Enable Time EN to A or B6 Bus Disable Time EN to A or B6 Bus Enable Time EN to A or B6 Bus Disable Time EN to A or B6 Bus Enable Time EN to A or B6 Bus Disable Time EN to A or B6 Break-before-Make Time Transition Time On Resistance Matching POWER REQUIREMENTS VCC Quiescent Power Supply Current Increase in ICC per Input7 Conditions Min VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V 2.0 1.7 0 ≤ A, B ≤ VCC 0 ≤ A, B ≤ VCC VA/VB = VCC = SEL = 3.3 V, IO = –5 µA VA/VB = VCC = SEL = 2.5 V, IO= –5 µA VA/VB = VCC = 3.3 V, SEL = 0 V, IO = –5 µA CA OFF CB OFF CA, CB ON CIN, CSEL CEN f = 1 MHz; EN = VCC f = 1 MHz; EN = VCC f = 1 MHz f = 1 MHz f = 1 MHz tPHL, tPLH CL = 50 pF, VCC = SEL = 3 V tPZH, tPZL tPHZ, tPLZ tPZH, tPZL tPHZ, tPLZ tPZH, tPZL tPHZ, tPLZ tBBM tTRANS VCC = 3.0 V to 3.6 V; SEL = VCC VCC = 3.0 V to 3.6 V; SEL = VCC VCC = 3.0 V to 3.6 V; SEL = 0 V VCC = 3.0 V to 3.6 V; SEL = 0 V VCC = 2.3 V to 2.7 V; SEL = VCC VCC = 2.3 V to 2.7 V; SEL = VCC RL = 510 Ω, CL = 50 pF RL = 510 Ω, CL = 50 pF; SEL = VCC RL = 510 Ω, CL = 50 pF; SEL = 0 V VCC = SEL = 3.3 V; VA/VB = 2 V VCC = SEL = 3.3 V; VA/VB = 2 V RON VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA VCC = 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA VCC = 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA VCC = 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA VCC = 3 V, SEL = 0 V VA = 0 V, IBA = 8 mA VCC = 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA VCC = 3 V, SEL = VCC, VA = 0 V, IA = 8 mA VCC = 3 V, SEL = 0 V, VA = 0 V, IA = 8 mA Maximum Data Rate Channel Jitter DIGITAL SWITCH On Resistance (VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.) ⌬RON 2.0 1.5 1.5 B Version Typ2 Max ± 0.01 ± 0.01 ± 0.01 2.5 1.8 1.8 3.5 4.5 8.5 4 6.5 1 1 1 1 1 1 5 3.5 5.5 3.2 4.5 3.5 4 10 16 15 1.244 45 4.5 12 5 9 5 12 0.1 0.1 2.3 ICC ⌬ICC Digital Inputs = 0 V or VCC; SEL = VCC Digital Inputs = 0 V or VCC; SEL = 0 V VCC = 3.6 V, EN = 3.0 V; SEL = VCC; IN = VCC 0.8 0.7 ±1 ±1 ±1 2.9 2.1 2.1 0.01 0.1 0.15 Unit V V V V µA µA µA V V V pF pF pF pF pF 0.225 5 4.8 8.2 4.5 7.7 4.6 5.8 29 22 ns ps ns ns ns ns ns ns ns ns ns Gbps ps p-p 0.5 0.5 Ω Ω Ω Ω Ω Ω Ω Ω 3.6 1 0.2 8 V µA mA µA 8 28 9 18 8 NOTES 1 Temperature range is as follows: B Version: –40°C to +85°C. 2 Typical values are at 25°C, unless otherwise stated. 3 Guaranteed by design, not subject to production test. 4 The digital switch contributes no propagation delay other than the RC delay of the typical R ON of the switch and the load capacitance when driven by an ideal voltage source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 5 Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF. 6 See Timing Measurement Information section. 7 This current applies to the control pin EN only. The A and B ports contribute no significant ac or dc currents as they transition. Specifications subject to change without notice. –2– REV. 0 ADG3249 ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION 8-Lead SOT-23 (TA = 25°C, unless otherwise noted.) VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V DC Output Current . . . . . . . . . . . . . . . . . 25 mA per Channel Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 206°C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . . 235°C EN 1 A0 2 ADG3249 8 VCC 7 SEL TOP VIEW 6 IN A1 (Not to Scale) 4 5 B GND 3 Table I. Pin Function Descriptions *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. Pin No. Mnemonic Description 1 2 3 4 5 6 7 8 EN A0 A1 GND B IN SEL VCC Enable (Active Low) Port A0, Input or Output Port A1, Input or Output Ground Reference Port B, Input or Output Channel Select Level Translation Select Positive Power Supply Voltage Table II. Truth Table EN IN SEL* FUNCTION H L L L L X L L H H X L H L H Disconnect A0 = B; 3.3 V to 1.8 V Level Shifting A0 = B; 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting A1 = B; 3.3 V to 1.8 V Level Shifting A1 = B; 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting *SEL = 0 V only when VDD = 3.3 V 10% ORDERING GUIDE Model Temperature Range Package Description Package Branding ADG3249BRJ-R2 ADG3249BRJ-REEL ADG3249BRJ-REEL7 –40°C to +85°C –40°C to +85°C –40°C to +85°C SOT-23 (Small Outline Transistor Package) SOT-23 (Small Outline Transistor Package) SOT-23 (Small Outline Transistor Package) RJ-8 RJ-8 RJ-8 SHA SHA SHA CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG3249 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– ADG3249 TERMINOLOGY VCC GND VINH VINL II IOZ IOL VP RON ⌬RON CX OFF CX ON CIN, CSEL, CEN ICC ⌬ICC tPLH, tPHL tPZH, tPZL tPHZ, tPLZ tBBM tTRANS Max Data Rate Channel Jitter Positive Power Supply Voltage. Ground (0 V) Reference. Minimum Input Voltage for Logic 1. Maximum Input Voltage for Logic 0. Input Leakage Current at the Control Inputs. OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state. ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state. Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when the switch input voltage is equal to the supply voltage. Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified amount of current through the switch. ON Resistance Match between Any Two Channels, i.e., RON max to RON min. OFF Switch Capacitance. ON Switch Capacitance. Control Input Capacitance. This consists of IN, SEL, and EN. Quiescent Power Supply Current. This current represents the leakage current between the VCC and ground pins. It is measured when all control inputs are at a logic high or low level and the switches are OFF. Extra power supply current component for the EN control input when the input is not driven at the supplies. Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant RON × CL, where CL is the load capacitance. Bus Enable Times. These are the times taken to cross the VT voltage at the switch output when the switch turns on in response to the control signal, EN. Bus Disable Times. These are the time taken to place the switch in the high impedance OFF state in response to the control signal. They are measured as the time taken for the output voltage to change by V⌬ from the original quiescent level, with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.) On or Off Time. Measured between the 90% points of both switches when switching fom one to another. Time taken to switch from one channel to the other, measured from 50% of the IN signal to 90% of the OUT signal. Maximum Rate at which Data Can Be Passed through the Switch. Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel. –4– REV. 0 Typical Performance Characteristics–ADG3249 40 35 VCC = 2.3V TA = 25C SEL = VCC 35 30 30 VCC = 3.3V 20 15 RON () 25 VCC = 3V TA = 25C SEL = 0V 35 30 RON () RON () 40 40 VCC = 3V TA = 25C SEL = VCC 25 VCC = 2.5V 20 25 VCC = 3.3V 20 15 15 VCC = 3.6V VCC = 2.7V 10 VCC = 3.6V 5 0 0 0.5 1.0 2.0 1.5 VA/VB (V) 3.0 2.5 10 10 5 5 0 3.5 0 0 TPC 1. On Resistance vs. Input Voltage 1.0 0.5 2.0 1.5 VA/VB (V) 2.5 3.0 0 3.0 15 VCC = 3.3V 1.0 TA = 25C SEL = VCC IO = –5A VCC = 2.5V SEL = VCC 1.5 2.0 VA/VB (V) 2.5 3.0 3.5 TPC 3. On Resistance vs. Input Voltage TPC 2. On Resistance vs. Input Voltage 20 0.5 SEL = VCC 2.5 VCC = 3.6V 15 10 85C VOUT (V) RON () RON () 10 85C VCC = 3.3V VCC = 3V 1.5 1.0 5 5 2.0 40C 25C 25C 0.5 40C 0 1.0 VA/VB (V) 0.5 0 2.0 1.5 TPC 4. On Resistance vs. Input Voltage for Different Temperatures 0.5 VA/VB (V) 1.2 1.0 TPC 5. On Resistance vs. Input Voltage for Different Temperatures TA = 25C SEL = VCC IO = –5A 2.0 1.5 VCC = 2.5V VCC = 2.3V 1.0 0.5 1.0 2.0 1.5 VA/VB (V) 2.5 3.0 3.5 300 TA = 25C SEL = 0V IO = –5A VCC = 2.7V VOUT (V) 2.0 0 TPC 6. Pass Voltage vs. VCC 2.5 2.5 VOUT (V) 0 0 TA = 25C VCC = 3.6V 250 VCC = SEL = 3.3V 200 VCC = 3.3V SEL = 0V 1.5 VCC = 3.3V VCC = 3V 1.0 ICC (A) 0 150 100 0.5 0.5 50 0 0 0.5 1.0 1.5 2.0 VA/VB (V) 2.5 TPC 7. Pass Voltage vs. VCC REV. 0 3.0 0 0 0.5 1.0 1.5 2.0 VA/VB (V) 2.5 3.0 TPC 8. Pass Voltage vs. VCC –5– 3.5 0 VCC = SEL = 2.5V 0 5 10 15 20 25 30 35 40 45 50 ENABLE FREQUENCY (MHz) TPC 9. ICC vs. Enable Frequency ADG3249 3.0 3.0 TA = 25C VA = 0V EN = 0 2.5 1.5 VCC = SEL = 3.3V 1.0 0.02 0.04 0.06 IO (A) 0.08 –0.08 –0.06 –0.04 IO (A) –0.02 0 –1.4 –2 –40 –3 –20 –30 –40 –6 –7 –8 0.03 0.1 –60 –70 –70 –80 –80 –90 1.0 10 100 FREQUENCY (MHz) 1000 TPC 13. Bandwidth vs. Frequency –90 –100 0.03 0.1 1.0 10 100 FREQUENCY (MHz) 1000 4.0 3.5 VCC = SEL = 3.3V 3 TIME (ns) ENABLE VCC = 3.3V, SEL = 0V ENABLE 2.5 VCC = SEL = 3.3V 90 V = 1.5V p-p IN 80 20dB ATTENUATION VCC = SEL = 2.5V ENABLE 2.0 1.5 70 60 50 40 30 1.0 1 1000 100 DISABLE 3.0 DISABLE 1.0 10 100 FREQUENCY (MHz) TPC 15. Off Isolation vs. Frequency JITTER (ps p-p) DISABLE –100 0.03 0.1 TPC 14. Crosstalk vs. Frequency 6 3.5 –50 –60 TA = 25C VCC = 3.3V/2.5V SEL = VCC VIN = 0dBm N/W ANALYZER: RL = RS = 50 –5 3.0 TA = 25C VCC = 3.3V/2.5V SEL = VCC VIN = 0dBm N/W ANALYZER: RL = RS = 50 –10 –50 –4 1.5 2.0 2.5 VA/VB (V) TPC 12. Charge Injection vs. Source Voltage ATTENUATION (dB) ATTENUATION (dB) –30 1.0 0 TA = 25C VCC = 3.3V/2.5V SEL = VCC VIN = 0dBm N/W ANALYZER: RL = RS = 50 –20 –1 0.5 0 0 –10 0 ATTENUATION (dB) –1.2 TPC 11. Output High Characteristic 1 2 VCC = 3.3V 0 –0.10 0.10 TPC 10. Output Low Characteristic 4 –1.0 VCC = 3.3V; SEL = 0V VCC = SEL = 2.5V 0 TIME (ns) –0.8 0.5 0 VCC = 2.5V –0.6 1.5 1.0 V = SEL = 2.5V CC 0.5 5 –0.4 VCC = SEL = 3.3V 2.0 VCC = 3.3V; SEL = 0V VOUT (V) VOUT (V) 2.0 TA = 25C SEL = VCC ON = OFF CL = INF. –0.2 QINJ (pC) 2.5 0 TA = 25C VA = VCC EN = 0 20 0.5 10 0 –40 –20 20 40 0 TEMPERATURE (C) 60 80 TPC 16. Enable/Disable Time vs. Temperature 0 –40 –20 20 40 0 TEMPERATURE (C) 60 80 TPC 17. Enable/Disable Time vs. Temperature –6– 0 0.5 0.7 0.9 1.1 1.3 1.5 1.7 DATA RATE (Gbps) 1.9 TPC 18. Jitter vs. Data Rate; PRBS 31 REV. 0 ADG3249 EYE WIDTH (%) 100 95 VCC = SEL = 3.3V 90 V = 1.5V p-p IN 85 20dB ATTENUATION 80 75 70 65 38.7mV/DIV 133.7ps/DIV 60 55 % EYE WIDTH = ((CLOCK PERIOD – JITTER p-p)/CLOCK PERIOD) 100% 50 0.5 0.7 0.9 1.1 1.3 1.5 1.7 DATA RATE (Gbps) 1.9 VCC = 3.3V SEL = 3.3V VIN = 2V p-p TPC 20. Eye Pattern; 1.244 Gbps, VCC = 3.3 V, PRBS 31 TPC 19. Eye Width vs. Data Rate; PRBS 31 REV. 0 20dB ATTENUATION TA = 25C –7– 20mV/DIV 166.3ps/DIV VCC = 2.5V SEL = 2.5V VIN = 1V p-p 20dB ATTENUATION TA = 25C TPC 21. Eye Pattern; 1 Gbps, VCC = 2.5 V, PRBS 31 ADG3249 TIMING MEASUREMENT INFORMATION For the following load circuit and waveforms, the notation that is used is VIN and VOUT where VIN = VA and VOUT = VB or VIN = VB and VOUT = VA VCC PULSE GENERATOR CONTROL INPUT EN GND RL VOUT VIN VIH 2 VCC SW1 VT tPLH tPLH VH VT VOUT DUT 0V VL RL CL RT Figure 2. Propagation Delay NOTES PULSE GENERATOR FOR ALL PULSES: tR 2 .5 n s , t F 2.5ns, FREQUENCY 10MHz. CL INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES. RT IS THE TERMINATION RESISTOR, SHOULD BE EQUAL TO ZOUT OF THE PULSE GENERATOR. Figure 1. Load Circuit Test Conditions Symbol VCC = 3.3 V ± 0.3 V (SEL = VCC) VCC = 2.5 V ± 0.2 V (SEL = VCC) VCC = 3.3 V ± 0.3 V (SEL = 0 V) Unit RL V⌬ CL VT 500 300 50 1.5 500 150 30 0.9 500 150 30 0.9 Ω mV pF V DISABLE ENABLE VINH VT CONTROL INPUT EN Table III. Switch Position 0V tPZL VIN = 0V VOUT SW1 @ 2VCC tPLZ VCC VCC VT VL + V VL tPZH VIN = VCC VOUT SW1 @ GND Test S1 tPLZ, tPZL tPHZ, tPZH 2 × VCC GND tPHZ VH VT 0V VH – V 0V Figure 3. Enable and Disable Times –8– REV. 0 ADG3249 BUS SWITCH APPLICATIONS Mixed Voltage Operation, Level Translation 2.5 V to 1.8 V Translation When VCC is 2.5 V (SEL = 2.5 V) and the input signal range is 0 V to VCC, the maximum output signal will, as before, be clamped to within a voltage threshold below the VCC supply. In this case, the output will be limited to approximately 1.8 V, as shown in Figure 8. Bus switches can provide an ideal solution for interfacing between mixed voltage systems. The ADG3249 is suitable for applications where voltage translation from 3.3 V technology to a lower voltage technology is needed. This device can translate from 2.5 V to 1.8 V, or bidirectionally from 3.3 V directly to 2.5 V. 2.5V Figure 4 shows a block diagram of a typical application in which a user needs to interface between a 3.3 V ADC and a 2.5 V microprocessor. The microprocessor may not have 3.3 V tolerant inputs, therefore placing the ADG3249 between the two devices allows the devices to communicate easily. The bus switch directly connects the two blocks, thus introducing minimal propagation delay, timing skew, or noise. ADG3249 2.5V 1.8V Figure 7. 2.5 V to 1.8 V Voltage Translation, SEL = 2.5 VCC 2.5V 3.3V ADG3249 VOUT 3.3V ADC 2.5V MICROPROCESSOR 1.8V Figure 4. Level Translation between a 3.3 V ADC and a 2.5 V Microprocessor 0V 3.3 V to 2.5 V Translation When VCC is 3.3 V (SEL = 3.3 V) and the input signal range is 0 V to VCC, the maximum output signal will be clamped to within a voltage threshold below the VCC supply. In this case, the output will be limited to 2.5 V, as shown in Figure 6. This device can be used for translation from 2.5 V to 3.3 V devices and also between two 3.3 V devices. SWITCH INPUT VIN 2.5V Figure 8. 2.5 V to 1.8 V Voltage Translation, SEL = VCC 3.3 V to 1.8 V Translation The ADG3249 offers the option of interfacing between a 3.3 V device and a 1.8 V device. This is possible through use of the SEL pin. The SEL pin is an active low control pin. SEL activates internal circuitry in the ADG3242 that allows voltage translation between 3.3 V devices and 1.8 V devices. 3.3V 3.3V 2.5V SUPPLY SEL = 2.5V SWITCH OUTPUT 3.3V When VCC is 3.3 V and the input signal range is 0 V to VCC, the maximum output signal will be clamped to 1.8 V, as shown in Figure 9. To do this, the SEL pin must be tied to Logic 0. If SEL is unused, it should be tied directly to VCC. 2.5V ADG3249 2.5V 2.5V 3.3V Figure 5. 3.3 V to 2.5 V Voltage Translation, SEL = VCC ADG3249 3.3V VOUT 1.8V 3.3V SUPPLY SEL = 3.3V SWITCH OUTPUT 2.5V 0V Figure 9. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V SWITCH INPUT VIN VOUT 3.3V 3.3V SUPPLY SEL = 0V 1.8V SWITCH OUTPUT Figure 6. 3.3 V to 2.5 V Voltage Translation, SEL = VCC 0V SWITCH INPUT VIN 3.3V Figure 10. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V REV. 0 –9– ADG3249 MEMORY ADDRESS Analog Switching Bus switches can be used in many analog switching applications, for example, video graphics. Bus switches can have lower on resistance, smaller ON and OFF channel capacitance, and thus improved frequency performance than their analog counterparts. The bus switch channel itself, consisting solely of an NMOS switch, limits the operating voltage (see TPC 1 for a typical plot), but in many cases, this does not present an issue. MEMORY BANK A DATA MEMORY BANK B MEMORY BANK C Multiplexing MEMORY BANK D Many systems, such as docking stations and memory banks, have a large number of common bus signals. Common problems faced by designers of these systems include Large delays caused by capacitive loading of the bus • Noise due to simultaneous switching of the address and data bus signals Figure 11 shows an array of memory banks in which each address and data signal is loaded by the sum of the individual loads. If a bus switch is used as shown in Figure 12, the output load on the memory address and data bits is halved. The speed at which the selected bank’s data can flow is much improved because the capacitance loading is halved and the switches introduce negligible propagation delay. Bus noise is also reduced. High Impedance during Power-Up/Power-Down MEMORY ADDRESS MEMORY BANK A MEMORY BANK B ADG3249 • ADG3249 Figure 11. All Memory Banks Are Permanently Connected to the Bus DATA MEMORY BANK C MEMORY BANK D Figure 12. ADG3249 Used to Reduce Both Access Time and Noise To ensure the high impedance state during power-up or powerdown, EN should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the currentsinking capability of the driver. –10– REV. 0 ADG3249 OUTLINE DIMENSIONS 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters 2.90 BSC 8 7 6 5 1 2 3 4 1.60 BSC 2.80 BSC PIN 1 0.65 BSC 1.30 1.15 0.90 1.95 BSC 1.45 MAX 0.15 MAX 0.38 0.22 SEATING PLANE 0.22 0.08 8 4 0 COMPLIANT TO JEDEC STANDARDS MO-178BA REV. 0 –11– 0.60 0.45 0.30 –12– C04403–0–10/03(0)