AD ADG824BCPZ-REEL

0.5 Ω CMOS 1.65 V to 3.6 V Dual
SPDT/2:1 Mux in Mini LFCSP Package
ADG824
FEATURES
FUNCTIONAL BLOCK DIAGRAM
0.5 Ω typical on resistance
0.7 Ω maximum on resistance at 85°C
1.65 V to 3.6 V operation
High current carrying capability: 300 mA continuous
Rail-to-rail switching operation
Fast switching times <20 ns
Typical power consumption (<0.1 μW)
1.3 mm × 1.6 mm mini LFCSP package
ADG824
S1A
D1
S1B
IN1
IN2
S2A
D2
APPLICATIONS
Cellular phones
PDAs
MP3 players
Power routing
Battery-powered systems
PCMCIA cards
Modems
Audio and video signal routing
Communication systems
SWITCHES SHOWN FOR A LOGIC 1 INPUT
06693-001
S2B
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG824 is a low voltage CMOS device containing two
independently selectable single-pole, double throw (SPDT)
switches. This device offers ultralow on resistance of less than
0.7 Ω over the full temperature range. The ADG824 is fully
specified for 3.3 V, 2.5 V, and 1.8 V supply operation.
1.
<0.7 Ω over the full temperature range of –40°C to +85°C.
2.
Single 1.65 V to 3.6 V operation.
3.
1.8 V logic compatible.
4.
High current carrying capability (300 mA continuous
current at 3.3 V).
5.
Low THD + N (0.06% typical).
6.
1.3 mm × 1.6 mm mini LFCSP package.
Each switch conducts equally well in both directions when on,
and has an input signal range that extends to the supplies. The
ADG824 exhibits break-before-make switching action.
The low on resistance of the ADG824 makes this device ideal
for audio switching. In addition, a data rate of 180 Mbps makes
the device suitable for USB low speed (1.5 Mbps) and full speed
(12 Mbps) data switching.
The ADG824 is available in a 1.3 mm × 1.6 mm, 10-lead mini
LFCSP package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADG824
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................6
Applications....................................................................................... 1
Pin Configuration and Function Descriptions..............................7
Functional Block Diagram .............................................................. 1
Typical Performance Characteristics ..............................................8
General Description ......................................................................... 1
Test Circuits..................................................................................... 11
Product Highlights ........................................................................... 1
Terminology .................................................................................... 13
Revision History ............................................................................... 2
Outline Dimensions ....................................................................... 14
Specifications..................................................................................... 3
Ordering Guide .......................................................................... 14
Absolute Maximum Ratings............................................................ 6
REVISION HISTORY
4/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADG824
SPECIFICATIONS
VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between
Channels, ∆RON
On Resistance Flatness, RFLAT (ON)
+25°C
0.5
0.65
0.003
−40°C to +85°C
Unit
0 to VDD
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
0.7
0.01
0.13
0.2
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
tON
±0.2
±0.2
nA typ
nA typ
VDD = 2.7 V, VS = 0 V to VDD, IDS = 100 mA
VDD = 3.6 V
VS = 0.6 V/3.3 V, VD = 3.3 V/0.6 V; see Figure 20
VS = VD = 0.6 V or 3.3 V; see Figure 21
±0.1
μA typ
μA max
pF typ
VIN = VINL or VINH
VIN = VINL or VINH
RL = 50 Ω, CL = 35 pF
VS = 2 V/0 V; see Figure 22
RL = 50 Ω, CL = 35 pF
VS = 2 V; see Figure 22
RL = 50 Ω, CL = 35 pF
VS1 = VS2 = 2 V; see Figure 23
VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 24
RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 25
S1A to S2A/S1B to S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz;
see Figure 26
S1A to S1B/S2A to S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz;
see Figure 27
RL = 33 Ω, f = 20 Hz to 20 kHz, VS = 2 V p-p
RL = 50 Ω, CL = 5 pF; see Figure 28
RL = 50 Ω, CL = 5 pF; see Figure 28
0.005
2.7
Break-Before-Make Time Delay, tBBM
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
27
−71
−90
−67
dB typ
0.06
−0.05
90
25
58
%
dB typ
MHz typ
pF typ
pF typ
0.003
μA typ
μA max
10.8
8.6
2
1
1
VDD = 2.7 V, VS = 0.65 V, IDS = 100 mA
V min
V max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
Total Harmonic Distortion, THD + N
Insertion Loss
−3 dB Bandwidth
CS (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD
VDD = 2.7 V, VS = 0 V to VDD, IDS = 100 mA; see Figure 19
1.3
0.8
7
9.5
6
7.7
3.5
tOFF
Test Conditions/Comments
Guaranteed by design; not subject to production test.
Rev. 0 | Page 3 of 16
VDD = 3.6 V
Digital inputs = 0 V or 3.6 V
ADG824
VDD = 2.5 V ± 0.2 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between
Channels, ∆RON
On Resistance Flatness, RFLAT (ON)
+25°C
0.65
0.78
0.005
−40°C to +85°C
Unit
0 to VDD
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
0.83
0.01
0.2
0.3
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
tON
±0.2
±0.2
nA typ
nA typ
VDD = 2.3 V, VS = 0 V to VDD, IDS = 100 mA
VDD = 2.7 V
VS = 0.6 V/2.4 V, VD = 2.4 V/0.6 V; see Figure 20
VS = VD = 0.6 V or 2.4 V; see Figure 21
±0.1
μA typ
μA max
pF typ
VIN = VINL or VINH
VIN = VINL or VINH
RL = 50 Ω, CL = 35 pF
VS = 1.5 V/0 V; see Figure 22
RL = 50 Ω, CL = 35 pF
VS = 1.5 V; see Figure 22
RL = 50 Ω, CL = 35 pF
VS1 = VS2 = 1.5 V; see Figure 23
VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 24
RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 25
S1A to S2A/S1B to S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz;
see Figure 26
S1A to S1B/S2A to S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz;
see Figure 27
RL = 33 Ω, f = 20 Hz to 20 kHz, VS = 1.5 V p-p
RL = 50 Ω, CL = 5 pF; see Figure 28
RL = 50 Ω, CL = 5 pF; see Figure 28
0.005
2.7
Break-Before-Make Time Delay, tBBM
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
21
−71
−90
−71
dB typ
0.1
−0.065
90
25
60
%
dB typ
MHz typ
pF typ
pF typ
0.003
μA typ
μA max
12.4
8
3
1
1
VDD = 2.3 V, VS = 0.7 V, IDS = 100 mA
V min
V max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
Total Harmonic Distortion, THD + N
Insertion Loss
–3 dB Bandwidth
CS (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD
VDD = 2.3 V, VS = 0 V to VDD, IDS = 100 mA; see Figure 19
1.3
0.7
9
11.5
6
7.4
5
tOFF
Test Conditions/Comments
Guaranteed by design; not subject to production test.
Rev. 0 | Page 4 of 16
VDD = 2.7 V
Digital inputs = 0 V or 2.7 V
ADG824
VDD = 1.65 V to 1.95 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between
Channels, ∆RON
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
tON
+25°C
1.3
1.7
2.5
0.01
−40°C to +85°C
Unit
0 to VDD
V
Ω typ
Ω max
Ω max
Ω typ
2.1
3
±0.2
±0.2
nA typ
nA typ
VDD = 1.95 V
VS = 0.6 V/1.65 V, VD = 1.65 V/0.6 V; see Figure 20
VS = VD = 0.6 V or 1.65 V; see Figure 21
±0.1
μA typ
μA max
pF typ
VIN = VINL or VINH
VIN = VINL or VINH
RL = 50 Ω, CL = 35 pF
VS = 1.2 V/0 V; see Figure 22
RL = 50 Ω, CL = 35 pF
VS = 1.2 V; see Figure 22
RL = 50 Ω, CL = 35 pF
VS1 = VS2 = 1.2 V; see Figure 23
VS = 1 V, RS = 0 Ω, CL = 1 nF; see Figure 24
RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 25
S1A to S2A/S1B to S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz;
see Figure 26
S1A to S1B/S2A to S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz;
see Figure 27
RL = 33 Ω, f = 20 Hz to 20 kHz, VS = 1.2 V p-p
RL = 50 Ω, CL = 5 pF; see Figure 28
RL = 50 Ω, CL = 5 pF; see Figure 28
0.005
2.7
Break-Before-Make Time Delay, tBBM
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
15
−71
−90
−71
dB typ
0.4
−0.1
90
26
61
%
dB typ
MHz typ
pF typ
pF typ
0.003
μA typ
μA max
19.3
10.2
5
1
1
VDD = 1.65 V, VS = 0 V to VDD, IDS = 100 mA; see Figure 19
VDD = 1.65 V, VS = 0.7 V, IDS = 100 mA
V min
V max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
Total Harmonic Distortion, THD + N
Insertion Loss
–3 dB Bandwidth
CS (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD
VDD = 1.8 V, VS = 0 V to VDD, IDS = 100 mA; see Figure 19
0.65 VDD
0.35 VDD
13
18.6
7
9.8
7.5
tOFF
Test Conditions/Comments
Guaranteed by design; not subject to production test.
Rev. 0 | Page 5 of 16
VDD = 1.95 V
Digital inputs = 0 V or 1.95 V
ADG824
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
VDD to GND
Analog Inputs 1
Digital Inputs1
Peak Current, Sx or Dx Pins
3.3 V Operation
2.5 V Operation
1.8 V Operation
Continuous Current, Sx or Dx Pins
3.3 V Operation
2.5 V Operation
1.8 V Operation
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Mini LFCSP Package
θJA Thermal Impedance
(4-Layer Board)
Reflow Soldering (Pb-Free)
Peak Temperature
Time at Peak Temperature
1
Rating
−0.3 V to +4.6 V
−0.3 V to VDD + 0.3 V
−0.3 V to +4.6 V or 10 mA,
whichever occurs first
Pulsed at 1 ms,
10% duty cycle max
500 mA
460 mA
420 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating may be applied at any
one time.
ESD CAUTION
300 mA
275 mA
250 mA
−40°C to +85°C
−65°C to +150°C
150°C
131.6°C/W
260°C
10 sec to 40 sec
Overvoltages at the INx, Sx, or Dx pins are clamped by internal diodes.
Current should be limited to the maximum ratings given.
Rev. 0 | Page 6 of 16
ADG824
9 S2A
10 GND
1 S1A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
7 S2B
VDD 6
IN1 4
8 D2
06693-012
ADG824
TOP VIEW
(Not to Scale)
IN2 5
D1 2
S1B 3
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
S1A
D1
S1B
IN1
IN2
VDD
S2B
D2
S2A
GND
Description
Source Terminal. This pin can be an input or an output.
Drain Terminal. This pin can be an input or an output.
Source Terminal. This pin can be an input or an output.
Logic Control Input. This pin controls Switch S1A and Switch S1B to D1.
Logic Control Input. This pin controls Switch S2A and Switch S2B to D2.
Most Positive Power Supply Potential.
Source Terminal. This pin can be an input or an output.
Drain Terminal. This pin can be an input or an output.
Source Terminal. This pin can be an input or an output.
Ground (0 V) Reference.
Table 6. ADG824 Truth Table
Logic (IN1/IN2)
0
1
Switch A (S1A or S2A)
Off
On
Switch B (S1B or S2B)
On
Off
Rev. 0 | Page 7 of 16
ADG824
TYPICAL PERFORMANCE CHARACTERISTICS
0.6
0.6
TA = 25ºC
0.4
0.3
0.2
0.1
TA = +25ºC
0.4
0.3
TA = –40ºC
0.2
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VD, VS (V)
0
0
1.5
2.0
2.5
3.0
3.5
Figure 6. On Resistance vs. VD (VS) for Different
Temperatures, VDD = 3.3 V
0.7
0.7
VDD = 2.5V
VDD = 2.3V
0.6
1.0
VD, VS (V)
Figure 3. On Resistance vs. VD (VS), VDD = 3.3 V ± 0.3 V
TA = 25ºC
0.5
06693-023
0.1
06693-020
0
TA = +85ºC
0.5
VDD = 3V
VDD = 3.3V
VDD = 3.6V
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
0.5
VDD = 3.3V
VDD = 2.5V
TA = +85ºC
TA = +25ºC
0.6
ON RESISTANCE (Ω)
0.4
0.3
0.2
0.1
0.4
TA = –40ºC
0.3
0.2
0
0.5
1.0
1.5
2.0
2.5
3.0
VD, VS (V)
0
0
1.5
2.0
2.5
3.0
2.0
Figure 7. On Resistance vs. VD (VS) for Different
Temperatures, VDD = 2.5 V
1.8
1.6
TA = 25ºC
VDD = 1.8V
1.6
VDD = 1.65V
TA = –40°C
1.4
1.4
ON RESISTANCE (Ω)
1.2
1.2
VDD = 1.8V
1.0
VDD = 1.95V
0.8
0.6
TA = +25°C
1.0
TA = +85°C
0.8
0.6
0.4
0.4
0.2
0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
VD, VS (V)
2.0
06693-022
ON RESISTANCE (Ω)
1.0
VD, VS (V)
Figure 4. On Resistance vs. VD (VS), VDD = 2.5 V ± 0.2 V
0
0.5
06693-024
0.1
06693-021
0
0.5
06693-025
ON RESISTANCE (Ω)
VDD = 2.7V
0.5
Figure 5. On Resistance vs. VD (VS), VDD = 1.8 V ± 0.15 V
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VD, VS (V)
Figure 8. On Resistance vs. VD (VS) for Different
Temperatures, VDD = 1.8 V
Rev. 0 | Page 8 of 16
1.8
ADG824
6
40
VDD = 3.3V
TA = 25°C
35
5
ID, IS (ON) + +
ID, IS (OFF) + –
25
3
QINJ (pC)
CURRENT (nA)
VDD = 3.3V
30
4
ID, IS (ON) – –
2
VDD = 2.5V
20
15
VDD = 1.8V
1
10
0
0
10
20
30
40
50
60
TEMPERATURE (°C)
70
80
90
0
06693-028
–1
0
1
2
06693-014
5
ID, IS (OFF) – +
3
VS (V)
Figure 12. Charge Injection vs. Source Voltage
Figure 9. Leakage Current vs. Temperature, VDD = 3.3 V
16
4.5
VDD = 2.5V
4.0
14
ID, IS (ON) + +
3.0
ID, IS (OFF) + –
2.5
ID, IS (ON) – –
2.0
tON (1.8V)
12
TIME (ns)
10
tON (3.3V)
tON (2.7V)
8
6
tOFF (1.8V)
tOFF (2.7V)
1.5
4
1.0
ID, IS (OFF) – +
10
20
30
40
50
60
70
80
90
TEMPERATURE (°C)
0
–60
06693-017
0
–40
–20
0
20
40
60
80
100
06693-019
0.5
0
tOFF (3.3V)
2
1000
06693-016
CURRENT (nA)
3.5
TEMPERATURE (°C)
Figure 10. Leakage Current vs. Temperature, VDD = 2.5 V
Figure 13. tON/tOFF Times vs. Temperature
4
2
VDD = 1.8V
ID, IS (ON) + +
0
–2
INSERTION LOSS (dB)
ID, IS (ON) – –
2
1
0
–4
–6
–8
–10
–12
–14
ID, IS (OFF) + –
ID, IS (OFF) – +
0
10
20
30
40
50
60
TEMPERATURE (°C)
70
80
90
06693-027
CURRENT (nA)
3
Figure 11. Leakage Current vs. Temperature, VDD = 1.8 V
–16
0.1
TA = 25°C
VDD = 3.3V, 2.5V, 1.8V
1
10
FREQUENCY (MHz)
Figure 14. Bandwidth
Rev. 0 | Page 9 of 16
100
ADG824
0
–10
0.30
TA = 25°C
VDD = 3.3V, 2.5V, 1.8V
0.25
VDD = 1.8V
VS = 1.2V p-p
VDD = 2.5V
VS = 1.5V p-p
VDD = 3.3V
VS = 2V p-p
0.20
–30
THD + N (%)
–40
–50
0.15
0.10
–60
–70
1
10
100
1000
FREQUENCY (MHz)
0
100
06693-015
–80
0.1
100k
Figure 17. Total Harmonic Distortion + Noise vs. Frequency
20
0
TA = 25°C
VDD = 3.3V, 2.5V, 1.8V
TA= 25°C
VDD = 3.3V
S1A TO S1B
0
–20
–30
–20
–40
PSRR (dB)
S1A TO S2A
–50
–60
–40
–60
–70
–80
–80
–90
–100
0.1
1
10
100
FREQUENCY (MHz)
1000
06693-018
CROSSTALK (dB)
10k
FREQUENCY (Hz)
Figure 15. Off Isolation vs. Frequency
–10
1k
06693-013
0.05
06693-029
ATTENUATION (dB)
–20
Figure 16. Crosstalk vs. Frequency
–100
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 18. PSRR vs. Frequency
Rev. 0 | Page 10 of 16
100M
1G
ADG824
TEST CIRCUITS
A
D
ID (OFF)
S
NC
A
D
ID (ON)
A
VD
VS
S
VD
06693-003
V1
D
RON = V1/IDS
06693-002
Figure 21. On Leakage
Figure 20. Off Leakage
Figure 19. On Resistance
VDD
0.1µF
VDD
S1B
S1A
VS
VOUT
D
CL
35pF
RL
50Ω
IN
50%
VIN
50%
90%
VOUT
90%
tON
tOFF
06693-005
GND
Figure 22. Switching Times, tON, tOFF
0.1µF
VDD
VDD
S1B
S1A
VS
VIN
D
VOUT
RL
50Ω
IN
50%
0V
VOUT
80%
CL
35pF
50%
80%
tBBM
tBBM
06693-006
GND
Figure 23. Break-Before-Make Time Delay, tBBM
VDD
SWITCH ON
D
VS
SWITCH OFF
VIN
S1B
NC
S1A
VOUT
1nF
IN
VOUT
ΔVOUT
GND
QINJ = CL × ΔVOUT
Figure 24. Charge Injection
Rev. 0 | Page 11 of 16
06693-007
VS
S
06693-004
IS (OFF)
IDS
ADG824
VDD
VDD
0.1µF
0.1µF
NETWORK
ANALYZER
S1A
VS
D
RL
50Ω
VOUT
VS
D2
NC
S1B
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
S1B
NC
50Ω
VS
VOUT
VS
VDD
NETWORK
ANALYZER
50Ω
S1A
VS
D
06693-011
VS
D1
S1A
VOUT
VDD
S2B
50Ω
GND
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
0.1µF
S2A
RL
50Ω
Figure 27. Channel-to-Channel Crosstalk (S1A to S1B/S2A to S2B)
NETWORK
ANALYZER
50Ω
D
S1B
VS
Figure 25. Off Isolation
VOUT
RL
50Ω
50Ω
VOUT
06693-008
GND
OFF ISOLATION = 20 log
VOUT
50Ω
50Ω
VDD
S1A
RL
50Ω
GND
INSERTION LOSS = 20 log
Figure 26. Channel-to-Channel Crosstalk (S1A to S2A/S1B to S2B)
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 28. Bandwidth
Rev. 0 | Page 12 of 16
VOUT
06693-009
S1B
NC
NETWORK
ANALYZER
06693-010
VDD
ADG824
TERMINOLOGY
IDD
CD, CS (On)
Positive supply current.
On switch capacitance. Measured with reference to ground.
VD (VS)
CIN
Analog voltage on Terminal D and Terminal S.
Digital input capacitance.
RON
tON
Ohmic resistance between Terminal D and Terminal S.
Delay time between the 50% and 90% points of the digital input
and switch on condition.
RFLAT (On)
The difference between the maximum and minimum values of
on resistance as measured on the switch.
ΔRON
On resistance match between any two channels.
IS (Off)
Source leakage current with the switch off.
ID (Off)
Drain leakage current with the switch off.
ID, IS (On)
Channel leakage current with the switch on.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IINL (IINH)
Input current of the digital input.
CS (Off)
Off switch source capacitance. Measured with reference
to ground.
tOFF
Delay time between the 50% and 90% points of the digital input
and switch off condition.
tBBM
On or off time measured between the 80% points of both
switches when switching from one to another.
Charge Injection
Measure of the glitch impulse transferred from the digital input
to the analog output during on/off switching.
Off Isolation
Measure of unwanted signal coupling through an off switch.
Crosstalk
Measure of unwanted signal that is coupled from one channel to
another as a result of parasitic capacitance.
−3 dB Bandwidth
Frequency at which the output is attenuated by 3 dB.
Insertion Loss
The loss due to the on resistance of the switch.
THD + N
Ratio of the harmonics amplitude plus noise of a signal to the
fundamental.
Rev. 0 | Page 13 of 16
ADG824
OUTLINE DIMENSIONS
0.20 DIA
TYP
0.55
0.40
0.30
1.30
1
1.60
0.40
BSC
6
4
0.35
0.30
0.25
BOTTOM VIEW
TOP VIEW
0.60
0.55
0.50
PIN 1
IDENTIFIER
9
0.05 MAX
0.02 NOM
033007-A
0.20 BSC
SEATING
PLANE
Figure 29. 10-Lead Lead Frame Chip Scale Package (LFCSP_UQ)
1.3 mm × 1.6 mm Body, Ultra Thin Quad
(CP-10-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADG824BCPZ-REEL 1
ADG824BCPZ-REEL71
EVAL-ADG824EBZ1
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
10-Lead Mini Lead Frame Chip Scale Package (LFCSP_UQ)
10-Lead Mini Lead Frame Chip Scale Package (LFCSP_UQ)
Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 14 of 16
Package Option
CP-10-10
CP-10-10
Branding
A
A
ADG824
NOTES
Rev. 0 | Page 15 of 16
ADG824
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06693-0-4/08(0)
Rev. 0 | Page 16 of 16