100 mA, Low Quiescent Current,
CMOS Linear Regulator
ADP120
TYPICAL APPLICATIONS CIRCUITS
VIN = 2.3V
1
VIN
2
GND
3
EN
VOUT 5
+
1µF
VOUT = 1.8V
+
1µF
NC 4
07589-001
Input voltage range: 2.3 V to 5.5 V
Output voltage range: 1.2 V to 3.3 V
Output current: 100 mA
Low quiescent current
IGND = 11 μA with zero load
IGND = 22 μA with 100 mA load
Low shutdown current: <1 μA
Low dropout voltage
60 mV @ 100 mA load
High PSRR
73 dB @ 1 kHz at VOUT = 1.2 V
70 dB @ 10 kHz at VOUT = 1.2 V
Low noise: 40 μV rms at VOUT = 1.2 V
No noise bypass capacitor required
Initial accuracy: ±1%
Stable with small 1 μF ceramic output capacitor
16 fixed output voltage options
Current-limit and thermal overload protection
Logic controlled enable
5-lead TSOT package
4-ball 0.4 mm pitch WLCSP
NC = NO CONNECT
Figure 1. ADP120 TSOT with Fixed Output Voltage, 1.8 V
VIN = 2.3V
+
1µF
VOUT = 1.8V
VIN
EN
VOUT
GND
+
1µF
07589-002
FEATURES
Figure 2. ADP120 WLCSP with Fixed Output Voltage, 1.8 V
APPLICATIONS
Mobile phones
Digital camera and audio devices
Portable and battery-powered equipment
Post regulation
GENERAL DESCRIPTION
The ADP120 is a low quiescent current, low dropout, linear
regulator that operates from 2.3 V to 5.5 V and provides up to
100 mA of output current. The low 60 mV dropout voltage at
100 mA load improves efficiency and allows operation over a
wide input voltage range. The low 25 μA of quiescent current at
full load makes the ADP120 ideal for battery-operated portable
equipment.
The ADP120 is available in 16 fixed output voltage options,
ranging from 1.2 V to 3.3 V. The part is optimized for stable
operation with small 1 μF ceramic output capacitors. The
ADP120 delivers good transient performance with minimal
board area.
Short-circuit protection and thermal overload protection circuits
prevent damage in adverse conditions. The ADP120 is available
in a tiny 5-lead TSOT and a 4-ball 0.4 mm pitch WLCSP for the
smallest footprint solution for use in a variety of portable
applications.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADP120
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Applications ....................................................................................... 1
Theory of Operation ...................................................................... 11
Typical Application Circuits............................................................ 1
Applications Information .............................................................. 12
General Description ......................................................................... 1
Capacitor Selection .................................................................... 12
Revision History ............................................................................... 2
Undervoltage Lockout ............................................................... 13
Specifications..................................................................................... 3
Enable Feature ............................................................................ 13
Recommended Specifications: Input and Output Capacitors 4
Current Limit and Thermal Overload Protection ................. 14
Absolute Maximum Ratings............................................................ 5
Thermal Considerations............................................................ 14
Thermal Data ................................................................................ 5
PCB Layout Considerations ...................................................... 17
Thermal Resistance ...................................................................... 5
Outline Dimensions ....................................................................... 18
ESD Caution .................................................................................. 5
Ordering Guide .......................................................................... 19
Pin Configurations and Function Descriptions ........................... 6
REVISION HISTORY
7/08—Rev. 0 to Rev. A
Deleted ADP120-1.............................................................. Universal
Changes to General Description .................................................... 1
Changes to Dropout Voltage Parameter, Table 1 .......................... 3
Changes to Thermal Data Section.................................................. 5
Changes to Figure 12 and Figure 14 ............................................... 8
Changes to Figure 22 ........................................................................ 9
Changes to Table 6 and Table 7 ..................................................... 14
Changes to Figure 46 and Figure 47 Captions ............................ 17
Changes to Ordering Guide .......................................................... 18
6/08—Revision 0: Initial Version
Rev. A | Page 2 of 20
ADP120
SPECIFICATIONS
VIN = (VOUT + 0.4 V) or 2.3 V, whichever is greater; EN = VIN, IOUT = 10 mA, CIN = COUT = 1 μF, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT
Symbol
VIN
IGND
SHUTDOWN CURRENT
IGND-SD
FIXED OUTPUT VOLTAGE ACCURACY
VOUT
REGULATION
Line Regulation
∆VOUT/∆VIN
Load Regulation 1
DROPOUT VOLTAGE 2
TSOT
∆VOUT/∆IOUT
VDROPOUT
WLCSP
START-UP TIME 3
CURRENT LIMIT THRESHOLD 4
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
EN INPUT
EN Input Logic High
EN Input Logic Low
EN Input Leakage Current
UNDERVOLTAGE LOCKOUT
Input Voltage Rising
Input Voltage Falling
Hysteresis
OUTPUT NOISE
tSTART-UP
ILIMIT
Conditions
TJ = −40°C to +125°C
IOUT = 0 μA
IOUT = 0 μA, TJ = −40°C to +125°C
IOUT = 10 mA
IOUT = 10 mA, TJ = −40°C to +125°C
IOUT = 100 mA
IOUT = 100 mA, TJ = −40°C to +125°C
EN = GND
EN = GND, TJ = −40°C to +125°C
IOUT = 10 mA
100 μA < IOUT < 100 mA, VIN = (VOUT + 0.4 V) to 5.5 V
100 μA < IOUT < 100 mA, VIN = (VOUT + 0.4 V) to 5.5 V,
TJ = −40°C to +125°C
Min
2.3
−1
−2
−2.5
1.5
+1
+2
+2.5
Unit
V
μA
μA
μA
μA
μA
μA
μA
μA
%
%
%
VIN = (VOUT + 0.4 V) to 5.5 V, IOUT = 1 mA,
TJ = −40°C to +125°C
IOUT = 1 mA to 100 mA
IOUT = 1 mA to 100 mA, TJ = −40°C to +125°C
VOUT = 3.3 V
IOUT = 10 mA
IOUT = 10 mA, TJ = −40°C to +125°C
IOUT = 100 mA
IOUT = 100 mA, TJ = −40°C to +125°C
IOUT = 10 mA
IOUT = 10 mA, TJ = −40°C to +125°C
IOUT = 100 mA
IOUT = 100 mA, TJ = −40°C to +125°C
VOUT = 3.3 V
−0.03
+0.03
%/ V
0.005
%/mA
%/mA
TJ rising
VIH
VIL
VI-LEAKAGE
2.3 V ≤ VIN ≤ 5.5 V
2.3 V ≤ VIN ≤ 5.5 V
EN = VIN or GND
EN = VIN or GND, TJ = −40°C to +125°C
UVLO
UVLORISE
UVLOFALL
UVLOHYS
OUTNOISE
Max
5.5
11
21
15
29
22
35
0.1
0.001
8
12
80
120
6
9
60
90
110
TSSD
TSSD-HYS
Typ
120
180
350
150
15
TJ = −40°C to +125°C
TJ = −40°C to +125°C
10 Hz to 100 kHz, VIN = 5 V, VOUT = 3.3 V
10 Hz to 100 kHz, VIN = 5 V, VOUT = 2.5 V
10 Hz to 100 kHz, VIN = 5 V, VOUT = 1.2 V
Rev. A | Page 3 of 20
°C
°C
1.2
0.4
0.05
1
2.25
1.5
120
65
52
40
mV
mV
mV
mV
mV
mV
mV
mV
μs
mA
V
V
μA
μA
V
V
mV
μV rms
μV rms
μV rms
ADP120
Parameter
POWER SUPPLY REJECTION RATIO
Symbol
PSRR
Conditions
10 kHz, VIN = 5 V, VOUT = 3.3 V
10 kHz, VIN = 5 V, VOUT = 2.5 V
10 kHz, VIN = 5 V, VOUT = 1.2 V
Min
Typ
60
66
70
Max
Unit
dB
dB
dB
1
Based on an endpoint calculation using 1 mA and 100 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA.
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.3 V.
3
Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.
4
Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
2
RECOMMENDED SPECIFICATIONS: INPUT AND OUTPUT CAPACITORS
Table 2.
Parameter
MINIMUM INPUT AND OUTPUT CAPACITANCE 1
CAPACITOR ESR
1
Symbol
CMIN
RESR
Conditions
TJ = −40°C to +125°C
TJ = −40°C to +125°C
Min
0.70
0.001
Typ
Max
1
Unit
μF
Ω
The minimum input and output capacitance should be greater than 0.70 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended,
Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. A | Page 4 of 20
ADP120
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND Pins
VOUT to GND Pins
EN to GND Pins
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
−0.3 V to +6 V
−0.3 V to VIN
−0.3 V to +6 V
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP120 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that TJ is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (TJ) of
the device is dependent on the ambient temperature (TA), the
power dissipation of the device (PD), and the junction-to-ambient
thermal resistance of the package (θJA).
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) using the
formula
TJ = TA + (PD × θJA)
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a four-layer board.
The junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending on
PCB material, layout, and environmental conditions. The specified values of θJA are based on a four-layer, 4 in. × 3 in. PCB.
Refer to JESD 51-7 and JESD 51-9 for detailed information
regarding board construction. For additional information, see
Application Note AN-617, MicroCSPTM Wafer Level Chip Scale
Package.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a four-layer board. JESD51-12, Guidelines for
Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as
thermal resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θJB. Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation from
the package, factors that make ΨJB more useful in real-world
applications. Maximum junction temperature (TJ) is calculated
from the board temperature (TB) and power dissipation (PD)
using the formula
TJ = TB + (PD × ΨJB)
Refer to JESD51-8, JESD51-9, and JESD51-12 for more detailed
information about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
5-Lead TSOT
4-Ball, 0.4 mm Pitch WLCSP
ESD CAUTION
Rev. A | Page 5 of 20
θJA
170
260
ΨJB
43
58
Unit
°C/W
°C/W
ADP120
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
5
A
TOP VIEW
(Not to Scale)
EN 3
4
NC = NO CONNECT
NC
2
VIN
VOUT
TOP VIEW
(Not to Scale)
07589-033
GND 2
1
VOUT
B
Figure 3. 5-Lead TSOT Pin Configuration
EN
GND
07589-034
VIN 1
Figure 4. 4-Ball WLCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
TSOT WLCSP
1
A1
2
B2
3
B1
Mnemonic
VIN
GND
EN
4
5
NC
VOUT
N/A
A2
Description
Regulator Input Supply. Bypass VIN to GND with a 1 μF or greater capacitor.
Ground.
Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic
startup, connect EN to VIN.
No Connect. Not connected internally. Not applicable (N/A) for the WLCSP.
Regulated Output Voltage. Bypass VOUT to GND with a 1 μF or greater capacitor.
Rev. A | Page 6 of 20
ADP120
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 1 μF, TA = 25°C, unless otherwise noted.
35
LOAD = 10µA
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
30
1.798
1.796
1.794
1.792
25
20
15
10
5
1.790
–5°C
25°C
85°C
0
07589-005
–40°C
125°C
TJ (°C)
–40°C
85°C
125°C
30
25
GROUND CURRENT (µA)
1.803
1.801
1.799
1.797
20
15
10
5
1
10
100
ILOAD (mA)
0
0.01
07589-006
0.1
1
30
LOAD = 10µA
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
GROUND CURRENT (µA)
25
1.801
1.799
1.797
20
15
10
LOAD = 10µA
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
07589-007
5
VIN (V)
100
Figure 9. Ground Current vs. Load Current
1.805
1.795
2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
10
ILOAD (mA)
Figure 6. Output Voltage vs. Load Current
1.803
0.1
07589-009
VOUT (V)
25°C
Figure 8. Ground Current vs. Junction Temperature
1.805
1.795
0.01
–5°C
TJ (°C)
Figure 5. Output Voltage vs. Junction Temperature
VOUT (V)
LOAD = 10µA
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
Figure 7. Output Voltage vs. Input Voltage
0
2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V)
Figure 10. Ground Current vs. Input Voltage
Rev. A | Page 7 of 20
07589-010
VOUT (V)
1.800
07589-008
1.802
GROUND CURRENT (µA)
1.804
ADP120
90
0.35
2.30V
2.50V
3.00V
3.50V
4.20V
5.50V
0.25
DROPOUT VOLTAGE (mV)
SHUTDOWN CURRENT (µA)
0.30
TA = 25°C
80
0.20
0.15
0.10
0.05
70
60
50
40
VOUT = 2.5V
30
20
10
VOUT = 3.3V
0
25
50
75
100
125
TEMPERATURE (°C)
1
Figure 11. Shutdown Current vs. Temperature at Various Input Voltages
100
Figure 14. Dropout Voltage vs. Load Current, WLCSP, VOUT = 2.5 V and 3.3 V
3.35
TA = 25°C
100
3.30
80
3.25
VOUT (V)
60
3.20
3.15
VOUT = 2.5V
VOUT @ 1mA
VOUT @ 10mA
VOUT @ 20mA
VOUT @ 50mA
VOUT @ 100mA
3.10
20
VOUT = 3.3V
3.05
3.20
1
10
100
ILOAD (mA)
07589-012
0
Figure 12. Dropout Voltage vs. Load Current, TSOT, VOUT = 2.5 V and 3.3 V
3.35
3.40
3.45
60
GROUND CURRENT (µA)
3.20
3.15
3.10
3.25
3.30
3.35
3.40
VIN (V)
3.45
3.50
@ 1mA
@ 10mA
@ 20mA
@ 50mA
@ 100mA
3.55
3.60
3.60
40
30
20
10
07589-013
VOUT
VOUT
VOUT
VOUT
VOUT
3.55
ILOAD @ 1mA
ILOAD @ 10mA
ILOAD @ 20mA
ILOAD @ 50mA
ILOAD @ 100mA
50
3.25
3.50
Figure 15. Output Voltage vs. Input Voltage (in Dropout), WLCSP, VOUT = 3.3 V
3.30
VOUT (V)
3.30
VIN (V)
3.35
3.05
3.20
3.25
07589-015
40
Figure 13. Output Voltage vs. Input Voltage (in Dropout), TSOT, VOUT = 3.3 V
Rev. A | Page 8 of 20
0
3.20
3.25
3.30
3.35
3.40
3.45
3.50
3.55
VIN (V)
Figure 16. Ground Current vs. Input Voltage (in Dropout)
3.60
07589-016
DROPOUT VOLTAGE (mV)
120
10
ILOAD (mA)
07589-014
–25
0
07589-011
0
–50
ADP120
100mA
10mA
1mA
100µA
NO LOAD
–10
–10
–30
–40
–40
PSRR (dB)
–30
–50
–60
–80
–80
–90
–90
1k
10k
100k
1M
10M
FREQUENCY (Hz)
–100
10
0
100mA
10mA
1mA
100µA
NO LOAD
–20
100
1k
10k
100k
1M
10M
Figure 20. Power Supply Rejection Ratio vs. Frequency,
Various Output Voltages and Load Currents
10
VRIPPLE = 50mV
VIN = 5V
VOUT = 1.8V
COUT = 1µF
3.3V
NOISE (µV/ Hz)
–30
PSRR (dB)
1.8V/100µA
FREQUENCY (Hz)
Figure 17. Power Supply Rejection Ratio vs. Frequency
–10
1.8V/100mA
1.2V/100µA
–60
–70
100
1.2V/100mA
3.3V/100µA
–50
–70
–100
10
3.3V/100mA
–20
07589-017
PSRR (dB)
–20
0
VRIPPLE = 50mV
VIN = 5V
VOUT = 1.2V
COUT = 1µF
07589-020
0
–40
–50
–60
–70
1.8V
1
1.2V
0.1
–80
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 18. Power Supply Rejection Ratio vs. Frequency
0
100mA
10mA
1mA
100µA
NO LOAD
–10
–20
0.01
10
07589-018
100
1k
10k
100k
FREQUENCY (Hz)
Figure 21. Output Noise Spectrum, VIN = 5 V, ILOAD = 10 mA, COUT = 1 μF
70
VRIPPLE = 50mV
VIN = 5V
VOUT = 3.3V
COUT = 1µF
3.3V
60
2.5V
50
NOISE (µV rms)
–30
–40
–50
–60
–70
1.8V
1.5V
40
1.2V
30
20
–80
10
–100
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
Figure 19. Power Supply Rejection Ratio vs. Frequency
0
0.001
0.01
0.1
1
10
100
ILOAD (mA)
Figure 22. Output Noise vs. Load Current and Output Voltage
VIN = 5 V, COUT = 1 μF
Rev. A | Page 9 of 20
07589-022
–90
07589-019
PSRR (dB)
100
07589-021
–90
–100
10
ADP120
ILOAD
(1V/DIV)
(100mA/DIV)
ILOAD
1mA TO 100mA LOAD STEP,
2.5A/µs
4V TO 5V INPUT VOLTAGE STEP,
2V/µs
(40µs/DIV)
VOUT = 1.8V,
CIN = COUT = 1µF
07589-023
VIN = 5V
VOUT = 1.8V
VOUT
(4µs/DIV)
Figure 23. Load Transient Response, CIN and COUT = 1 μF
07589-125
(50mV/DIV)
(10mV/DIV)
VOUT
Figure 25. Line Transient Response, Load Current = 100 mA
(1V/DIV)
(100mA/DIV)
ILOAD
1mA TO 100mA LOAD STEP,
2.5A/µs
ILOAD
4V TO 5V INPUT VOLTAGE STEP,
2V/µs
(40µs/DIV)
VOUT = 1.8V,
CIN = COUT = 1µF
07589-024
VIN = 5V
VOUT = 1.8V
VOUT
(10µs/DIV)
Figure 24. Load Transient Response, CIN and COUT = 4.7 μF
Figure 26. Line Transient Response, Load Current = 1 mA
Rev. A | Page 10 of 20
07589-026
(50mV/DIV)
(10mV/DIV)
VOUT
ADP120
THEORY OF OPERATION
The ADP120 is a low quiescent current, low dropout linear
regulator that operates from 2.3 V to 5.5 V and provides up
to 100 mA of output current. Drawing a low 22 μA of quiescent current (typical) at full load makes the ADP120 ideal
for battery-operated portable equipment. Shutdown current
consumption is typically 100 nA.
Internally, the ADP120 consists of a reference, an error amplifier,
a feedback voltage divider, and a PMOS pass transistor. Output
current is delivered via the PMOS pass device, which is controlled
by the error amplifier. The error amplifier compares the reference
voltage with the feedback voltage from the output and amplifies
the difference. If the feedback voltage is lower than the reference
voltage, the gate of the PMOS device is pulled lower, allowing
more current to pass and increasing the output voltage. If the
feedback voltage is higher than the reference voltage, the gate of
the PMOS device is pulled higher, allowing less current to pass
and decreasing the output voltage.
Optimized for use with small 1 μF ceramic capacitors, the
ADP120 provides excellent transient performance.
VIN
VOUT
The ADP120 is available in 16 output voltage options, ranging
from 1.2 V to 3.3 V. The ADP120 uses the EN pin to enable and
disable the VOUT pin under normal operating conditions. When
EN is high, VOUT turns on; when EN is low, VOUT turns off.
For automatic startup, EN can be tied to VIN.
R1
EN
SHUTDOWN
0.8V REFERENCE
R2
07589-127
GND
SHORT CIRCUIT,
UVLO, AND
THERMAL
PROTECT
Figure 27. Internal Block Diagram
Rev. A | Page 11 of 20
ADP120
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Input and Output Capacitor Properties
Output Capacitor
Use any good quality ceramic capacitors with the ADP120, as
long as they meet the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with
a voltage rating of 6.3 V or 10 V are recommended for best
performance. Y5V and Z5U dielectrics are not recommended
for use with any LDO because of their poor temperature and dc
bias characteristics.
The ADP120 is designed for operation with small, space-saving
ceramic capacitors, but functions with most commonly used
capacitors as long as care is taken with regard to the effective
series resistance (ESR) value. The ESR of the output capacitor
affects stability of the LDO control loop. A minimum of 0.70 μF
capacitance with an ESR of 1 Ω or less is recommended to ensure
stability of the ADP120. Transient response to changes in load
current is also affected by output capacitance. Using a larger
value of output capacitance improves the transient response of
the ADP120 to large changes in load current. Figure 28 and
Figure 29 show the transient responses for output capacitance
values of 1 μF and 4.7 μF, respectively.
(100mA/DIV)
ILOAD
1mA TO 100mA LOAD STEP,
2.5A/µs
Figure 30 depicts the capacitance vs. voltage bias characteristic
of a 0402 1 μF, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating.
In general, a capacitor in a larger package or higher voltage rating
exhibits better stability. The temperature variation of the X5R
dielectric is about ±15% over the −40°C to +85°C temperature
range and is not a function of package or voltage rating.
1.2
MURATA PART NUMBER:
GRM155R61A105KE15
(400ns/DIV)
07589-128
VOUT = 1.8V,
CIN = COUT = 1µF
CAPACITANCE (µF)
VOUT
Figure 28. Output Transient Response, COUT = 1 μF
(100mA/DIV)
ILOAD
0.8
0.6
0.4
0.2
1mA TO 100mA LOAD STEP,
2.5A/µs
0
0
2
4
6
VOLTAGE (V)
8
10
07589-126
(50mV/DIV)
1.0
(50mV/DIV)
Figure 30. Capacitance vs. Voltage Characteristic
Use Equation 1 to determine the worst-case capacitance accounting
for capacitor variation over temperature, component tolerance,
and voltage.
VOUT
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
(400ns/DIV)
(1)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
07589-129
VOUT = 1.8V,
CIN = COUT = 4.7µF
Figure 29. Output Transient Response, COUT = 4.7 μF
Input Bypass Capacitor
Connecting a 1 μF capacitor from VIN to GND reduces the circuit sensitivity to printed circuit board (PCB) layout, especially
when long input traces or high source impedance are encountered.
If greater than 1 μF of output capacitance is required, increase
the input capacitor to match it.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%,
and CBIAS is 0.94 μF at 1.8 V, as shown in Figure 30.
Substituting these values in Equation 1 yields
CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF
Rev. A | Page 12 of 20
ADP120
UNDERVOLTAGE LOCKOUT
The ADP120 has an internal undervoltage lockout circuit that
disables all inputs and the output when the input voltage is less
than approximately 2.2 V. This ensures that the inputs and the
output of the ADP120 behave in a predictable manner during
power-up.
1.05
1.00
0.95
EN ACTIVE
0.90
0.85
EN INACTIVE
0.80
0.75
0.70
2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50
VIN (V)
ENABLE FEATURE
07589-025
To guarantee the performance of the ADP120, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
1.10
TYPICAL EN THRESHOLDS (V)
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage.
Figure 32. Typical EN Pin Thresholds vs. Input Voltage
The ADP120 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. As shown in Figure 31,
when a rising voltage on EN crosses the active threshold, VOUT
turns on. When a falling voltage on EN crosses the inactive
threshold, VOUT turns off.
The ADP120 utilizes an internal soft start to limit the inrush
current when the output is enabled. The start-up time for the
1.8 V option is approximately 120 μs from the time the EN
active threshold is crossed to when the output reaches 90% of its
final value. The start-up time is somewhat dependent on the
output voltage setting and increases slightly as the output
voltage increases.
VOUT
6
EN
VIN = 5V
VOUT = 1.8V
CIN = COUT = 1µF
ILOAD = 100mA
(40ms/DIV)
CURRENT (V)
4
3.3V
3
2
07589-124
(500mV/DIV)
EN
5
1.8V
1.2V
1
As shown in Figure 31, the EN pin has hysteresis built-in. This
prevents on/off oscillations that can occur due to noise on the
EN pin as it passes through the threshold points.
The EN pin active/inactive thresholds are derived from the VIN
voltage; therefore, these thresholds vary with changing input
voltage. Figure 32 shows typical EN active/inactive thresholds
when the input voltage varies from 2.3 V to 5.5 V.
Rev. A | Page 13 of 20
0
0
20
40
60
80
100
120
140
TIME (µs)
Figure 33. Typical Start-Up Time
160
180
200
07589-133
Figure 31. Typical EN Pin Operation
ADP120
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP120 is protected against damage due to excessive
power dissipation by current and thermal overload protection
circuits. The ADP120 is designed to current limit when the
output load reaches 150 mA (typical). When the output load
exceeds 150 mA, the output voltage reduces to maintain a
constant current limit.
Thermal overload protection is built-in, limiting the junction
temperature to a maximum of 150°C (typical). Under extreme
conditions (that is, high ambient temperature and power dissipation) when the junction temperature starts to rise above 150°C,
the output turns off, reducing the output current to zero. When
the junction temperature drops below 135°C, the output turns
on again thereby restoring output current to its nominal value.
Consider the case where a hard short from VOUT to GND
occurs. At first, the ADP120 current limits, conducting only
150 mA into the short. If self-heating of the junction is great
enough to cause its temperature to rise above 150°C, thermal
shutdown activates, turning off the output and reducing the
output current to zero. As the junction temperature cools and
drops below 135°C, the output turns on and conducts 150 mA
into the short, again causing the junction temperature to rise
above 150°C. This thermal oscillation between 135°C and 150°C
causes a current oscillation between 150 mA and 0 mA that
continues as long as the short remains at the output.
Current- and thermal-limit protections are intended to protect
the device against accidental overload conditions. For reliable
operation, device power dissipation must be externally limited
to prevent junction temperatures from exceeding 125°C.
temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal
resistances between the junction and ambient air (θJA). The θJA
number is dependent on the package assembly compounds that
are used and the amount of copper used to solder the package
GND pins to the PCB. Table 6 shows typical θJA values of the
5-lead TSOT and 4-ball WLCSP packages for various PCB
copper sizes. Table 7 shows the typical ΨJB value of the 5-lead
TSOT and 4-ball WLCSP.
Table 6. Typical θJA Values
2
Copper Size (mm )
01
50
100
300
500
1
TSOT
170
152
146
134
131
θJA (°C/W)
WLCSP
260
159
157
153
151
Device soldered to minimum size pin traces.
Table 7. Typical ΨJB Values
TSOT
42.8
ΨJB (°C/W)
WLCSP
58.4
The junction temperature of the ADP120 can be calculated
from the following equation:
TJ = TA + (PD × θJA)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND)
THERMAL CONSIDERATIONS
In most applications, the ADP120 does not dissipate much heat
due to its high efficiency. However, in applications with high
ambient temperature and high supply voltage-to-output voltage
differential, the heat dissipated in the package is large enough to
cause the junction temperature of the die to exceed the maximum
junction temperature of 125°C.
When the junction temperature exceeds 150°C, the converter
enters thermal shutdown. It recovers only after the junction
temperature has decreased below 135°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application
is very important to guarantee reliable performance over all
conditions. The junction temperature of the die is the sum of
the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown
in Equation 2.
(2)
(3)
where:
ILOAD is the load current.
IGND is the ground current.
VIN and VOUT are input and output voltages, respectively.
Power dissipation due to ground current is quite small and
can be ignored. Therefore, the junction temperature equation
simplifies to the following:
TJ = TA + {[(VIN − VOUT) × ILOAD] × θJA}
(4)
As shown in Equation 4, for a given ambient temperature, inputto-output voltage differential, and continuous load current, there
exists a minimum copper size requirement for the PCB to ensure
the junction temperature does not rise above 125°C. The following
figures show junction temperature calculations for different
ambient temperatures, load currents, VIN-to-VOUT differentials,
and areas of PCB copper.
To guarantee reliable operation, the junction temperature of
the ADP120 must not exceed 125°C. To ensure the junction
temperature stays below this maximum value, the user needs to
be aware of the parameters that contribute to junction
Rev. A | Page 14 of 20
ADP120
140
140
MAX JUNCTION TEMPERATURE
JUNCTION TEMPERATURE, TJ (°C)
120
100
IL = 100mA
IL = 75mA
60
IL = 50mA
IL = 25mA
40
20
IL = 10mA
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
120
IL = 100mA
100
IL = 75mA
IL = 50mA
80
IL = 25mA
60
IL = 10mA
40
20
IL = 1mA
4.0
4.5
VIN – VOUT (V)
0
0.5
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Figure 37. TSOT, 500 mm2 of PCB Copper, TA = 50°C
140
140
MAX JUNCTION TEMPERATURE
MAX JUNCTION TEMPERATURE
JUNCTION TEMPERATURE, TJ (°C)
120
100
IL = 100mA
IL = 75mA
IL = 50mA
60
IL = 25mA
40
20
IL = 10mA
1.0
1.5
2.0
2.5
3.0
3.5
IL = 100mA
IL = 75mA
100
IL = 50mA
80
IL = 25mA
60
40
IL = 10mA
20
IL = 1mA
4.0
4.5
VIN – VOUT (V)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VIN – VOUT (V)
Figure 35. TSOT, 100 mm2 of PCB Copper, TA = 25°C
Figure 38. TSOT, 100 mm2 of PCB Copper, TA = 50°C
140
140
MAX JUNCTION TEMPERATURE
MAX JUNCTION TEMPERATURE
100
IL = 100mA
80
IL = 75mA
JUNCTION TEMPERATURE, TJ (°C)
120
IL = 50mA
60
IL = 25mA
40
IL = 10mA
1.0
1.5
2.0
2.5
3.0
3.5
120
IL = 100mA
IL = 75mA
100
IL = 50mA
80
IL = 25mA
60
IL = 10mA
40
IL = 1mA
20
IL = 1mA
4.0
VIN – VOUT (V)
4.5
07589-028
20
0
0.5
IL = 1mA
Figure 36. TSOT, 0 mm2 of PCB Copper, TA = 25°C
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VIN – VOUT (V)
Figure 39. TSOT, 0 mm2 of PCB Copper, TA = 50°C
Rev. A | Page 15 of 20
4.5
07589-031
0
0.5
120
07589-030
80
07589-027
JUNCTION TEMPERATURE, TJ (°C)
1.0
VIN – VOUT (V)
Figure 34. TSOT, 500 mm2 of PCB Copper, TA = 25°C
JUNCTION TEMPERATURE, TJ (°C)
IL = 1mA
07589-137
80
07589-134
JUNCTION TEMPERATURE, TJ (°C)
MAX JUNCTION TEMPERATURE
ADP120
140
140
MAX JUNCTION TEMPERATURE
JUNCTION TEMPERATURE, TJ (°C)
120
100
IL = 100mA
80
IL = 75mA
60
IL = 50mA
IL = 25mA
20
IL = 10mA
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
120
IL = 100mA
IL = 75mA
100
IL = 50mA
80
IL = 25mA
60
40
IL = 10mA
20
IL = 1mA
4.0
4.5
VIN – VOUT (V)
0
0.5
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Figure 43. WLCSP, 500 mm2 of PCB Copper, TA = 50°C
140
140
MAX JUNCTION TEMPERATURE
MAX JUNCTION TEMPERATURE
IL = 100mA
80
IL = 75mA
60
IL = 50mA
IL = 25mA
40
20
IL = 10mA
1.0
1.5
2.0
2.5
3.0
3.5
IL = 100mA
IL = 75mA
100
IL = 50mA
80
IL = 25mA
60
40
IL = 10mA
IL = 1mA
4.0
4.5
VIN – VOUT (V)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VIN – VOUT (V)
Figure 41. WLCSP, 100 mm2 of PCB Copper, TA = 25°C
Figure 44. WLCSP, 100 mm2 of PCB Copper, TA = 50°C
140
140
MAX JUNCTION TEMPERATURE
120
JUNCTION TEMPERATURE, TJ (°C)
MAX JUNCTION TEMPERATURE
IL = 75mA
IL = 100mA
100
IL = 50mA
80
60
IL = 25mA
40
20
1.0
1.5
2.0
2.5
3.0
3.5
120
IL = 100mA
IL = 75mA
100
IL = 50mA
80
IL = 25mA
60
IL = 10mA
40
IL = 1mA
20
IL = 1mA
4.0
VIN – VOUT (V)
4.5
07589-142
IL = 10mA
0
0.5
IL = 1mA
20
Figure 42. WLCSP, 0 mm2 of PCB Copper, TA = 25°C
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VIN – VOUT (V)
Figure 45. WLCSP, 0 mm2 of PCB Copper, TA = 50°C
Rev. A | Page 16 of 20
4.5
07589-145
0
0.5
120
07589-144
100
JUNCTION TEMPERATURE, TJ (°C)
120
07589-141
JUNCTION TEMPERATURE, TJ (°C)
1.0
VIN – VOUT (V)
Figure 40. WLCSP, 500 mm2 of PCB Copper, TA = 25°C
JUNCTION TEMPERATURE, TJ (°C)
IL = 1mA
07589-143
40
07589-140
JUNCTION TEMPERATURE, TJ (°C)
MAX JUNCTION TEMPERATURE
ADP120
In cases where the board temperature is known, use the thermal
characterization parameter, ΨJB, to estimate the junction
temperature rise. Maximum junction temperature (TJ) is
calculated from the board temperature (TB) and power
dissipation (PD) using the formula
TJ = TB + (PD × ΨJB)
(5)
120
IL = 50mA
100
80
IL = 25mA
GND
GND
IL = 10mA
IL = 1mA
ANALOG DEVICES
ADP120-xx-EVALZ
60
40
C1
U1
C2
20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VIN – VOUT (V)
07589-146
JUNCTION TEMPERATURE, TJ (°C)
MAX JUNCTION TEMPERATURE
IL = 75mA
Improve heat dissipation from the package by increasing the
amount of copper attached to the pins of the ADP120. However,
as listed in Table 6, a point of diminishing returns is eventually
reached, beyond which an increase in the copper size does not
yield significant heat dissipation benefits.
Place the input capacitor as close as possible to the VIN and
GND pins. Place the output capacitor as close as possible to the
VOUT and GND pins. Use of 0402- or 0603-size capacitors and
resistors achieves the smallest possible footprint solution on
boards where area is limited.
140
IL = 100mA
PCB LAYOUT CONSIDERATIONS
Figure 46. TSOT, TB = 85°C
J1
VIN
140
VOUT
120
IL = 50mA
IL = 75mA
IL = 100mA
80
GND
IL = 25mA
IL = 10mA
IL = 1mA
GND
Figure 48. TSOT PCB Layout
60
J1
ADP120CB-xx-EVALZ
40
VOUT
VIN
20
C1
1.0
1.5
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
4.5
C2
WLC
SP
GND
Figure 47. WLCSP, TB = 85°C
U1
GND
EN
07589-136
0
0.5
EN
07589-032
100
07589-147
JUNCTION TEMPERATURE, TJ (°C)
MAX JUNCTION TEMPERATURE
Figure 49. WLCSP PCB Layout
Rev. A | Page 17 of 20
ADP120
OUTLINE DIMENSIONS
2.90 BSC
5
4
2.80 BSC
1.60 BSC
1
2
3
PIN 1
0.95 BSC
1.90
BSC
*0.90
0.87
0.84
*1.00 MAX
0.10 MAX
0.50
0.30
0.20
0.08
SEATING
PLANE
8°
4°
0°
0.60
0.45
0.30
*COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 50. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions shown in millimeters
SEATING
PLANE
2
1
A
0.280
0.260
0.240
B
0.40
BALL PITCH
TOP VIEW
(BALL SIDE DOWN)
0.230
0.200
0.170
BOTTOM VIEW
(BALL SIDE UP)
0.050 NOM
COPLANARITY
Figure 51. 4-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-4-2)
Dimensions shown in millimeters
Rev. A | Page 18 of 20
101507-A
A1 BALL
CORNER
0.660
0.600
0.540
0.860
0.820 SQ
0.780
ADP120
ORDERING GUIDE
Model
ADP120-AUJZ12R7 2
ADP120-AUJZ15R72
ADP120-AUJZ18R72
ADP120-AUJZ33R72
ADP120-ACBZ12R72
ADP120-ACBZ15R72
ADP120-ACBZ155R72
ADP120-ACBZ16R72
ADP120-ACBZ165R72
ADP120-ACBZ17R72
ADP120-ACBZ175R72
ADP120-ACBZ18R72
ADP120-ACBZ188R72
ADP120-ACBZ20R72
ADP120-ACBZ25R72
ADP120-ACBZ278R72
ADP120-ACBZ28R72
ADP120-ACBZ29R72
ADP120-ACBZ30R72
ADP120-ACBZ33R72
ADP120-33-EVALZ2
ADP120-18-EVALZ2
ADP120-15-EVALZ2
ADP120-12-EVALZ2
ADP120CB-2.8-EVALZ2
ADP120CB-2.5-EVALZ2
ADP120CB-1.8-EVALZ2
ADP120CB-1.5-EVALZ2
ADP120CB-1.2-EVALZ2
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Output
Voltage (V) 1
1.2
1.5
1.8
3.3
1.2
1.5
1.55
1.6
1.65
1.7
1.75
1.8
1.875
2.0
2.5
2.775
2.8
2.9
3.0
3.3
3.3
1.8
1.5
1.2
2.8
2.5
1.8
1.5
1.2
Package Description
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
ADP120 3.3 V Output Evaluation Board
ADP120 1.8 V Output Evaluation Board
ADP120 1.5 V Output Evaluation Board
ADP120 1.2 V Output Evaluation Board
ADP120 WLCSP 2.8 V Output Evaluation Board
ADP120 WLCSP 2.5 V Output Evaluation Board
ADP120 WLCSP 1.8 V Output Evaluation Board
ADP120 WLCSP 1.5 V Output Evaluation Board
ADP120 WLCSP 1.2 V Output Evaluation Board
1
For additional voltage options, contact your local Analog Devices, Inc., sales or distribution representative.
2
Z = RoHS Compliant Part.
Rev. A | Page 19 of 20
Package
Option
UJ-5
UJ-5
UJ-5
UJ-5
CB-4-2
CB-4-2
CB-4-2
CB-4-2
CB-4-2
CB-4-2
CB-4-2
CB-4-2
CB-4-2
CB-4-2
CB-4-2
CB-4-2
CB-4-2
CB-4-2
CB-4-2
CB-4-2
Branding
L9R
L9Q
L9P
L9N
LBJ
LBK
LBL
LBM
LBN
LBP
LBQ
LBR
LBS
LBT
LBU
LBV
LBW
LBX
LBY
LBZ
ADP120
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07589-0-7/08(0)
Rev. A | Page 20 of 20