AD ADP1821ARQZ-R7

Step-Down DC-to-DC Controller
ADP1821
FEATURES
GENERAL DESCRIPTION
Wide power-input voltage range: 1 V to 24 V
Chip supply voltage range: 3 V to 5.5 V
Wide output voltage range: 0.6 V to 85% of input voltage
1% accuracy, 0.6 V reference voltage
All N-channel MOSFET design for low cost
Fixed-frequency operation 300 kHz, 600 kHz, or
synchronized operation up to 1.2 MHz
No current sense resistor required
Power-good output
Programmable soft start with reverse current protection
Soft start, thermal overload, current-limit protection
Undervoltage lockout
10 μA shutdown supply current
Small, 16-lead QSOP
The ADP1821 is a versatile and inexpensive, synchronous, pulse
width-modulated (PWM), voltage-mode, step-down controller.
It drives an all N-channel power stage to regulate an output voltage
as low as 0.6 V. The ADP1821 can be configured to provide
output voltages from 0.6 V to 85% of the input voltage and is
sized to handle large MOSFETs for point-of-load regulators.
The ADP1821 is well suited for a wide range of high power
applications, such as DSP and processor core power in telecom,
medical imaging, high performance servers, and industrial
applications. It operates from a 3.0 V to 5.5 V supply with a
power input voltage ranging from 1.0 V to 24 V.
The ADP1821 operates at a pin-selectable, fixed switching
frequency of either 300 kHz or 600 kHz, minimizing external
component size and cost. For noise-sensitive applications, it
can be synchronized to an external clock to achieve switching
frequencies between 300 kHz and 1.2 MHz. The ADP1821
includes soft start protection to limit the inrush current from
the input supply during startup, reverse current protection
during soft start for precharged outputs, as well as a unique
adjustable lossless current-limit scheme utilizing external
MOSFET sensing.
APPLICATIONS
Telecom and networking systems
Set-top boxes
Printers
Servers
Medical imaging systems
Microprocessor and DSP core power supplies
Mobile communication base stations
The ADP1821 operates over the –40°C to +85°C temperature
range and is available in a 16-lead QSOP.
97
BIAS INPUT
5V
BST
DH
FREQ
SW
SYNC
PWGD
CSL
DL
COMP
PGND
4.7kΩ
SS
0.47µF
CIN1 +
2.2µF
25V
CIN2
2.2µF
25V
×2
M1
OUTPUT
1.8V, 20A
L1 = 1µH
3.3kΩ
M2
M3
COUT1
10µF +
6.3V
×2
fSW = 300kHz
COUT2
820µF
2.5V
×2
GND FB
AGND
CIN2: SANYO, OSCON 20SP180M
COUT2: SANYO, OSCON 2R5SEPC820M
L1: COILTRONICS, HC7-1R0
300Ω
CIN1: MURATA, GRM31MR71E225k
M1: IRLR7807Z
M2, M3: IRFR3709Z
D1: VISHAY BAT54
93
1.8V OUTPUT
92
91
90
10nF
1.5nF
6.8nF 100nF
94
EFFICIENCY (%)
SHDN
100kΩ
+
ADP1821
3.3V OUTPUT
95
2kΩ
89
1kΩ
88
87
05310-001
1µF
POWER INPUT
2.5V TO 20V
PVCC
0
2
4
6
8
10
12
LOAD CURRENT (A)
14
16
05310-002
D1
10Ω
VCC
TA = 25°C
FREQUENCY = 300kHz
96
1µF
Figure 1. Typical Operating Circuit
Figure 2. Efficiency vs. Load Current, 5 V Input
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rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
Rev. B
ADP1821
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Shutdown .................................................................... 11
Applications....................................................................................... 1
Shutdown Control...................................................................... 11
General Description ......................................................................... 1
Application Information................................................................ 12
Revision History ............................................................................... 2
Selecting the Input Capacitor ................................................... 12
Specifications..................................................................................... 3
Output LC Filter ......................................................................... 12
Absolute Maximum Ratings............................................................ 5
Selecting the MOSFETs ............................................................. 13
ESD Caution.................................................................................. 5
Setting the Current Limit .......................................................... 14
Simplified Block Diagram ........................................................... 5
Feedback Voltage Divider ......................................................... 14
Pin Configuration and Function Descriptions............................. 6
Compensating the Voltage Mode Buck Regulator................. 14
Typical Performance Characteristics ............................................. 7
Setting the Soft Start Period...................................................... 18
Theory of Operation ........................................................................ 9
PCB Layout Guideline ................................................................... 19
Soft Start ........................................................................................ 9
Recommended Component Manufacturers........................... 20
Error Amplifier ............................................................................. 9
Application Circuits ....................................................................... 21
Current-Limit Scheme................................................................. 9
Summary of Equations .................................................................. 23
MOSFET Drivers........................................................................ 10
Compensation Equations .......................................................... 23
Input Voltage Range ................................................................... 10
Type II Compensation Equations ............................................ 23
Setting the Output Voltage ........................................................ 10
Type III Compensation Equations........................................... 23
Switching Frequency Control and Synchronization.............. 10
Outline Dimensions ....................................................................... 24
Compensation............................................................................. 11
Ordering Guide .......................................................................... 24
Power-Good Indicator ............................................................... 11
REVISION HISTORY
12/06—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Features Section............................................................ 1
Changes to Applications Section .................................................... 1
Changes to General Description Section ...................................... 1
Changes to Error Amplifier............................................................. 3
Changes to PWM Controller .......................................................... 3
Changes to Oscillator Frequency.................................................... 3
Changes to Theory of Operation Section...................................... 9
Changes to Application Information Section ............................. 12
Added PCB Layout Section........................................................... 19
Changes to Application Circuits Section..................................... 21
Added Summary of Equations Section........................................ 23
1/06—Rev. 0 to Rev. A
Changes to Specifications Table ......................................................3
Changes to Theory of Operation Section.................................... 10
Changes to Input Voltage Range Section .................................... 11
Added Equation 1........................................................................... 12
Changes to Equation 7 and Equation 8 ....................................... 13
Added Equation 9........................................................................... 13
Changes to Equation 16................................................................. 14
Changes to Figure 15...................................................................... 14
Changes to Equation 21................................................................. 15
Changes to Figure 16...................................................................... 15
Changes to Equation 28................................................................. 15
Updated Outline Dimensions....................................................... 18
7/05—Revision 0: Initial Version
Rev. B | Page 2 of 24
ADP1821
SPECIFICATIONS
VVCC = VPVCC = VSHDN = VFREQ = 5 V, SYNC = GND. All limits at temperature extremes are guaranteed via correlation using standard
statistical quality control (SQC). TA = −40°C to +85°C, unless otherwise specified.
Table 1.
Parameter
POWER SUPPLY
Input Voltage
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
Quiescent Current
Shutdown Current
Power Stage Supply Voltage
ERROR AMPLIFIER
FB Regulation Voltage
FB Input Bias Current
Error Amplifier Open-Loop Voltage Gain
COMP Output Sink Current
COMP Output Source Current
COMP Clamp High Voltage
COMP Clamp Low Voltage
PWM CONTROLLER
PWM Peak Ramp Voltage
DL Minimum On-Time
DH Maximum Duty Cycle
DH Minimum Duty Cycle
SOFT START
SS Pull-Up Resistance
SS Pull-Down Resistance
OSCILLATOR
Oscillator Frequency
Synchronization Range
SYNC Minimum Pulse Width
CURRENT SENSE
CSL Threshold Voltage
CSL Output Current
Current Sense Blanking Period
GATE DRIVERS
DH Rise Time
DH Fall Time
DL Rise Time
DL Fall Time
DL Low to DH High Dead Time
DH Low to DL High Dead Time
LOGIC THRESHOLDS (SHDN, SYNC, FREQ)
SHDN, SYNC, FREQ Input High Voltage
SHDN, SYNC, FREQ Input Low Voltage
SYNC, FREQ Input Leakage Current
SHDN Pull-Down Resistance
Conditions
VVCC rising
VVCC
IVCC + IVCC, not switching
SHDN = GND
Min
3.0
2.5
Typ
2.7
0.1
1
1.0
594
–100
FREQ = VCC (300 kHz)
FREQ = GND (300 kHz)
FREQ = GND (300 kHz)
140
85
600
+1
70
600
110
2.4
0.75
1.25
170
90
1
Unit
5.5
2.9
V
V
V
mA
μA
V
2
10
24
606
+100
mV
nA
dB
μA
μA
V
V
3
V
ns
%
%
4.2
kΩ
kΩ
200
SS = GND
VSS = 0.6 V
1.65
FREQ = GND
FREQ = VCC
FREQ = GND
FREQ = VCC
250
470
300
600
310
570
375
720
600
1200
80
kHz
kHz
kHz
kHz
ns
Relative to PGND
VCSL = 0 V
−30
42
0
50
160
+30
54
mV
μA
ns
CGATE = 3 nF, VDH = VIN, VBST − VSW = 5 V
CGATE = 3 nF, VDH = VIN, VBST − VSW = 5 V
CGATE = 3 nF, VDL = VIN
CGATE = 3 nF, VDL = 0 V
VVCC = 3.0 V to 5.5 V
VVCC = 3.0 V to 5.5 V
SYNC = FREQ = GND
Rev. B | Page 3 of 24
95
2.5
Max
16
12
19
13
33
42
ns
ns
ns
ns
ns
ns
0.1
100
V
V
μA
kΩ
2.0
0.8
1
ADP1821
Parameter
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
PWGD OUTPUT
FB Overvoltage Threshold
FB Overvoltage Hysteresis
FB Undervoltage Threshold
FB Undervoltage Hysteresis
PWGD Off Current
PWGD Low Voltage
Conditions
VFB rising
VFB rising
VPWGD = 5 V
IPWGD = 10 mA
Rev. B | Page 4 of 24
Min
Typ
Max
Unit
145
10
°C
°C
750
35
550
35
mV
mV
mV
mV
μA
mV
150
1
500
ADP1821
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 2.
Parameter
VCC, SHDN, SYNC, FREQ, COMP, SS, FB to
GND, PVCC to PGND, BST to SW
BST to GND
CSL to GND
DH to GND
DL to PGND
SW to GND
PGND to GND
θJA, 2-Layer (SEMI Standard Board)
θJA, 4-Layer (JEDEC Standard Board)
Operating Ambient Temperature Range
Operating Junction Temperature Range
Storage Temperature Range
Maximum Soldering Lead Temperature
Rating
−0.3 V to +6 V
−0.3 V to +30 V
−1 V to +30 V
(VSW − 0.3 V) to
(VBST + 0.3 V)
−0.3 V to
(VPVCC + 0.3 V)
−2 V to +30 V
±2 V
150°C/W
105°C/W
−40°C to +85°C
−55°C to +125°C
−65°C to +150°C
260°C
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages
are referenced to GND.
ESD CAUTION
SIMPLIFIED BLOCK DIAGRAM
SHDN
ADP1821
VCC
UVLO
LOGIC
FAULT
BST
THERMAL
SHUTDOWN
GND
DH
FREQ
SYNC
S
OSCILLATOR
Q
PWM
COMP
R
SW
PVCC
Q
VCC
DL
PGND
CSL
FB
0.6V
OV
REFERENCE
100kΩ
0.8V
UV
PWGD
2.5kΩ
FAULT
UVLO
THSD
Figure 3. Simplified Block Diagram
Rev. B | Page 5 of 24
05310-003
SS
ADP1821
BST
1
16
PVCC
DH
2
15
DL
SW
3
ADP1821
14
PGND
SYNC
4
TOP VIEW
(Not to Scale)
13
CSL
FREQ
5
12
VCC
SHDN
6
11
COMP
PWGD 7
10
FB
8
9
SS
GND
05310-004
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 3. Pin Function Description
Pin No.
1
Mnemonic
BST
2
DH
3
SW
4
SYNC
5
FREQ
6
SHDN
7
PWGD
8
9
GND
SS
10
FB
11
COMP
12
VCC
13
CSL
14
15
PGND
DL
16
PVCC
Description
High-Side Gate Driver Boost Capacitor Input. A capacitor between SW and BST powers the high-side gate driver, DH.
The capacitor is charged through a diode from PVCC when the low-side MOSFET is on. Connect a 0.1 μF or greater
ceramic capacitor from BST to SW and a Schottky diode from PVCC to BST to power the high-side gate driver.
High-Side Gate Driver Output. Connect DH to the gate of the external high-side, N-channel MOSFET switch. DH is
powered from the capacitor between SW and BST, and its voltage swings between VSW and VBST.
Power Switch Node. Connect the source of the high-side, N-channel MOSFET switch and the drain of the low-side,
N-channel MOSFET synchronous rectifier to SW. SW powers the output through the output LC filter.
Frequency Synchronization Input. Drive SYNC with an external 300 kHz to 1.2 MHz signal to synchronize the converter
switching frequency to the applied signal. The maximum SYNC frequency is limited to 2 times the nominal internal
frequency selected by FREQ. Do not leave SYNC unconnected; when not used, connect SYNC to GND.
Frequency Select Input. FREQ selects the converter switching frequency. Drive FREQ low to select 300 kHz, or high
to select 600 kHz. Do not leave FREQ unconnected.
Active-Low DC-to-DC Shutdown Input. Drive SHDN high to turn on the converter and low to turn it off. Connect
SHDN to VCC for automatic startup.
Open-Drain Power-Good Output. PWGD sinks current to GND when the output voltage is above or below the
regulation voltage. Connect a pull-up resistor from PWGD to VDD for a logical power-good indicator.
Analog Ground. Connect GND to PGND at a single point as close as possible to the internal circuitry (IC).
Soft Start Control Input. A capacitor from SS to GND controls the soft start period. When the output is overloaded,
SS is discharged to prevent excessive input current while the output recovers. Connect a 1 nF capacitor to 1 μF
capacitor from SS to GND to set the soft start period. See the Soft Start section.
Voltage Feedback Input. Connect to a resistive voltage divider from the output to FB to set the output voltage. See
the Setting the Output Voltage section.
Compensation Node. Connect a resistor-capacitor network from COMP to FB to compensate the regulation control
system. See the Compensation section.
Internal Power Supply Input. VCC powers the internal circuitry. Bypass VCC to GND with a 0.1 μF or greater
capacitor connected as close as possible to the IC.
Low-Side Current Sense Input. Connect CSL to SW through a resistor to set the current limit. See the Setting the
Current Limit section.
Power Ground. Connect GND to PGND at a single point as close as possible to the IC.
Low-Side Gate Driver Output. Connect DL to the gate of the low-side N-channel MOSFET synchronous rectifier. The
DL voltage swings between PGND and PVCC.
Internal Gate Driver Power Supply Input. PVCC powers the low-side gate driver, DL. Bypass PVCC to PGND with a
1 μF or greater capacitor connected as close as possible to the IC.
Rev. B | Page 6 of 24
ADP1821
TYPICAL PERFORMANCE CHARACTERISTICS
97
0.6003
TA = 25°C
FREQUENCY = 300kHz
96
0.6002
FEEDBACK VOLTAGE (V)
3.3V OUTPUT
95
EFFICIENCY (%)
94
93
1.8V OUTPUT
92
91
90
0.6001
0.6000
0.5999
0.5998
89
2
4
6
8
10
12
14
16
LOAD CURRENT (A)
0.5996
–50
30
50
70
90
110
100
700
TA = 25°C
FREQUENCY = 300kHz
SWITCHING FREQUENCY (kHz)
600
3.3V OUTPUT
90
EFFICIENCY (%)
10
Figure 8. FB Regulation Voltage vs. Temperature
92
88
1.8V OUTPUT
86
84
82
600kHz
500
400
300
300kHz
200
100
0
2
4
6
8
10
12
14
16
LOAD CURRENT (A)
05310-006
80
–10
TEMPERATURE (°C)
Figure 5. Efficiency vs. Load Current, VIN = 5 V, VOUT = 3.3 V, 1.8 V
94
–30
05310-008
0
05310-005
87
05310-009
0.5997
88
Figure 6. Efficiency vs. Load Current, VIN = 12 V, VOUT = 3.3 V, 1.8 V
0
–50
0
50
TEMPERATURE (°C)
Figure 9. Switching Frequency vs. Temperature
1400
OUTPUT VOLTAGE
(20mV/DIV)
1000
800
600
400
LOAD CURRENT
(5A/DIV)
0
0
1
2
3
4
5
VCC VOLTAGE (V)
6
05310-010
200
05310-007
VCC CURRENT (µA)
1200
Figure 7. VCC Supply Current vs. VCC Voltage
Figure 10. Load Transient Response, 1.5 A to 15 A
Rev. B | Page 7 of 24
ADP1821
OUTPUT VOLTAGE
(1V/DIV)
OUTPUT VOLTAGE
(50mV/DIV)
SHDN (5V/DIV)
INPUT VOLTAGE
(5V/DIV)
05310-011
05310-013
PWGD (5V/DIV)
Figure 13. Power-On Response, Prebiased Output
Figure 11. Line Transient Response, 10 V to 16 V
OUTPUT VOLTAGE
(1V/DIV)
OUTPUT VOLTAGE
(1V/DIV)
SHDN (5V/DIV)
LOAD CURRENT
(10A/DIV)
05310-014
05310-012
PWGD (5V/DIV)
Figure 12. Power-On Response
Figure 14. Output Short-Circuit Response and Recovery
Rev. B | Page 8 of 24
ADP1821
THEORY OF OPERATION
The ADP1821 is a versatile, economical, synchronous-rectified,
fixed-frequency, PWM, voltage mode step-down controller
capable of generating an output voltage as low as 0.6 V. It is ideal
for a wide range of high power applications, such as DSP power
and processor core power in telecom, medical imaging, and
industrial applications. The ADP1821 controller operates from
a 3.0 V to 5.5 V supply with a power input voltage ranging from
1.0 V to 24 V.
The ADP1821 operates at a fixed, internally set 300 kHz or
600 kHz switching frequency that is controlled by the state of
the FREQ input. The high frequency reduces external component size and cost while maintaining high efficiency. For noise
sensitive applications where the switching frequency needs to be
more tightly controlled, synchronize the ADP1821 to an external
signal whose frequency is between 300 kHz and 1.2 MHz.
The ADP1821 includes adjustable soft start with output reversecurrent protection, and a unique adjustable, lossless current
limit. It operates over the −40°C to +85°C temperature range
and is available in a space-saving, 16-lead QSOP.
SOFT START
When powering up or resuming operation after shutdown, overload, or short-circuit conditions, the ADP1821 employs an
adjustable soft start feature that reduces input current transients
and prevents output voltage overshoot at start-up and overload
conditions. The soft start period is set by the value of the soft
start capacitor, CSS, between SS and GND.
When starting the ADP1821, CSS is initially discharged. It is
enabled when SHDN is high and VCC is above the undervoltage lockout threshold. CSS begins charging to 0.8 V through
an internal 100 kΩ resistor. As CSS charges, the regulation voltage
at FB is limited to the lesser of either the voltage at SS or the
internal 0.6 V reference voltage. As the voltage at SS rises, the
output voltage rises proportionally until the voltage at SS exceeds
0.6 V. At this time, the output voltage is regulated to the desired
voltage.
If the output voltage is precharged prior to turn-on, the ADP1821
limits reverse inductor current, which would discharge the output
voltage. Once the voltage at SS exceeds the 0.6 V regulation voltage,
the reverse current is re-enabled to allow the output voltage
regulation to be independent of load current.
ERROR AMPLIFIER
The ADP1821 error amplifier is an operational amplifier.
The ADP1821 senses the output voltages through an external
resistor divider at the FB pin. The FB pin is the inverting input
to the error amplifier. The error amplifier compares this feedback voltage to the internal 0.6 V reference, and the output of
the error amplifier appears at the COMP pin. The COMP pin
voltage then directly controls the duty cycle of the switching
converter.
A series/parallel RC network is tied between the FB pin and the
COMP pin to provide the compensation for the buck converter
control loop. A detailed design procedure for compensating the
system is provided in the Compensating the Voltage Mode Buck
Regulator section.
The error amplifier output is clamped between a lower limit
of about 0.7 V and a higher limit of about 2.4 V. When the
COMP pin is low, the switching duty cycle goes to 0%, and
when the COMP pin is high, the switching duty cycle goes to
the maximum.
The SS pin is an auxiliary positive input to the error amplifier.
Whichever voltage is lowest, SS or the internal 0.6 V reference,
controls the FB pin voltage and thus the output. As a consequence, if two of these inputs are close to each other, a small
offset is imposed on the error amplifier.
CURRENT-LIMIT SCHEME
The ADP1821 employs a unique, programmable, cycle-by-cycle,
lossless current limit circuit that uses an ordinary, inexpensive
resistor to set the threshold. Every switching cycle, the synchronous rectifier turns on for a minimum time and the voltage
drop across the MOSFET RDSON is measured to determine if the
current is too high.
This measurement is done by an internal current limit comparator and an external current limit set resistor. The resistor
is connected between the switch node (that is the drain of the
rectifier MOSFET) and the CSL pin. The CSL pin, which is the
inverting input of the comparator, forces 50 μA through the
resistor to create an offset voltage drop across it.
When the inductor current is flowing in the MOSFET rectifier,
its drain is forced below PGND by the voltage drop across its
RDSON. If the RDSON voltage drop exceeds the preset drop on the
current-limit-set resistor, the inverting comparator input is
similarly forced below PGND and an overcurrent fault is
flagged.
The normal transient ringing on the switch node is ignored
for 100 ns after the synchronous rectifier turns on, so the over
current condition must also persist for 100 ns in order for a
fault to be flagged.
Rev. B | Page 9 of 24
ADP1821
When the ADP1821 senses an overcurrent condition, the next
switching cycle is suppressed, the soft start capacitor is discharged
through an internal 2.5 kΩ resistor, and the error amplifier
output voltage is pulled down. The ADP1821 remains in this
mode for as long as the overcurrent condition persists. When
the overcurrent condition is removed, operation resumes in soft
start mode.
INPUT VOLTAGE RANGE
See the Setting the Current Limit section for more information.
The power input to the dc-to-dc converter can range between
1.2× the output voltage and 24 V. Bypass the power input to
PGND with a suitably large capacitor. See the Selecting the
Input Capacitor section.
MOSFET DRIVERS
The DH pin drives the high-side switch MOSFET. This is a
boosted 5 V gate driver that is powered by a bootstrap capacitor circuit. This configuration allows the high-side, N-channel
MOSFET gate to be driven above the input voltage, allowing full
enhancement and a low voltage drop across the MOSFET. The
bootstrap capacitor is connected from the SW pin to the BST
pin. A bootstrap Schottky diode connected from the PVCC pin
to the BST pin recharges the bootstrap capacitor every time the
SW node goes low. Use a bootstrap capacitor value greater than
100× the high-side MOSFET input capacitance.
In practice, the switch node can run up to 24 V of input voltage,
and the boost nodes can operate more than 5 V above this to
allow full gate drive. The power input voltage can be run from
1 V to 24 V.
The switching cycle is initiated by the internal clock signal. The
high-side MOSFET is turned on by the DH driver, and the SW
node goes high, pulling up on the inductor. When the internally
generated ramp signal crosses the COMP pin voltage, the switch
MOSFET is turned off and the low-side synchronous rectifier
MOSFET is turned on by the DL driver. Active break-beforemake circuitry as well as a supplemental fixed dead time are
used to prevent cross-conduction in the switches.
The DL pin provides the gate drive for the low-side MOSFET
synchronous rectifier. Internal circuitry monitors the external
MOSFETs to ensure break-before-make switching to prevent
cross-conduction. An active dead-time reduction circuit
reduces the break-before-make time of the switching to limit
the losses due to current flowing through the synchronous
rectifier body diode.
The PVCC pin provides power to the low-side drivers. It is
limited to 5.5 V maximum input and should have a local
decoupling capacitor to PGND.
The synchronous rectifier is turned on for a minimum time
of about 200 ns on every switching cycle in order to sense the
current. This and the nonoverlap dead time put a limit on the
maximum high-side switch duty cycle based on the selected
switching frequency. Typically, this is about 90% at 300 kHz
switching, and at 1 MHz switching, it reduces to about 70%
maximum duty cycle.
The ADP1821 takes its internal power from the VCC and PVCC
inputs. PVCC powers the low-side MOSFET gate drive (DL),
and VCC powers the internal control circuitry. Both of these
inputs are limited to between 3.0 V and 5.5 V. Bypass PVCC to
PGND with a 1 μF or greater capacitor. Bypass VCC to GND
with a 0.1 μF or greater capacitor.
SETTING THE OUTPUT VOLTAGE
The output voltage is set using a resistive voltage divider from
the output to FB. The voltage divider drops the output voltage
to the 0.6 V FB regulation voltage to set the regulation output
voltage. The output voltage is set to voltages as low as 0.6 V and
as high as 85% of the minimum power input voltage (see the
Feedback Voltage Divider section).
SWITCHING FREQUENCY CONTROL AND
SYNCHRONIZATION
The ADP1821 has a logic-controlled frequency select input (FREQ)
which sets the switching frequency to 300 kHz or 600 kHz. Drive
FREQ low for 300 kHz and high for 600 kHz.
The SYNC input is used to synchronize the converter switching
frequency to an external signal. The converter switching can be
synchronized to an external signal. This allows multiple ADP1821
converters to be operated at the same frequency to prevent
frequency beating or other interactions.
To synchronize the ADP1821 switching to an external signal,
drive the SYNC input with a synchronizing signal. The ADP1821
can only synchronize up to 2× the nominal oscillator frequency.
If the frequency is set to 300 kHz (FREQ connected to GND),
then the synchronization frequency needs to be in between
300 kHz and 600 kHz. Since the 300 kHz setting has a minimum specification (see Table 1) of 250 kHz and a maximum
of 375 kHz over the specified temperature range, the recommended synchronization frequency range is between 375 kHz
and 500 kHz to cover the whole range of part-to-part variation
and over the operating temperature range. If the frequency is set
to 600 kHz (FREQ connected to VCC), then the synchronization
frequency needs to be in between 600 kHz and 1.2 MHz. Since
the 600 kHz setting has a minimum specification (see Table 1)
of 470 kHz and a maximum of 720 kHz over the specified temperature range, the recommended synchronization frequency
range is between 720 kHz and 940 kHz to cover the whole range
of part-to-part variation and over the operating temperature
range. Driving SYNC faster than recommended for the FREQ
setting results in a small ramp signal, which could affect the
signal-to-noise ratio and the modulator gain and stability.
Rev. B | Page 10 of 24
ADP1821
When an external clock is detected at the first SYNC edge,
the internal oscillator is reset and clock control shifts to SYNC.
The SYNC edges then trigger subsequent clocking of the PWM
outputs. The DH rising edges appear about 320 ns after the corresponding SYNC edge, and the frequency is locked to the
external signal. If the external SYNC signal disappears during
operation, the ADP1821 reverts to its internal oscillator and
experiences a delay of no more than a single cycle of the
internal oscillator.
COMPENSATION
The control loop is compensated by an external series RC
network from COMP to FB and sometimes requires a series
RC in parallel with the top voltage divider resistor. COMP is
the output of the internal error amplifier.
POWER-GOOD INDICATOR
The ADP1821 features an open-drain, power-good output
(PWGD) that sinks current when the output voltage drops 8.3%
below or 25% above the nominal regulation voltage. Two comparators measure the voltage at FB to set these thresholds. The
PWGD comparator directly monitors FB, and the threshold is
fixed at 0.55 V for undervoltage and 0.75 V for overvoltage. The
PWGD output also sinks current if an over temperature or input
undervoltage condition is detected and is operational with VCC
voltage as low as 1.0 V.
Use this output as a logical power-good signal by connecting a
pull-up resistor from PWGD to an appropriate supply voltage.
THERMAL SHUTDOWN
The internal error amplifier compares the voltage at FB to the
internal 0.6 V reference voltage. The difference between the two
(the feedback voltage error) is amplified by the error amplifier.
To optimize the ADP1821 for stability and transient response
for a given set of external components and input/output voltage
conditions, choose the compensation components carefully. For
more information on choosing the compensation components,
see the Compensating the Voltage Mode Buck Regulator
section.
The ADP1821 controller does not generate much heat under
normal conditions, even when driving a relatively large MOSFET.
However, the surrounding power components or other circuits
on the same PCB could heat up the PCB to an unsafe operating
temperature. The ADP1821 controller goes into shutdown and
shuts off the gate drivers when its junction temperature reaches
about 145°C. When the junction temperature drops below
about 135°C, the ADP1821 resumes normal operation in a soft
start mode.
SHUTDOWN CONTROL
The ADP1821 dc-to-dc converter features a low-power shutdown mode that reduces quiescent supply current to 1 μA. To
shut down the ADP1821, drive SHDN low. To turn it on, drive
SHDN high. For automatic startup, connect SHDN to VCC.
Rev. B | Page 11 of 24
ADP1821
APPLICATION INFORMATION
Use the following equation to choose the inductor value:
SELECTING THE INPUT CAPACITOR
The input current to a buck converter is a pulsed waveform. It
is zero when the high-side switch is off and approximately equal
to the load current when it is on. The input capacitor carries the
input ripple current, allowing the input power source to supply
only the dc current. The input capacitor needs sufficient ripple
current rating to handle the input ripple and the equivalent series
resistance (ESR) that is low enough to mitigate input voltage
ripple. For the usual current ranges for these converters, good
practice is to use two parallel capacitors placed close to the drains
of the high-side switch MOSFETs, one bulk capacitor of sufficiently high current rating as calculated in Equation 1, along
with 10 μF of ceramic capacitor.
Select an input bulk capacitor based on its ripple current rating.
First, determine the duty cycle of the output with the larger load
current:
D=
VOUT
VIN
(1)
L=
⎡ V
⎤
1
VOUT ⎢1 − OUT ⎥
f SW × ΔI L
VIN ⎦
⎣
(4)
where:
L is the inductor value.
fSW is the switching frequency.
VOUT is the output voltage.
VIN is the input voltage.
ΔIL is the inductor ripple current, typically 1/3 of the maximum
dc load current.
Choose the output bulk capacitor to set the desired output voltage
ripple. The impedance of the output capacitor at the switching
frequency multiplied by the ripple current gives the output
voltage ripple. The impedance is made up of the capacitive
impedance plus the nonideal parasitic characteristics, the ESR
and the equivalent series inductance (ESL). The output voltage
ripple can be approximated with
2
Second, determine the input capacitor ripple current, which is
approximately
I RIPPLE ≈ I L D (1 − D )
(2)
where:
IL is the maximum inductor or load current for the channel.
D is the duty cycle.
Use this method to determine the input capacitor ripple current
rating for duty cycles between 20% and 80%.
For duty cycles less than 20% or greater than 80%, use an input
capacitor with a ripple current rating:
IRIPPLE > 0.4 IL
(3)
OUTPUT LC FILTER
The output LC filter smoothes the switched voltage at SW,
making the output voltage an almost dc voltage. Choose the
output LC filter to achieve the desired output ripple voltage.
Because the output LC filter is part of the regulator negativefeedback control loop, the choice of the output LC filter
components affects the regulation control loop stability.
Choose an inductor value such that the inductor ripple current
is approximately 1/3 of the maximum dc output load current.
Using a larger value inductor results in a physical size larger
than required and using a smaller value results in increased
losses in the inductor and/or MOSFET switches.
ΔVOUT = ΔI L
⎛
⎞
1
⎟ + (4 f SW ESL)2
ESR + ⎜⎜
⎟
8
f
C
⎝ SW OUT ⎠
2
(5)
where:
ΔVOUT is the output ripple voltage.
ΔIL is the inductor ripple current.
ESR is the equivalent series resistance of the output capacitor
(or the parallel combination of ESR of all output capacitors).
ESL is the equivalent series inductance of the output capacitor
(or the parallel combination of ESL of all capacitors).
Note that the factors of 8 and 4 in Equation 5 would normally
be 2π for sinusoidal waveforms, but the ripple current waveform in this application is triangular. Parallel combinations
of different types of capacitors, for example, a large aluminum
electrolytic in parallel with MLCCs, may give different results.
Usually the impedance is dominated by ESR at the switching
frequency so this equation reduces to
ΔVOUT ≅ ΔI L ESR
(6)
Electrolytic capacitors have significant ESL also, on the order
of 5 nH to 20 nH, depending on type, size, and geometry; and
PCB traces contribute some ESR and ESL as well. However,
using the maximum ESR rating from a capacitor data sheet
usually provides some margin such that measuring the ESL is
not usually required.
Rev. B | Page 12 of 24
ADP1821
In the case of output capacitors where the impedance of the
ESR and ESL are small at the switching frequency, for instance,
where the output capacitor is a bank of parallel MLCC capacitors, the capacitive impedance dominates and the ripple
equation reduces to
ΔVOUT ≅
ΔI L
(7)
8 COUT f SW
Make sure that the ripple current rating of the output capacitors
is greater than the maximum inductor ripple current.
During a load step transient on the output, the output capacitor
supplies the load until the control loop has a chance to ramp the
inductor current. This initial output voltage deviation due to a
change in load is dependent on the output capacitor characteristics. Again, usually the capacitor ESR dominates this response,
and the ΔVOUT in Equation 6 can be used with the load step
current value for ΔIL.
SELECTING THE MOSFETS
The choice of MOSFET directly affects the dc-to-dc converter
performance. The MOSFET must have low on resistance to reduce
I2R losses and low gate charge to reduce transition losses. In
addition, the MOSFET must have low thermal resistance to
ensure that the power dissipated in the MOSFET does not result
in excessive MOSFET die temperature.
The high-side MOSFET carries the load current during on-time
and carries all the transition losses of the converter. Typically,
the lower the MOSFET on resistance, the higher the gate charge
and vice versa. Therefore, it is important to choose a high-side
MOSFET that balances the two losses. The conduction loss of
the high-side MOSFET is determined by the equation
⎛V
PC ≅ (I LOAD )2 R DSON ⎜⎜ OUT
⎝ V IN
⎞
⎟
⎟
⎠
(8)
where:
PC = conduction power loss.
RDSON = MOSFET on resistance.
The total power dissipation of the high-side MOSFET is the
sum of all the previous losses, or
PD ≅ PC + PG + PT
where PD is the total high-side MOSFET power loss.
The conduction losses may need an adjustment to account
for the MOSFET RDSON variation with temperature. Note that
MOSFET RDSON increases with increasing temperature. A MOSFET
data sheet should list the thermal resistance of the package, θJA,
along with a normalized curve of the temperature coefficient of
the RDSON. For the power dissipation estimated above, calculate
the MOSFET junction temperature rise over the ambient
temperature of interest.
TJ = TA + θJAPD
RDSON @ TJ = RDSON @ 25°C(1 + TC(TJ − 25°C))
where:
PG = gate charging loss power.
VPVCC = gate driver supply voltage.
QG = MOSFET total gate charge.
fSW = converter switching frequency.
The high-side MOSFET transition loss is approximated by the
equation
PT =
VIN I LOAD (t R + t F ) f SW
2
(13)
Then the conduction losses can be recalculated and the procedure iterated once or twice until the junction temperature
calculations are relatively consistent.
The synchronous rectifier, or low-side MOSFET, carries the
inductor current when the high-side MOSFET is off. The lowside MOSFET transition loss is small and can be neglected in
the calculation. For high input voltage and low output voltage,
the low-side MOSFET carries the current most of the time.
Therefore, to achieve high efficiency, it is critical to optimize
the low-side MOSFET for low on resistance. In cases where the
power loss exceeds the MOSFET rating or lower resistance is
required than is available in a single MOSFET, connect multiple
low-side MOSFETs in parallel. The equation for low-side
MOSFET power loss is
⎤
⎡ V
PLS ≅ (I LOAD )2 RDSON ⎢1 − OUT ⎥
VIN ⎦
⎣
(9)
(12)
Then calculate the new RDSON from the temperature coefficient curve and the RDSON spec at 25°C. A typical value of the
temperature coefficient (TC) of the RDSON is 0.004/°C, so an
alternate method to calculate the MOSFET RDSON at a second
temperature, TJ, is
The gate charging loss is approximated by the equation
PG ≅ V PVCC Q G f SW
(11)
(14)
where:
PLS is the low-side MOSFET on resistance.
RDSON is the total on resistance of the low-side MOSFET(s).
Check the gate charge losses of the synchronous rectifier
using the PG equation (Equation 9) to be sure it is reasonable.
If multiple low-side MOSFETs are used in parallel, then use
the parallel combination of the on resistances for determining
RDSON to solve this equation.
(10)
where:
PT = high-side MOSFET switching loss power.
tR = MOSFET rise time.
tF = MOSFET fall time.
Rev. B | Page 13 of 24
ADP1821
SETTING THE CURRENT LIMIT
FEEDBACK VOLTAGE DIVIDER
The current limit comparator measures the voltage across the
low-side MOSFET to determine the load current.
The output regulation voltage is set through the feedback
voltage divider. The output voltage is reduced through the
voltage divider and drives the FB feedback input. The regula
tion threshold at FB is 0.6 V. The maximum input bias current
into FB is 100 nA. For a 0.15% degradation in regulation voltage
and with 100 nA bias current, the low-side resistor, RBOT, needs
to be less than 9 kΩ, which results in 67 μA of divider current.
For RBOT, use 1 kΩ to 10 kΩ. A larger value resistor can be used,
but results in a reduction in output voltage accuracy due to the
input bias current at the FB pin, while lower values cause increased
quiescent current consumption. Choose RTOP to set the output
voltage by using the following equation:
The current limit is set through the current limit resistor, RCL.
CSL, the current sense pin, sources 50 μA through RCL. This
creates an offset voltage of RCL multiplied by the 50 μA CSL
current. When the drop across the low-side MOSFET RDSON is
equal to or greater than this offset voltage, the ADP1821 flags
a current-limit event.
Because the CSL current and the MOSFET RDSON vary over process
and temperature, the minimum current limit should be set to
ensure that the system can handle the maximum desired load
current. To do this, use the peak current in the inductor, which
is the desired current-limit level plus the ripple current, the
maximum RDSON of the MOSFET at its highest expected temperature, and the minimum CSL current.
RCL =
I LPK RDSON (MAX )
42 μA
(15)
where ILPK is the peak inductor current.
When an over-current event occurs, the over-current comparator does prevent switching cycles until the rectifier current has
decayed below the threshold. The over-current comparator is
blanked for the first 100 ns of the synchronous rectifier cycle to
prevent switch node ringing from falsely tripping the current
limit. The ADP1821 senses the current limit during the off
cycle. When the current limit condition occurs, the ADP1821
resets the internal clock until the over-current condition
disappears. This suppresses the start clock cycles until the
overload condition is removed. At the same time, the SS cap
is discharged through a 2.5 kΩ resistor. The SS input is an
auxiliary positive input of the error amplifier, so it behaves
like another voltage reference. The lowest reference voltage
wins. Discharging the SS voltage causes the converter to use
a lower voltage reference when switching is allowed again.
Therefore, as switching cycles continue around the current
limit, the output looks roughly like a constant current source
due to the rectifier limit, and the output voltage droops as the
load resistance decreases. When the overload condition is
removed, the output recovers with the normal soft start slope
and does not overshoot.
Because the buck converter is usually running at a fairly high
current, PCB layout and component placement may affect
the current-limit setting. An iteration of the RCL values may be
required for a particular board layout and MOSFET selection.
If alternate MOSFETs are substituted at some point in production,
the values of the RCL resistor may also need an iteration.
⎛ VOUT _ VFB
RTOP = R BOT ⎜
⎜
VFB
⎝
⎞
⎟
⎟
⎠
(16)
where:
RTOP is the high-side voltage divider resistance.
RBOT is the low-side voltage divider resistance.
VOUT is the regulated output voltage.
VFB is the feedback regulation threshold, 0.6 V.
COMPENSATING THE VOLTAGE MODE BUCK
REGULATOR
Assuming the LC filter design is complete, the feedback control
system can then be compensated. Good compensation is critical
to proper operation of the regulator. Calculate the quantities in
Equation 17 through Equation 58 to derive the compensation
values. For convenience, a summary of the design equations is
located in the Summary of Equations section. The information
can then be added to an Excel spreadsheet, for automated
calculation.
The goal is to guarantee that the voltage gain of the buck converter crosses unity at a slope that provides adequate phase
margin for stable operation. Additionally, at frequencies
above the crossover frequency, fCO, guaranteeing sufficient
gain margin and attenuation of switching noise are important
secondary goals. For initial practical designs, a good choice for
the crossover frequency is one tenth of the switching frequency;
so first calculate
f CO =
f SW
10
(17)
This gives sufficient frequency range to design a compensation
that attenuates switching artifacts, while also giving sufficient
control loop bandwidth to provide good transient response.
The output LC filter is a resonant network that inflicts two poles
upon the response at a frequency fLC, so next calculate
f LC =
Rev. B | Page 14 of 24
1
2π LC
(18)
ADP1821
Generally speaking, the LC corner frequency is about two
orders of magnitude below the switching frequency, and
therefore about one order of magnitude below crossover.
To achieve sufficient phase margin at crossover to guarantee
stability, the design must compensate for the two poles at the
LC corner frequency with two zeros to boost the system phase
prior to crossover. The two zeros require an additional pole or
two above the crossover frequency to guarantee adequate gain
margin and attenuation of switching noise at high frequencies.
To compensate the control loop, the gain of the system must
be brought back up so that it is 0 dB at the desired crossover
frequency. Some gain is provided by the PWM modulation
itself, so next calculate
⎛ V
AMOD = 20 log ⎜⎜ IN
⎝ VRAMP
f ESR =
(19)
2π RESRCOUT
⎛ V
⎞
AMOD = 20 log⎜ IN ⎟
⎜ 1.25 V ⎟
⎝
⎠
⎛ f
VRAMP = 1.25 V ⎜⎜ FREQ
⎝ f SYNC
Figure 15 shows a typical bode plot of the LC filter by itself.
fLC
fESR
fCO
fSW
FREQUENCY
AT = AMOD + AFILTER + ACOMP
–40dB/dec
–20dB/dec
AFILTER
0°
–90°
05310-015
ΦFILTER
–180°
Figure 15. LC Filter Bode Plot
The gain of the LC filter at crossover can be linearly
approximated from Figure 15 as
AFILTER = ALC + AESR
⎞
⎛ f
⎟ − 20 dB × log ⎜ CO
⎟
⎜f
⎠
⎝ ESR
(23)
(24)
where:
AMOD is the gain of the PWM modulator
AFILTER is the gain of the LC filter including the effects of the
ESR zero
ACOMP is the gain of the compensated error amplifier.
PHASE
⎛f
AFILTER = − 40 dB × log ⎜⎜ ESR
⎝ f LC
⎞
⎟
⎟
⎠
The rest of the system gain needed to reach 0 dB at crossover is
provided by the error amplifier and is covered in the compensation design information that follows. The total gain of the
system therefore, is given by
LC FILTER BODE PLOT
0dB
(22)
Note that if the converter is being synchronized, the ramp
voltage, VRAMP, is lower than 1.25 V by the percentage of
frequency increase over the nominal setting of the FREQ pin:
This zero is often near or below crossover and is useful in
bringing back some of the phase lost at the LC corner.
GAIN
(21)
For systems using the internal oscillator, this becomes
Depending on component selection, one zero might already be
generated by the ESR of the output capacitor. Calculate this zero
corner frequency, fESR, as
1
⎞
⎟
⎟
⎠
⎞
⎟
⎟
⎠
Additionally, the phase of the system must be brought back up
to guarantee stability. Note from the bode plot of the filter that
the LC contributes −180 degrees of phase shift. Additionally,
because the error amplifier is an integrator at low frequency,
it contributes an initial −90 degrees. Therefore, before adding
compensation or accounting for the ESR zero, the system is
already down −270 degrees. To avoid loop inversion at crossover, or −180 degrees phase shift, a good initial practical design
is to require a phase margin of 60 degrees, which is therefore an
overall phase loss of −120 degrees from the initial low frequency
dc phase. The goal of the compensation is to boost the phase
back up from −270 degrees to −120 degrees at crossover.
Two common compensation schemes are used, which are
sometimes referred to as Type II or Type III compensation,
depending on whether the compensation design includes
two or three poles. (Dominant pole compensations, or single
pole compensation, is referred to as Type I compensation, but
unfortunately it is not very useful for dealing successfully with
switching regulators.)
(20)
If fESR ≈ fCO, then add another 3 dB to account for the local
difference between the exact solution and the preceding linear
approximation.
Rev. B | Page 15 of 24
ADP1821
If the zero produced by the ESR of the output capacitor provides sufficient phase boost at crossover, Type II compensation
is adequate. If the phase boost produced by the ESR of the output
capacitor is not sufficient, another zero is added to the compensation network, and thus Type III is used. A general rule to
determine the scheme whether the phase contribution of the
ESR zero is greater than 70 degrees at crossover.
Note in the compensator phase expression shown in Equation 27,
the −90 degree term is the phase contributed by the initial integrator pole. The φP is the additional phase contributed by the
high frequency compensation poles placed above crossover, and
φZ is the phase contributed by the compensation zeros placed
below crossover. For the system to be stable at crossover, phase
boost is required from the compensator.
In Figure 16, the location of the ESR zero corner frequency gives
significantly different net phase at the crossover frequency.
For stability, the total phase at crossover is designed to be equal
to −120 degrees
LC FILTER BODE PLOT
PHASE CONTRIBUTION AT CROSSOVER
OF VARIOUS ESR ZERO CORNERS
GAIN
0dB
fLC fESR1 fESR2 fESR3 fCO
fSW
(28)
−120 = −180 + φESR + −90 + φP + φZ
(29)
Define phase boost, φB, to be that portion of the phase at
crossover contributed by the compensator’s higher order
poles and zeros:
FREQUENCY
–40dB/dec
φT = φLC + φESR + φCOMP
–20dB/dec
φB = φP + φZ
(30)
φB = 150 − φESR
(31)
D. Venable, in his article “The K Factor: A New Mathematical
Tool for Stability Analysis and Synthesis,” 1983, showed that an
optimum compensation solution was to place the zeros and
poles symmetrically around the crossover frequency. He derived
a factor known as K with which the frequencies of the compensation zeros and poles may be calculated. K is calculated for the
type of compensation selected Figure 17.
PHASE
0°
Type II Compensator
Φ1
G
(dB)
–90°
LO
PHASE
Φ2
PE
fZ
LO
PE
fP
–270°
CHF
Figure 16. LC Filter Bode Plot
RZ
FROM
VOUT
(25)
CI
RTOP
RBOT
EA
VRAMP
VREF
If φESR ≥ 70, then Type II compensation is adequate.
0V
If φESR < 70, use Type III, as an additional zero is needed.
Figure 17. Type II Compensation
The total phase of the system at crossover is the sum of the
contributing elements, namely
φT = φLC + φESR + φCOMP
where:
φLC = −180.
φESR is as calculated in Equation 25.
φCOMP = −90 + φP + φZ
TO PWM
COMP
05310-017
Using a linear approximation from Figure 16, the phase contribution of the ESR zero at crossover can be estimated by
10 × fCO
ϕESR = 45 × log
f ESR
–1
S
–180°
05310-016
Φ3
–180°
–1
S
To calculate K for Type II compensation use
φ
K = tan⎛⎜ B + 45 ⎞⎟
⎝ 2
⎠
(26)
(27)
(32)
Values of K between 4 and 15 are practical for implementation,
so if the selected type of compensation does not yield a reasonable value of K, try the other type.
Rev. B | Page 16 of 24
ADP1821
From K, the frequency of the added zeros, fZ, is below crossover
for Type II by
(33)
(37)
0 dB = AMOD + AFILTER + ACOMP
(38)
ACOMP = 0 dB − AMOD − AFILTER
(39)
fP
RZ
CI
EA
RBOT
COMP
⎞
⎟
⎟
⎠
⎛ ACOMP ⎞
⎟
⎜
⎝ 20 ⎠
1
2π R Z f Z
TO PWM
VRAMP
0V
φ
⎞
⎛
K = ⎜ tan ⎛⎜ B + 45 ⎞⎟ ⎟
⎝ 2
⎠⎠
⎝
fZ =
2
f CO
K
fP = fCO √K
(44)
(45)
(46)
Select RTOP between 1 k and 10 k. A good starting value is 2 k.
(40)
Next, calculate RBOT as
R BOT =
(41)
Calculate the integrator cap value to place the compensation
zero at the desired frequency using the following equation:
RBOT =
(42)
C FF =
(43)
VFB RTOP
VOUT − VFB
0.6 V × RTOP
VOUT − 0.6 V
(47)
(48)
Calculate the feedforward capacitor to produce the first
compensator zero
Calculate the capacitor value for the high frequency pole by
C HF
PE
Figure 18. Type III Compensation
Calculate the value of RZ to achieve that gain
1
=
2π R Z f P
–1
SL
O
VREF
AT = AMOD + AFILTER + ACOMP
CI =
PE
RTOP
FROM
VOUT
Calculate the compensator gain needed at crossover to achieve
0 dB total system gain:
R Z = RTOP × 10
CFF
(36)
VOUT − 0.6 V
⎛ R
ACOMP = 20 × log⎜⎜ Z
⎝ RTOP
fZ
RFF
(35)
0.6 V × RTOP
LO
CHF
Next, calculate RBOT as
RBOT =
S
+1
–270°
(34)
VFB RTOP
VOUT − VFB
PE
PHASE
Select RTOP between 1 k and 10 k. A good starting value is 2 k.
R BOT =
LO
–90°
Similarly, the frequency of the added poles, fP, should be
previous crossover by for Type II
fP = fCOK
–1
S
G
(dB)
05310-018
f
f Z = CO
K
Type III Compensator
1
2π RTOP f Z
(49)
Calculate the resistor of the feedforward network to provide the
first high frequency compensator pole
RFF =
1
2π C FF f P
(50)
Calculate the impedance of the feedforward network at the
crossover frequency, as this is required to set the gain of the
compensator.
Z FF =
Rev. B | Page 17 of 24
1
+ RFF
2π C FF f CO
(51)
ADP1821
Calculate the compensator gain needed at crossover to achieve
0 dB total system gain:
AT = AMOD + AFILTER + ACOMP
(52)
0 dB = AMOD + AFILTER + ACOMP
(53)
ACOMP = 0 dB − AMOD − AFILTER
(54)
SETTING THE SOFT START PERIOD
The ADP1821 uses an adjustable soft start to limit the output
voltage ramp-up period, limiting the input inrush current. The
soft start is set by selecting the capacitor, CSS, from SS to GND.
The ADP1821 charges CSS to 0.8 V through an internal 100 kΩ
resistor. The voltage on CSS while it is charging is
Calculate the value of RZ to achieve the previous gain by
ACOMP
⎛
RZ
= 20 × log⎜⎜
⎝ RTOP || Z FF
R Z = (RTOP || Z FF )
⎞
⎟
⎟
⎠
⎛ ACOMP ⎞
⎟
⎜
× 10 ⎝ 20 ⎠
VCSS
(55)
1
2π RZ f Z
(56)
1
2π RZ f P
(59)
The soft start period, tSS, is achieved when VCSS = 0.6 V or
(57)
(58)
t SS
⎛
⎞
100 kΩ(CSS ) ⎟
⎜
0.6 V = 0.8 V⎜1 − e
⎟
⎝
⎠
(60)
⎛ 0.6 V ⎞
t SS
⎟ = 1.386
= − 1n⎜ 1 −
⎜ 0.8 V ⎟
100 kΩ(CSS )
⎝
⎠
(61)
or
Calculate the capacitor value for the high frequency pole by
CHF =
⎞
⎟
⎟
⎠
where R is the internal 100 kΩ resistor.
Calculate the integrator capacitor value to place the compensation zero at the desired frequency:
CI =
t
⎛
RCSS
⎜
= 0.8 V 1 − e
⎜
⎝
Solve for CSS by
Check that the calculated component values are reasonable.
For instance, capacitors smaller than about 10 pF should be
avoided. In addition, the ADP1821 error amplifier has finite
output current drive, so RZ values less than a few kilohm and CI
values greater than 10 nF should be avoided. If necessary, recalculate the compensation network with a different starting value
of RTOP. If CHF is too small, start with a smaller value RTOP. If RZ
is too small and CI is too big, start with a larger value of RTOP.
Rev. B | Page 18 of 24
CSS = tSS × 7.21 μF/sec
(62)
ADP1821
PCB LAYOUT GUIDELINE
In any switching converter, there are some circuit paths that
carry high dI/dt, which can create spikes and noise. Other
circuit paths are sensitive to noise and still others carry high
dc current and can produce significant IR voltage drops. The
key to proper PCB layout of a switching converter is to identify
these critical paths and arrange the components and copper
area accordingly. When designing PCB layouts, be sure to keep
high current loops small. In addition, keep compensation and
feedback components away from the switch nodes and their
associated components.
The following is a list of recommended layout practices for
ADP1821, arranged in approximately decreasing order of
importance. A PCB layout example of the circuit shown in
Figure 22 is shown in Figure 19 and Figure 20.
•
The current waveform in the top and bottom FETs is a pulse
with very high dI/dt, so the path to, through, and from each
individual FET should be as short as possible and the two
paths should be as similar as possible. In designs that use
a pair of D-Paks or SO-8 FETs on one side of the PCB, it is
best to counter-rotate the two so that the switch node is on
one side of the pair and the high side drain can be bypassed
to the low side source with a suitable ceramic bypass capacitor,
placed as close as possible to the FETs in order to minimize
inductance around this loop through the FETs and capacitor.
The recommended bypass ceramic capacitor values range
from 1 μF to 22 μF depending upon the output current. This
bypass capacitor is usually connected to a larger value bulk
filter capacitor and should be grounded to the PGND plane.
•
GND, VCC bypass, PVCC bypass, soft start capacitor, and
the bottom end of the output feedback divider resistors should
be tied to an almost isolated, small AGND plane. All of
these connections to the AGND plane should be kept as
short as possible. No high current or high dI/dt signals
should be connected to this AGND plane. The AGND
area should be connected through one wide trace to the
negative terminal of the output filter capacitors.
•
The PGND pin handles high dI/dt gate drive current
returning from the source of the low side MOSFET. The
voltage at this pin also establishes the 0 V reference for the
over-current limit protection (OCP) function and the CSL
pin. A small PGND plane should connect the PGND pin
and the PVCC bypass capacitor through a wide and direct
path to the source of the low side MOSFET. The placement
of CIN is critical for controlling ground bounce. The negative
terminal of CIN needs to be placed very close to the source of
the low-side MOSFET.
•
Avoid long traces or large copper areas at the FB and CSL
pins, which are low, signal-level inputs that are sensitive to
capacitive and inductive noise pickup. It is best to position
any series resistors and capacitors as closely as possible to
these pins. Avoid running these traces close and parallel to
high dI/dt traces.
•
The switch node is the noisiest place in the switcher circuit
with large ac and dc voltage and current. This node should
be wide to keep resistive voltage drop down. But to minimize the generation of capacitively coupled noise, the total
area should be small. Place the FETs and inductor close
together on a small copper plane in order to minimize series
resistance and keep the copper area small.
•
Gate drive traces (DH and DL) handle high dI/dt and
tend to produce noise and ringing. They should be as
short and direct as possible. If possible, avoid using feedthrough vias in the gate drive traces. If vias are needed, it
is best to use two relatively large ones in parallel to reduce
the peak current density and the current in each via. If the
overall PCB layout is less than optimal, slowing down the
gate drive slightly can be very helpful to reduce noise and
ringing. It is occasionally helpful to place small value resistors
(such as 5 Ω or 10 Ω) in series with the gate leads, mainly
DH traces to the high side FET gates. These can be populated with 0 Ω resistors if resistance is not needed. Note that
the added gate resistance increases the switching rise and
fall times, and that also increases the switching power loss
in the MOSFET.
•
The negative terminal of output filter capacitors should be
tied closely to the source of the low side FET. Doing this
helps to minimize voltage difference between GND and
PGND at the ADP1821.
•
Generally be sure that all traces should be sized according
to the current being handled as well as their sensitivity in
the circuit. Standard PCB layout guidelines mainly address
heating effects of current in a copper conductor. While
these are completely valid, they do not fully cover other
concerns such as stray inductance or dc voltage drop. Any
dc voltage differential in connections between ADP1821
GND and the converter power output ground can cause a
significant output voltage error, as it affects converter output
voltage according to the ratio with the 600 mV feedback
reference. For example, a 6 mV offset between ground on
the ADP1821 and the converter power output causes a 1%
error in the converter output voltage.
Rev. B | Page 19 of 24
ADP1821
05310-020
VIA TO 2 LAYER
SOME TRACES ARE OMITTED FOR CLARITY
Figure 19. Top Layer Layout Example of Circuit (see Figure 22)
Figure 20. Bottom Layer Layout Example of Circuit (See Figure 22)
RECOMMENDED COMPONENT MANUFACTURERS
Table 4.
Vendor
AVX Corporation
Central Semiconductor Corp.
Coilcraft®, Inc.
Diodes, Inc.
International Rectifier
Murata Manufacturing Co., Ltd.
ON Semiconductor®
Rubycon Corporation
Sanyo
Sumida Corporation
Taiyo Yuden, Inc.
Toko America, Inc.
United Chemi-Con, Inc.
Vishay Siliconix
PGND
05310-019
AGND
Components
Capacitors
Diodes
Inductors
Diodes
Diodes, MOSFETs
Capacitors, inductors
Diodes, MOSFETs
Capacitors
Capacitors
Inductors
Capacitors, inductors
Inductors
Capacitors
Diodes, MOSFETs, resistors, capacitors
Rev. B | Page 20 of 24
ADP1821
APPLICATION CIRCUITS
The ADP1821 controller can be configured to regulate an output
with a load of more than 20 A if the power components, such
as the inductor, MOSFETs, and the bulk capacitors, are chosen
carefully to meet the power requirement. The maximum load
and power dissipation are limited by the power-train components. Figure 1 shows a typical application circuit that can drive
an output load of 20 A. Note that two low-side MOSFETs are
needed to deliver the 20 A load. In this example, two power rails
are needed: a 5 V bias supply, which needs to supply about 30
mA to power the ADP1821 at full load, and a power input rail,
which ranges from 2.5 V to 20 V. The bulk input and output
capacitors used in this example are Sanyo’s OSCONTM capacitors, which have low ESR and high-current ripple rating. An
alternative to the OSCON capacitors are the polymer aluminum
capacitors that are available from other manufacturers such as
United Chemi-Con. Aluminum electrolytic capacitors, such as
Rubycon’s ZLG low-ESR series, can also be paralleled up at the
input or output to meet the current ripple requirement. Since
the aluminum electrolytic capacitors have higher ESR and much
larger variation in capacitance over the operating temperature
range, a larger bulk input and output capacitance is needed to
reduce the effective ESR and suppress the current ripple.
The ADP1821 can be configured to drive an output load of
less than 1 A. Figure 21 shows a typical application circuit that
drives a 3 A load in an all multilayer ceramic capacitor (MLCC)
solution. Notice that the two MOSFETs used in this example are
dual-channel MOSFETs in a PowerPAK® SO-8 package, which
reduces cost and saves layout space. For input voltages less than
3.7 V, it is recommended to use MOSFETs that are fully turned
on at VGS less than 3 V. Because there’s a forward voltage (VF)
drop across the Schottky diode D1, for input voltages less than
3.3 V, the effective voltage to the internal gate drivers may not
be enough to drive a large load at the output. A Schottky diode
with VF less than 0.5 V at IF of 100 mA is recommended for
input voltages less than 3.3 V.
VIN = 3V TO 5.5V
1µF
+
D1
10Ω
VCC
1µF
+
PVCC
CIN2
10µF
10V
×2
ADP1821
SHDN
BST
DH
FREQ
100kΩ
CIN1
1µF
10V
SW
SYNC
PWGD
CSL
DL
COMP
0.22µF
M1
L1 = 2.2µH
M2
PGND
6.65kΩ
SS
OUTPUT
1.8V, 3A
4.1kΩ
COUT1
1µF
10V
COUT2
47µF
6.3V
COUT3
100µF
6.3V
GND FB
84.5Ω
8.2nF
2kΩ
120pF
1.5nF
100nF
1kΩ
AGND
L1: TOKO, FDV0620-2R2M
COUT2: MURATA, GRM31CR60J476M
CIN2: MURATA, GRM21BR61A106K
D1: CENTRAL SEMI, CMDSH2-4L
COUT3: MURATA, GRM31CR60J107M
M1, M2: VISHAY, DUAL-CHANNEL MOSFET Si7940DP
05310-021
fSW = 600kHz
Figure 21. Typical Application Circuit with all Multilayer Ceramic Capacitors (MLCC), 3.3 V to 5 V Input
Rev. B | Page 21 of 24
ADP1821
The ADP1821 can also be configured to run with an input voltage
higher than 5.5 V. Figure 22 shows a typical application circuit
that operates from a 12 V input. An external LDO is built, with
a NPN, a 5.6 V Zener diode and a resistor, to step down the
R7
10Ω
C6
1µF
D1
VCC
R5
1.2kΩ
PVCC
BST
DH
SW
SYNC
PWGD
CSL
C4
0.22µF
M2
PGND
SS
+
CIN2
180µF
20V
M1
L1 = 2.2µH
R4 3.3kΩ
DL
COMP
INPUT
12V
CIN1
10µF
16V
ADP1821
FREQ
R8
82kΩ
D2
C5
1µF
SHDN
R6
100kΩ
Q1
OUTPUT
1.8V, 10A
COUT1
10µF +
6.3V
×2
COUT2
680µF
4V
×2
GND FB
R1
20kΩ
C2
18pF
C3
1nF
fSW = 300kHz
CSS
100nF AGND
R3
2.7kΩ
C1
1.8nF
R2
10kΩ
CIN2: SANYO, OSCON 20SP180M
COUT2: SANYO, OSCON 4SEPC680M
D2: CENTRAL SEMI, CMOZ5V6, 5.6V ZENER
L1: COILTRONICS, HC7-2R2
Q1: CENTRAL SEMI, CMST2222A, NPN
D1: CENTRAL SEMI, CMDSH2-4L
M1, M2: IRFR3709Z
Figure 22. Typical Application Circuit, 12 V Input
Rev. B | Page 22 of 24
05310-022
VE
input voltage from 12 V to 5 V to power the ADP1821. These
external signal components are cheap and small in size. Alternatively, LDOs such as the ADP3300 or the ADP3330 in a small
SOT-23 package can be used for input voltages up to 12 V.
ADP1821
SUMMARY OF EQUATIONS
⎛ ACOMP ⎞
⎜
⎟
20 ⎠
The following equations are for the reference and convenience
of the user. Equations are replicated from the Compensating the
Voltage Mode Buck Regulator section.
RZ = RTOP × 10 ⎝
COMPENSATION EQUATIONS
CI =
See the Compensating the Voltage Mode Buck Regulator
section.
fCO =
f LC =
f ESR =
1
2π RZ f Z
C HF =
f SW
10
1
2π RZ f P
TYPE III COMPENSATION EQUATIONS
1
2π LC
See the Type III Compensator section.
φ
⎞
⎛
K = ⎜ tan ⎛⎜ B + 45 ⎞⎟ ⎟
⎝ 2
⎠⎠
⎝
1
2π R ESR COUT
fCO
K
fZ =
⎛f ⎞
⎛ f ⎞
AFILTER = −40 dB × log⎜⎜ ESR ⎟⎟ − 20 dB × log⎜⎜ CO ⎟⎟
⎝ f LC ⎠
⎝ f ESR ⎠
2
fP = fCO √K
AMOD
⎛ V
= 20 log⎜⎜ IN
⎝ VRAMP
⎞
⎟
⎟
⎠
Select RTOP between 1 k and 10 k. A good starting value is 2 k.
0.6 V × RTOP
10 × fCO
ϕESR = 45 × log
f ESR
RBOT =
ϕB =150 − ϕ ESR
CFF =
1
2π RTOP f Z
RFF =
1
2π CFF f P
Z FF =
1
+ RFF
2π CFF f CO
If ϕESR ≥ 70 , use Type II compensation.
If ϕ ESR < 70 , use Type III compensation.
TYPE II COMPENSATION EQUATIONS
See the Type II Compensator section.
⎛φ
⎞
K = tan⎜ B + 45 ⎟
2
⎝
⎠
ACOMP = 0 dB − AMOD − AFILTER
⎛ ACOMP ⎞
⎜
⎟
20 ⎠
RZ = (RTOP || Z FF ) × 10⎝
f
f Z = CO
K
CI =
fP = fCOK
Select RTOP between 1 k and 10 k; a good starting value is 2 k.
RBOT =
VFB RTOP
VOUT − VFB
VOUT − 0.6 V
1
2π RZ f Z
C HF =
ACOMP = 0 dB − AMOD − AFILTER
Rev. B | Page 23 of 24
1
2π RZ f P
ADP1821
OUTLINE DIMENSIONS
0.197
0.193
0.189
9
16
0.158
0.154
0.150
1
8
0.244
0.236
0.228
PIN 1
0.069
0.053
0.065
0.049
0.010
0.025
0.004
BSC
COPLANARITY
0.004
0.012
0.008
SEATING
PLANE
0.010
0.006
8°
0°
0.050
0.016
COMPLIANT TO JEDEC STANDARDS MO-137-AB
Figure 23. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches
ORDERING GUIDE
Model
ADP1821ARQZ-R7 1
ADP1821-EVAL
1
Temperature Range
–40°C to +85°C
Package Description
16-Lead Shrink Small Outline Package [QSOP]
Evaluation Board
Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05310-0-12/06(B)
Rev. B | Page 24 of 24
Package Option
RQ-16
Quantity
1000