AD ADP2386

20 V, 6 A, Synchronous Step-Down
DC-to-DC Regulator
ADP2386
Data Sheet
FEATURES
TYPICAL APPLICATIONS CIRCUIT
ADP2386
VIN
BST
PVIN
CIN
CBST
EN
VOUT
PGOOD
COUT
RTOP
SYNC
FB
RT
RT
L
SW
COMP
VREG
CVREG
SS
GND
PGND
RC
RBOT
CC
CSS
10211-001
Input voltage: 4.5 V to 20 V
Integrated MOSFET: 44 mΩ/11 mΩ
Reference voltage: 0.6 V ± 1%
Continuous output current: 6 A
Programmable switching frequency: 200 kHz to 1.4 MHz
Synchronizes to external clock: 200 kHz to 1.4 MHz
180° out of phase clock synchronization
Precision enable and power good
External compensation
Internal soft start with external adjustable option
Startup into a precharged output
Supported by ADIsimPower design tool
Figure 1.
APPLICATIONS
100
Communications infrastructure
Networking and servers
Industrial and instrumentation
Healthcare and medical
Intermediate power rail conversion
DC-to-dc point-of-load applications
95
90
EFFICIENCY (%)
85
80
75
70
65
60
50
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
10211-002
VOUT = 5.0V
VOUT = 3.3V
VOUT = 1.2V
55
Figure 2. Efficiency vs. Output Current, VIN = 12 V, fSW = 300 kHz
GENERAL DESCRIPTION
The ADP2386 is a synchronous step-down, dc-to-dc regulator with
an integrated 44 mΩ, high-side power MOSFET and an 11 mΩ,
synchronous rectifier MOSFET to provide a high efficiency
solution in a compact 4 mm × 4 mm LFCSP package. This device
uses a peak current mode, constant frequency pulse-width
modulation (PWM) control scheme for excellent stability and
transient response. The switching frequency of the ADP2386
can be programmed from 200 kHz to 1.4 MHz. To minimize
system noise, the synchronization function allows the switching
frequency to be synchronized to an external clock.
The ADP2386 requires minimal external components and
operates from an input voltage of 4.5 V to 20 V. The output
voltage can be adjusted from 0.6 V to 90% of the input voltage
Rev. A
and delivers up to 6 A of continuous current. Each IC draws less
than 110 μA current from the input source when it is disabled.
This regulator targets high performance applications that require
high efficiency and design flexibility. External compensation and an
adjustable soft start function provide design flexibility. The powergood output and precision enable input provide simple and reliable
power sequencing.
Other key features include undervoltage lockout (UVLO),
overvoltage protection (OVP), overcurrent protection (OCP),
short-circuit protection (SCP), and thermal shutdown (TSD).
The ADP2386 operates over the −40°C to +125°C junction
temperature range and is available in a 24-lead, 4 mm × 4 mm
LFCSP package.
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ADP2386
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Shutdown .................................................................... 14
Applications ....................................................................................... 1
Applications Information .............................................................. 15
Typical Applications Circuit............................................................ 1
Input Capacitor Selection .......................................................... 15
General Description ......................................................................... 1
Output Voltage Setting .............................................................. 15
Revision History ............................................................................... 2
Voltage Conversion Limitations ............................................... 15
Specifications..................................................................................... 3
Inductor Selection ...................................................................... 15
Absolute Maximum Ratings ............................................................ 5
Output Capacitor Selection....................................................... 16
Thermal Resistance ...................................................................... 5
Programming the Input Voltage UVLO.................................. 17
ESD Caution .................................................................................. 5
Compensation Design ............................................................... 17
Pin Configuration and Function Descriptions ............................. 6
ADIsimPower Design Tool ....................................................... 17
Typical Performance Characteristics ............................................. 7
Design Example .............................................................................. 18
Functional Block Diagram ............................................................ 11
Output Voltage Setting .............................................................. 18
Theory of Operation ...................................................................... 12
Frequency Setting ....................................................................... 18
Control Scheme .......................................................................... 12
Inductor Selection ...................................................................... 18
Precision Enable/Shutdown ...................................................... 12
Output Capacitor Selection....................................................... 19
Internal Regulator (VREG) ....................................................... 12
Compensation Components ..................................................... 19
Bootstrap Circuitry .................................................................... 12
Soft Start Time Program ........................................................... 19
Oscillator ..................................................................................... 12
Input Capacitor Selection .......................................................... 19
Synchronization .......................................................................... 12
Recommended External Components .................................... 20
Soft Start ...................................................................................... 13
Circuit Board Layout Recommendations ................................... 21
Power Good ................................................................................. 13
Typical Applications Circuits ........................................................ 22
Peak Current-Limit and Short-Circuit Protection................. 13
Outline Dimensions ....................................................................... 23
Overvoltage Protection (OVP) ................................................. 14
Ordering Guide .......................................................................... 23
Undervoltage Lockout (UVLO) ............................................... 14
REVISION HISTORY
4/13—Rev. 0 to Rev. A
Changes to Figure 4 and Figure 7 .................................................... 7
Updated Outline Dimensions ........................................................23
Changes to Ordering Guide ...........................................................23
11/12—Revision 0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
ADP2386
SPECIFICATIONS
VPVIN = 12 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 1.
Parameter
PVIN
PVIN Voltage Range
Quiescent Current
Shutdown Current
PVIN Undervoltage Lockout Threshold
FB
FB Regulation Voltage
FB Bias Current
ERROR AMPLIFIER (EA)
Transconductance
EA Source Current
EA Sink Current
INTERNAL REGULATOR (VREG)
VREG Voltage
Dropout Voltage
Regulator Current Limit
SW
High-Side On Resistance 1
Low-Side On Resistance1
High-Side Peak Current Limit
Low-Side Negative Current-Limit 2
SW Minimum On Time
SW Minimum Off Time
BST
Bootstrap Voltage
OSCILLATOR (RT PIN)
Switching Frequency
Switching Frequency Range
SYNC
Synchronization Range
SYNC Minimum Pulse Width
SYNC Positive Pulse Maximum Duty Cycle
SYNC Input High Voltage
SYNC Input Low Voltage
SS
Internal Soft Start
SS Pin Pull-Up Current
Symbol
VPVIN
IQ
ISHDN
UVLO
VFB
Test Conditions/Comments
No switching
EN = GND
PVIN rising
PVIN falling
−40°C < TJ < 85°C
−40°C < TJ < 125°C
Min
4.5
2.4
50
3.6
VVREG
VPVIN = 12 V, IVREG = 50 mA
VPVIN = 12 V, IVREG = 50 mA
V
mA
µA
V
V
V
V
µA
380
45
45
480
60
60
580
75
75
µS
µA
µA
7.6
8
340
100
8.4
V
mV
mA
44
11
9.6
2.5
125
200
70
18
11.5
165
260
mΩ
mΩ
A
A
ns
ns
4.6
5
5.4
V
540
200
600
660
1400
kHz
kHz
1400
0.4
kHz
ns
%
V
V
3.9
Clock cycles
µA
7.2
tMIN_ON
tMIN_OFF
RT = 100 kΩ
20
3.6
110
4.4
0.606
0.609
0.1
VBST − VSW = 5 V
VVREG = 8 V
fSW
fSW
Unit
0.6
0.6
0.01
62
VBOOT
2.9
80
4.3
3.8
Max
0.594
0.591
IFB
gm
ISOURCE
ISINK
Typ
200
100
DMAX_SYNC
137
50
1.3
ISS_UP
2.3
Rev. A | Page 3 of 24
1600
3.2
ADP2386
Parameter
PGOOD
Power-Good Range
FB Rising Threshold
FB Rising Hysteresis
FB Falling Threshold
FB Falling Hysteresis
Power-Good Deglitch Time
Power-Good Leakage Current
Power-Good Output Low Voltage
EN
EN Rising Threshold
EN Falling Threshold
EN Source Current
Data Sheet
Symbol
Test Conditions/Comments
PGOOD from low to high
PGOOD from high to low
PGOOD from low to high
PGOOD from high to low
PGOOD from low to high
PGOOD from high to low
VPGOOD = 5 V
IPGOOD = 1 mA
EN voltage below falling threshold
EN voltage above rising threshold
2
Typ
95
5
105
11.7
1024
16
0.01
125
0.97
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
1
Min
1.17
1.07
5
1
150
25
Pin-to-pin measurement.
Guaranteed by design.
Rev. A | Page 4 of 24
Max
Unit
0.1
190
%
%
%
%
Clock cycles
Clock cycles
µA
mV
1.25
V
V
µA
µA
°C
°C
Data Sheet
ADP2386
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
PVIN, EN, PGOOD
SW
BST
FB, SS, COMP, SYNC, RT
VREG
PGND to GND
Operating Junction Temperature Range
Storage Temperature Range
Soldering Conditions
Rating
−0.3 V to +22 V
−1 V to +22 V
VSW + 6 V
−0.3 V to +6 V
−0.3 V to +12 V
−0.3 V to +0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
θJA is specified for the worst-case conditions, that is, a device
soldered in a 4-layer, JEDEC standard circuit board for surfacemount packages.
Table 3. Thermal Resistance
Package Type
24-Lead LFCSP_WQ
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 5 of 24
θJA
42.6
Unit
°C/W
ADP2386
Data Sheet
20 EN
19 PVIN
22 RT
21 PGOOD
24 SS
23 SYNC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
18 PVIN
COMP 1
FB 2
17 PVIN
25
GND
VREG 3
16 PVIN
15 BST
GND 4
26
SW
SW 5
14 SW
SW 6
PGND 12
PGND 11
PGND 9
PGND 10
SW 7
PGND 8
13 PGND
TOP VIEW
NOTES
1. THE EXPOSED GND PAD MUST BE SOLDERED
TO A LARGE, EXTERNAL, COPPER GND PLANE
TO REDUCE THERMAL RESISTANCE.
2. THE EXPOSED SW PAD MUST BE CONNECTED
TO THE SW PINS OF THE ADP2386 BY USING
SHORT, WIDE TRACES, OR ELSE SOLDERED
TO A LARGE, EXTERNAL, COPPER SW PLANE
TO REDUCE THERMAL RESISTANCE.
10211-003
ADP2386
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
COMP
FB
VREG
4
5, 6, 7, 14
8, 9, 10, 11, 12, 13
15
16, 17, 18, 19
20
GND
SW
PGND
BST
PVIN
EN
21
22
PGOOD
RT
23
SYNC
24
SS
25
EP, GND
26
EP, SW
Description
Error Amplifier Output. Connect an RC network from COMP to GND.
Feedback Voltage Sense Input. Connect to a resistor divider from the output voltage, VOUT.
Output of the Internal 8 V Regulator. The control circuits are powered from this voltage. Place a 1 µF,
X7R or X5R ceramic capacitor between this pin and GND.
Analog Ground. Return of internal control circuit.
Switch Node Output. Connect to the output inductor.
Power Ground. Return of low-side power MOSFET.
Supply Rail for the High-Side Gate Drive. Place a 0.1 µF, X7R or X5R capacitor between SW and BST.
Power Input. Connect to the input power source and connect a bypass capacitor between this pin and PGND.
Precision Enable Pin. An external resistor divider can be used to set the turn-on threshold. To enable the
part automatically, connect the EN pin to the PVIN pin.
Power-Good Output (Open Drain). A pull-up resistor of 10 kΩ to 100 kΩ is recommended.
Frequency Setting. Connect a resistor between RT and GND to program the switching frequency from
200 kHz to 1.4 MHz.
Synchronization Input. Connect this pin to an external clock to synchronize the switching frequency
within a range from 200 kHz to 1.4 MHz. See the Oscillator section and Synchronization section for
more information.
Soft Start Control. Connect a capacitor from SS to GND to program the soft start time. If this pin is open,
the regulator uses the internal soft start time.
The exposed GND pad must be soldered to a large, external, copper GND plane to reduce thermal
resistance.
The exposed SW pad must be connected to the SW pins of the ADP2386 by using short, wide traces, or
else soldered to a large, external, copper SW plane to reduce thermal resistance.
Rev. A | Page 6 of 24
Data Sheet
ADP2386
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
95
95
90
90
85
85
EFFICIENCY (%)
80
75
70
65
75
70
65
0
1
55
5
4
3
2
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
60
6
OUTPUT CURRENT (A)
50
10211-007
55
0
100
100
95
95
90
90
85
85
EFFICIENCY (%)
4
5
6
80
75
70
80
75
70
65
60
1
0
2
3
4
5
55
6
OUTPUT CURRENT (A)
50
10211-005
55
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.5V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
60
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
0
1
4
3
2
6
5
OUTPUT CURRENT (A)
Figure 5. Efficiency at VIN = 18 V, fSW = 600 kHz
10211-008
EFFICIENCY (%)
3
Figure 7. Efficiency at VIN = 12 V, fSW = 300 kHz
65
Figure 8. Efficiency at VIN = 5 V, fSW = 600 kHz
100
3.2
TJ = –40°C
TJ = +25°C
TJ = +125°C
TJ = –40°C
TJ = +25°C
TJ = +125°C
3.0
QUIESCENT CURRENT (mA)
90
80
70
60
2.8
2.6
2.4
2.2
2.0
50
4
6
8
10
12
14
16
18
INPUT VOLTAGE (V)
20
1.8
10211-006
SHUTDOWN CURRENT (μA)
2
OUTPUT CURRENT (A)
Figure 4. Efficiency at VIN = 12 V, fSW = 600 kHz
50
1
10211-004
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
60
50
80
4
6
8
10
12
14
16
INPUT VOLTAGE (V)
Figure 6. Shutdown Current vs. Input Voltage (VIN)
Figure 9. Quiescent Current vs. VIN
Rev. A | Page 7 of 24
18
20
10211-009
EFFICIENCY (%)
TA = 25°C, VIN = 12 V, VOUT = 3.3 V, L = 2.2 µH, COUT = 100 µF + 47 µF, fSW = 600 kHz, unless otherwise noted.
ADP2386
4.5
4.4
Data Sheet
1.25
RISING
FALLING
RISING
FALLING
EN THRESHOLD (V)
PVIN UVLO THRESHOLD (V)
1.20
4.3
4.2
4.1
4.0
3.9
1.15
1.10
1.05
3.8
1.00
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
0.95
–40
10211-010
3.6
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
10211-013
3.7
Figure 13. EN Threshold vs. Temperature
Figure 10. PVIN UVLO Threshold vs. Temperature
606
3.30
3.25
FEEDBACK VOLTAGE (mV)
SS PULL-UP CURRENT (μA)
604
3.20
3.15
3.10
3.05
3.00
602
600
598
596
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
594
–40
10211-011
2.90
–40
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 14. Feedback Voltage vs. Temperature
Figure 11. SS Pin Pull-Up Current vs. Temperature
8.4
630
8.3
VREG VOLTAGE (V)
620
610
RT = 100kΩ
600
590
8.2
8.1
8.0
7.9
580
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
7.7
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 15. VREG Voltage vs. Temperature
Figure 12. Frequency vs. Temperature
Rev. A | Page 8 of 24
120
10211-015
570
–40
7.8
10211-012
FREQUENCY (kHz)
–20
10211-014
2.95
Data Sheet
10.5
MOSFET RESISTOR (mΩ)
55
45
35
25
5
–40
–20
20
0
40
60
80
100
120
TEMPERATURE (°C)
9.5
9.0
8.5
8.0
7.5
–40
10211-016
15
10.0
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 16. MOSFET RDSON vs. Temperature
Figure 19. Current-Limit Threshold vs. Temperature
VOUT (AC)
1
EN
3
IL
VOUT
1
2
SW
PGOOD
3
IOUT
2
B
W
CH2 10V
M2.00µs
T 50.2%
A CH2
6V
CH1 2V
CH3 10V
Figure 17. Working Mode Waveform
B
CH2 5V
CH4 5A Ω
W
M2.00ms
T 50%
A CH2
5.8V
10211-020
CH1 10mV
CH3 2A Ω
10211-017
4
Figure 20. Soft Start with Full Load
EN
SYNC
4
VOUT
2
1
SW
PGOOD
2
4
IL
M2.00ms
T 50%
A CH2
2V
CH2 5V
CH4 10V
Figure 18. Voltage Precharged Output
M1.00µs
T 50%
A CH4
Figure 21. External Synchronization
Rev. A | Page 9 of 24
7.8V
10211-021
CH1 2V BW CH2 5V
CH3 5A Ω
CH4 10V
10211-018
3
10211-019
HIGH-SIDE RDSON
LOW-SIDE RDSON
PEAK CURRENT-LIMIT THRESHOLD (A)
65
ADP2386
ADP2386
Data Sheet
VOUT (AC)
VOUT (AC)
1
1
VIN
SW
3
IOUT
B
W
CH4 2A Ω
M200µs
T 70.4%
A CH4
2.8A
10211-022
CH1 100mV
B
CH1 20mV
CH3 5V
B
W
CH2 10V
W
B
W
M1.00ms
T 20%
A CH3
12.4V
10211-025
2
4
Figure 25. Line Transient Response, VIN from 8 V to 14 V, IOUT = 6 A
Figure 22. Load Transient Response, 1 A to 5 A
VOUT
VOUT
1
1
SW
SW
2
2
IL
IL
4
W
CH2 10V
CH4 5A Ω
M4.00ms
T 30.2%
A CH1
2.12V
CH1 2V
6
6
5
5
LOAD CURRENT (A)
7
4
3
2
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
40
55
70
M4.00ms
T 70.4%
CH2 10V
CH4 5A Ω
A CH1
2.12V
85
100
AMBIENT TEMPERATURE (°C)
4
3
2
VOUT = 1V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
1
0
25
10211-024
LOAD CURRENT (A)
7
0
25
W
Figure 26. Output Short Recovery
Figure 23. Output Short Entry
1
B
10211-026
B
40
55
70
85
100
AMBIENT TEMPERATURE (°C)
Figure 27. Load Current vs. Ambient Temperature at VIN = 12 V,
fSW = 300 kHz
Figure 24. Load Current vs. Ambient Temperature at VIN = 12 V,
fSW = 600 kHz
Rev. A | Page 10 of 24
10211-027
CH1 2V
10211-023
4
Data Sheet
ADP2386
FUNCTIONAL BLOCK DIAGRAM
VREG
CLK
RT
OSC
BIAS AND DRIVER
REGULATOR
PVIN
SLOPE RAMP
SYNC
UVLO
EN
EN_BUF
BOOST
REGULATOR
1.17V
1µA
4µA
ACS
SLOPE RAMP
Σ
VI_MAX
+
OCP
–
HICCUP
MODE
BST
COMP
0.6V
+
SS
+ AMP
FB
–
DRIVER
SW
CONTROL
LOGIC
AND MOSFET
DRIVER WITH
ANTICROSS
PROTECTION
OVP
0.7V
NFET
+
CMP
–
ISS
NFET
DRIVER
CLK
PGND
–
NEG CURRENT
–
CMP
+
+
–
0.54V
VREG
VI_NEG
+
PGOOD
DEGLITCH
10211-028
GND
Figure 28.
Rev. A | Page 11 of 24
ADP2386
Data Sheet
THEORY OF OPERATION
The ADP2386 operates from an input voltage that ranges from
4.5 V to 20 V and regulates the output voltage from 0.6 V to 90%
of the input voltage. Additional features that maximize design
flexibility include the following: programmable switching
frequency, programmable soft start, external compensation,
precision enable, and a power-good output.
BOOTSTRAP CIRCUITRY
The ADP2386 includes a regulator to provide the gate drive
voltage for the high-side N-MOSFET. It uses differential sensing to
generate a 5 V bootstrap voltage between the BST and SW pins.
It is recommended that a 0.1 µF, X7R or X5R ceramic capacitor
be placed between the BST pin and the SW pin.
OSCILLATOR
The ADP2386 switching frequency is controlled by the RT pin.
A resistor from RT to GND can program the switching frequency
according to the following equation:
CONTROL SCHEME
1400
1200
1000
PRECISION ENABLE/SHUTDOWN
The EN input pin has a precision analog threshold of 1.17 V
(typical) with 100 mV of hysteresis. When the enable voltage
exceeds 1.17 V, the regulator turns on; when it falls to less than
1.07 V (typical), the regulator turns off. To force the regulator
to automatically start when input power is applied, connect EN
to PVIN.
INTERNAL REGULATOR (VREG)
The on-board regulator provides a stable supply for the internal
circuits. It is recommended that a 1 µF ceramic capacitor be
placed between the VREG and GND pins. The internal regulator
includes a current-limit circuit to protect the output if the
maximum external load current is exceeded.
800
600
400
200
0
20
The precision EN pin has an internal pull-down current source
(5 µA) that provides a default turn-off when the EN pin is open.
When the EN pin voltage exceeds 1.17 V (typical), the ADP2386
is enabled and the internal pull-down current source at the EN
pin decreases to 1 µA, which allows users to program the PVIN
UVLO and hysteresis.
69120
RT (k Ω) + 15
A 100 kΩ resistor sets the frequency to 600 kHz, and a 42.2 kΩ
resistor sets the frequency to 1.2 MHz. Figure 29 shows the
typical relationship between fSW and RT.
FREQUENCY (kHz)
The ADP2386 uses a fixed frequency, peak current-mode PWM
control architecture. At the start of each oscillator cycle, the highside N-MOSFET is turned on, putting a positive voltage across
the inductor. When the inductor current crosses the peak inductor
current threshold, the high-side N-MOSFET is turned off and
the low-side N-MOSFET is turned on. This puts a negative voltage
across the inductor, causing the inductor current to decrease.
The low-side N-MOSFET stays on for the rest of the cycle (see
Figure 17).
fSW (kHz) =
60
100
140
180
220
RT (kΩ)
260
300
10211-029
The ADP2386 is a synchronous step-down, dc-to-dc regulator
that uses a current-mode architecture with an integrated highside power switch and a low-side synchronous rectifier. The
regulator targets high performance applications that require
high efficiency and design flexibility.
Figure 29. Switching Frequency vs. RT
SYNCHRONIZATION
To synchronize the ADP2386, connect an external clock to the
SYNC pin. The external clock frequency can be in the range
of 200 kHz to 1.4 MHz. During synchronization, the regulator
operates in continuous conduction mode (CCM), and the rising
edge of the switching waveform runs 180° out of phase to the rising
edge of the external clock.
When the ADP2386 operates in synchronization mode, a resistor
must be connected from the RT pin to GND to program the
internal oscillator to run at 90% to 110% of the external
synchronization clock.
Rev. A | Page 12 of 24
Data Sheet
ADP2386
VOUT RISING
SOFT START
105%
100%
95%
90%
1600
(ms)
f SW (kHz)
A slower soft start time can be programmed by using the SS pin.
When a capacitor is connected between the SS pin and GND, an
internal current charges the capacitor to establish the soft start
ramp. The soft start time is calculated using the following equation:
tSS_EXT = 0.6 V  C SS
I SS _ UP
where:
CSS is the soft start capacitance.
ISS_UP is the soft start pull-up current (3.2 μA).
The internal error amplifier includes three positive inputs: the
internal reference voltage, the internal digital soft start voltage,
and the SS pin voltage. The error amplifier regulates the FB
voltage to the lowest of the three voltages.
If the output voltage is charged prior to turn-on, the ADP2386
prevents reverse inductor current that would discharge the output
capacitor. This function remains active until the soft start
voltage exceeds the voltage on the FB pin.
POWER GOOD
The power-good pin (PGOOD) is an active high, open-drain
output that requires an external resistor to pull it up to a voltage.
A logic high on the PGOOD pin indicates that the voltage on
the FB pin (and, therefore, the output voltage) is within regulation.
The power-good circuitry monitors the output voltage on the
FB pin and compares it to the rising and falling thresholds that
are specified in Table 1. If the rising output voltage exceeds the
target value, the PGOOD pin is held low. The PGOOD pin
continues to be held low until the falling output voltage returns
to the target value.
If the output voltage falls below the target output voltage, the
PGOOD pin is held low. The PGOOD pin continues to be held
low until the rising output voltage returns to the target value.
The power-good rising and falling thresholds are shown in
Figure 30. There is a 1024-cycle waiting period (deglitch) before
the PGOOD pin is pulled from low to high, and there is a
16-cycle waiting period (deglitch) before the PGOOD pin is
pulled from high to low.
PGOOD
1024 CYCLE
DEGLITCH
16 CYCLE
DEGLITCH
1024 CYCLE
DEGLITCH
16 CYCLE
DEGLITCH
10211-130
tSS_INT =
116.7%
VOUT (%)
The ADP2386 has integrated soft start circuitry to limit the output
voltage rising time and reduce inrush current at startup. The
internal soft start time is calculated using the following equation:
VOUT FALLING
Figure 30. PGOOD Rising and Falling Thresholds
PEAK CURRENT-LIMIT AND SHORT-CIRCUIT
PROTECTION
The ADP2386 has a peak current-limit protection circuit to
prevent current runaway. During the initial soft start, the
ADP2386 uses frequency foldback to prevent output current
runaway. The switching frequency is reduced according to the
voltage on the FB pin, which allows more time for the inductor
to discharge. The correlation between the switching frequency
and the FB pin voltage is shown in Table 5.
Table 5. FB Pin Voltage and Switching Frequency
FB Pin Voltage
VFB ≥ 0.4 V
0.4 V > VFB ≥ 0.2 V
VFB < 0.2 V
Switching Frequency
fSW
fSW/2
fSW/4
For protection against heavy loads, the ADP2386 uses a hiccup
mode for overcurrent protection. When the inductor peak
current reaches the current-limit value, the high-side MOSFET
turns off and the low-side MOSFET turns on until the next cycle.
The overcurrent counter increments during this process. If the
overcurrent counter reaches 10, or the FB pin voltage falls to
0.4 V after the soft start, the regulator enters hiccup mode. The
high-side and low-side MOSFETs are both turned off. The
regulator remains in hiccup mode for 4096 clock cycles and then
attempts to restart. If the current-limit fault has cleared, the
regulator resumes normal operation. Otherwise, it reenters
hiccup mode.
The ADP2386 also provides a sink current limit to prevent the
low-side MOSFET from sinking a lot of current from the load.
When the voltage across the low-side MOSFET exceeds the sink
current-limit threshold, which is typically 2.5 A, the low-side
MOSFET turns off immediately for the rest of the cycle. Both highside and low-side MOSFETs turn off until the next clock cycle.
In some cases, the input voltage (VPVIN) ramp rate is too slow or
the output capacitor is too large for the output to reach regulation
during the soft start process, which causes the regulator to enter
the hiccup mode. To avoid such occurrences, use a resistor
divider at the EN pin to program the input voltage UVLO,
or use a longer soft start time.
Rev. A | Page 13 of 24
ADP2386
Data Sheet
OVERVOLTAGE PROTECTION (OVP)
The ADP2386 includes an overvoltage protection feature
to protect the regulator against an output short to a higher
voltage supply or when a strong load disconnect transient
occurs. If the feedback voltage increases to 0.7 V, the internal
high-side and low-side MOSFETs are turned off until the
voltage at the FB pin decreases to 0.63 V. At that time, the
ADP2386 resumes normal operation.
UNDERVOLTAGE LOCKOUT (UVLO)
Undervoltage lockout circuitry is integrated in the ADP2386 to
prevent the occurrence of power-on glitches. If the VPVIN voltage
falls to less than 3.8 V typical, the part shuts down, and both the
power switch and synchronous rectifier turn off. When the
VPVIN voltage rises to greater than 4.3 V typical, the soft start
period is initiated, and the part is enabled.
THERMAL SHUTDOWN
If the ADP2386 junction temperatures rises to greater than 150°C,
the internal thermal shutdown circuit turns off the regulator for
self-protection. Extreme junction temperatures can be the result of
high current operation, poor circuit board thermal design,
and/or high ambient temperature. A 25°C hysteresis is included
in the thermal shut-down circuit so that, if an overtemperature
event occurs, the ADP2386 does not return to normal operation
until the on-chip temperature falls to less than 125°C. Upon
recovery, a soft start is initiated before normal operation begins.
Rev. A | Page 14 of 24
Data Sheet
ADP2386
APPLICATIONS INFORMATION
INPUT CAPACITOR SELECTION
The input capacitor reduces the input voltage ripple caused by
the switch current on PVIN. Place the input capacitor as close
as possible to the PVIN pin. A ceramic capacitor in the 10 μF to
47 μF range is recommended. The loop that is composed of this
input capacitor, the high-side N-MOSFET, and the low-side NMOSFET must be kept as small as possible.
The voltage rating of the input capacitor must be greater than
the maximum input voltage. Ensure that the rms current rating
of the input capacitor is larger than the value calculated from
the following equation:
ICIN_RMS = IOUT ×
D × (1 − D )
OUTPUT VOLTAGE SETTING
The output voltage of the ADP2386 is set by an external resistive
divider. The resistor values are calculated using

R
VOUT = 0.6 × 1 + TOP
R
BOT




To limit the output voltage accuracy degradation due to the FB
bias current (0.1 µA maximum) to less than 0.5% (maximum),
ensure that RBOT < 30 kΩ.
RBOT ± 1% (kΩ)
15
10
10
10
15
2.21
3
The maximum output voltage, limited by the maximum duty
cycle at a given input voltage, can be calculated using the
following equation:
(3)
As shown in Equation 1 to Equation 3, reducing the switching
frequency alleviates the minimum on time and minimum off
time limitation.
The inductor value is determined by the operating frequency,
input voltage, output voltage, and inductor ripple current. Using
a small inductor value leads to a faster transient response; however,
it degrades efficiency, due to a larger inductor ripple current.
Using a large inductor value leads to smaller ripple current and
better efficiency, but it results in a slower transient response.
The minimum output voltage for a given input voltage and
switching frequency is constrained by the minimum on time.
The minimum on time of the ADP2386 is typically 125 ns.
The minimum output voltage for a given input voltage and
switching frequency can be calculated using the following:
where:
VOUT_MIN is the minimum output voltage.
VIN is the input voltage.
tMIN_ON is the minimum on time.
fSW is the switching frequency.
RDSON_HS is the high-side MOSFET on resistance.
RDSON_LS is the low-side MOSFET on resistance.
IOUT_MIN is the minimum output current.
RL is the series resistance of the output inductor.
where:
VOUT_MAX is the maximum output voltage.
VIN is the input voltage.
tMIN_OFF is the minimum off time.
fSW is the switching frequency.
RDSON_HS is the high-side MOSFET on resistance.
RDSON_LS is the low-side MOSFET on resistance.
IOUT_MAX is the maximum output current.
RL is the series resistance of the output inductor.
INDUCTOR SELECTION
VOLTAGE CONVERSION LIMITATIONS
VOUT_MIN = VIN × tMIN_ON × fSW − (RDSON_HS − RDSON_LS) ×
IOUT_MIN × tMIN_ON × fSW − (RDSON_LS + RL) × IOUT_MIN
VOUT_MAX = VIN × (1 − tMIN_OFF × fSW) − (RDSON_HS − RDSON_LS) ×
IOUT_MAX × (1 − tMIN_OFF × fSW) − (RDSON_LS + RL) × IOUT_MAX (2)
where DMAX is the maximum duty cycle; VIN is the input voltage.
Table 6. Resistor Divider Values for Various Output Voltages
RTOP ± 1% (kΩ)
10
10
15
20
47.5
10
22
The maximum output voltage, limited by the minimum off time
at a given input voltage and switching frequency, can be calculated
using the following equation:
VOUT_MAX = DMAX × VIN
Table 6 lists the recommended resistor divider values for the
various output voltages.
VOUT (V)
1.0
1.2
1.5
1.8
2.5
3.3
5.0
The maximum output voltage for a given input voltage and
switching frequency is constrained by the minimum off time
and the maximum duty cycle. The minimum off time is typically
200 ns, and the maximum duty cycle of the ADP2386 is
typically 90%.
As a guideline, the inductor ripple current, ΔIL, is typically set
to one-third of the maximum load current. The inductor value
is calculated using the following equation:
L = (VIN − VOUT ) × D
(1)
∆I L × f SW
where:
VIN is the input voltage.
VOUT is the output voltage.
D is the duty cycle (D = VOUT/VIN).
ΔIL is the inductor current ripple.
fSW is the switching frequency.
The ADP2386 uses adaptive slope compensation in the current
loop to prevent subharmonic oscillations when the duty cycle
is larger than 50%. The internal slope compensation limits the
minimum inductor value.
Rev. A | Page 15 of 24
ADP2386
Data Sheet
For a duty cycle that is larger than 50%, the minimum inductor
value is determined using the following equation:
L (Minimum) =
VOUT × (1 − D )
2 × f SW
Another example occurs when a load is suddenly removed from
the output, and the energy stored in the inductor rushes into
the output capacitor, causing the output to overshoot.
The peak inductor current is calculated by
IPEAK = IOUT + ∆I L
2
The saturation current of the inductor must be larger than the peak
inductor current. For ferrite core inductors with a quick saturation
characteristic, the saturation current rating of the inductor must
be higher than the current-limit threshold of the switch. This
prevents the inductor from reaching saturation.
The rms current of the inductor is calculated as follows:
IRMS =
I OUT +
2
∆I L
12
where:
KUV is a factor, with a typical setting of KUV = 2.
ΔISTEP is the load step.
ΔVOUT_UV is the allowable undershoot on the output voltage.
2
Shielded ferrite core materials are recommended for low core
loss and low EMI. Table 7 lists some recommended inductors.
The output capacitance that is required to meet the overshoot
requirement can be calculated using the following equation:
where:
ΔVOUT_OV is the allowable overshoot on the output voltage.
KOV is a factor, with a typical setting of KOV = 2.
The output ripple is determined by the ESR and the value of the
capacitance. Use the following equations to select a capacitor
that can meet the output ripple requirements:
COUT_RIPPLE =
OUTPUT CAPACITOR SELECTION
The output capacitor selection affects the output ripple voltage
load step transient and the loop stability of the regulator.
For example, during a load step transient where the load is
suddenly increased, the output capacitor supplies the load until
the control loop can ramp up the inductor current. The delay
caused by the control loop causes output undershoot. The
output capacitance that is required to satisfy the voltage droop
requirement can be calculated using the following equation:
KUV × ∆I STEP × L
2 × (VIN − VOUT ) × ∆VOUT _ UV
2
COUT_UV =
K OV × ∆I STEP × L
2
(VOUT + ∆VOUT _ OV ) 2 − VOUT
2
COUT_OV =
∆I L
8 × f SW × ∆VOUT _ RIPPLE
RESR = ∆VOUT _ RIPPLE
∆I L
where:
ΔIL is the inductor current ripple.
ΔVOUT_RIPPLE is the allowable output ripple voltage.
RESR is the equivalent series resistance of the output capacitor
in ohms (Ω).
Select the largest output capacitance given by COUT_UV, COUT_OV,
and COUT_RIPPLE to meet both load transient and output ripple
performance.
Table 7. Recommended Inductors
Vendor
Toko
Vishay
Wurth Elektronik
Part No.
FDVE0630-R47M
FDVE0630-R75M
FDVE0630-1R0M
FDVE1040-1R5M
FDVE1040-2R2M
FDVE1040-3R3M
FDVE1040-4R7M
IHLP3232DZ-R47M-11
IHLP3232DZ-R68M-11
IHLP3232DZ-1R0M-11
IHLP4040DZ-1R5M-01
IHLP4040DZ-2R2M-01
IHLP4040DZ-3R3M-01
IHLP4040DZ-4R7M-01
744 325 120
744 325 180
744 325 240
744 325 330
744 325 420
Value (µH)
0.47
0.75
1.0
1.5
2.2
3.3
4.7
0.47
0.68
1.0
1.5
2.2
3.3
4.7
1.2
1.8
2.4
3.3
4.2
Rev. A | Page 16 of 24
ISAT (A)
15.6
10.9
9.5
13.7
11.4
9.8
8.2
14
14.5
12
27.5
25.6
18.6
17
25
18
17
15
14
IRMS (A)
14.1
10.7
9.5
14.6
11.6
9.0
8.0
25
22.2
18.2
15
12
10
9.5
20
16
14
12
11
DCR (mΩ)
3.7
6.2
8.5
4.6
6.8
10.1
13.8
2.38
3.22
4.63
5.8
9
14.4
16.5
1.8
3.5
4.75
5.9
7.1
Data Sheet
ADP2386
The selected output capacitor voltage rating must be greater
than the output voltage. The rms current rating of the output
capacitor must be larger than the value that is calculated by
using the following equation:
ICOUT_RMS = ∆I L
12
The ADP2386 uses a transconductance amplifier for the error
amplifier and to compensate the system. Figure 32 shows the
simplified, peak current-mode control, small signal circuit.
VOUT
VOUT
RTOP
PVIN
RBOT
+
AVI
COUT
R
RC
CCP
–
RESR
CC
10211-031
The ADP2386 has a precision enable input that can be used to
program the UVLO threshold of the input voltage (see Figure 31).
VCOMP
–
gm
+
PROGRAMMING THE INPUT VOLTAGE UVLO
ADP2386
Figure 32. Simplified Peak Current Mode Control, Small Signal Circuit
RTOP_EN
The compensation components, RC and CC, contribute a zero,
and RC and the optional CCP contribute an optional pole.
EN CMP
EN
The closed-loop transfer equation is as follows:
1.17V
RBOT_EN
4µA
TV (s) =
10211-030
1µA
1 + RC × CC × s
× GVD ( s )
R × CC × CCP
× s)
s × (1 + C
CC + CCP
Figure 31. Programming the Input Voltage UVLO
Use the following equations to calculate RTOP_EN and RBOT_EN:
RTOP_EN =
RBOT_EN =
1.07 V × VIN _ RISING − 1.17 V × VIN _ FALLING
The following design guideline shows how to select the RC, CC,
and CCP compensation components for ceramic output
capacitor applications:
1.07 V × 5μA − 1.17 V × 1 μA
1.17 V × RTOP _ EN
VIN _ RISING − RTOP _ EN × 5μA − 1.17 V
where:
VIN_RISING is the VIN rising threshold.
VIN_FALLING is the VIN falling threshold.


s
1 +

2 × π × f Z 
VOUT ( s )

GVD (s) =
= AVI × R ×
V COMP ( s )


s
1 +

2
π
f
×
×
P 

fP =
1
2 × π × ( R + RESR ) × COUT
Determine the cross frequency, fC. Generally, fC is between
fSW/12 and fSW/6.
2.
Calculate RC, using the following equation:
0.6 V × g m × AVI
For peak current-mode control, the power stage can be simplified
as a voltage controlled current source supplying current to the
output capacitor and load resistor. It is composed of one domain
pole and a zero that is contributed by the output capacitor ESR.
The control-to-output transfer function is based on the following:
1
2 × π × RESR × COUT
1.
RC = 2 × π × VOUT × COUT × f C
COMPENSATION DESIGN
fZ =
− gm
R BOT
×
×
R BOT + RTOP C C + C CP
3.
Place the compensation zero at the domain pole, fP; then
determine CC by using the following equation:
CC = ( R + RESR ) × COUT
RC
4.
CCP is optional. It can be used to cancel the zero caused by
the ESR of the output capacitor.
CCP = RESR × COUT
RC
ADIsimPOWER DESIGN TOOL
where:
AVI = 8.7 A/V.
R is the load resistance.
COUT is the output capacitance.
RESR is the equivalent series resistance of the output capacitor.
The ADP2386 is supported by the ADIsimPower™ design tool
set. ADIsimPower is a collection of tools that produce complete
power designs that are optimized for a specific design goal. The
tools enable the user to generate a full schematic and bill of
materials and calculate performance in minutes. ADIsimPower
can optimize designs for cost, area, efficiency, and part count,
while taking into consideration the operating conditions and
limitations of the IC and all real external components. For more
information about theADIsimPower design tools, refer to
www.analog.com/ADIsimPower. The tool set is available from
this website, and users can request an unpopulated board.
Rev. A | Page 17 of 24
ADP2386
Data Sheet
DESIGN EXAMPLE
VIN = 12V
PVIN
BST
CBST
0.1µF
EN
L1
2.2µF
PGOOD
SYNC
RT
100kΩ
CVREG
1µF
RTOP
10kΩ
1%
ADP2386
RT
FB
COMP
VREG
CSS
22nF
VOUT = 3.3V
SW
SS
CCP
4.7pF
GND PGND
RC
44.2kΩ
CC
1.2nF
COUT1
100µ F
6.3V
COUT2
47µ F
6.3V
RTOP
2.21kΩ
1%
10211-033
CIN
10µF
25V
Figure 33. Schematic for Design Example
This section describes the procedures for selecting the external
components, based on the example specifications that are listed
in Table 8. See Figure 33 for the schematic of this design example.
Table 8. Step-Down DC-to-DC Regulator Requirements
Parameter
Input Voltage
Output Voltage
Output Current
Output Voltage Ripple
Load Transient
Switching Frequency
Specification
VIN = 12.0 V ± 10%
VOUT = 3.3 V
IOUT = 6 A
∆VOUT_RIPPLE = 33 mV
±5%, 1 A to 5 A, 2 A/μs
fSW = 600 kHz
This calculation results in L = 2.215 μH. Choose the standard
inductor value of 2.2 μH.
The peak-to-peak inductor ripple current can be calculated by
using the following equation:
ΔIL =
(VIN − VOUT ) × D
L × f SW
This calculation results in ∆IL = 1.81 A.
Use the following equation to calculate the peak inductor current:
∆I L
2
IPEAK = IOUT +
OUTPUT VOLTAGE SETTING
This calculation results in IPEAK = 6.905 A.
Choose a 10 kΩ resistor as the top feedback resistor (RTOP),
and calculate the bottom feedback resistor (RBOT) by using the
following equation:
Use the following equation to calculate the rms current flowing
through the inductor:
IRMS =

0.6
RBOT = RTOP × 

V
 OUT − 0.6 
I OUT +
2
∆I L
12
2
This calculation results in IRMS = 6.023 A.
To set the output voltage to 3.3 V, the resistors values are as
follows: RTOP = 10 kΩ, and RBOT = 2.21 kΩ.
Based on the calculated current value, select an inductor with
a minimum rms current rating of 6.03 A and a minimum
saturation current rating of 6.91 A.
FREQUENCY SETTING
To set the switching frequency to 600 kHz, connect a 100 kΩ
resistor from the RT pin to GND.
INDUCTOR SELECTION
However, to protect the inductor from reaching its saturation
point under the current-limit condition, the inductor should be
rated for at least a 9.6 A saturation current for reliable operation.
The peak-to-peak inductor ripple current, ∆IL, is set to 30% of
the maximum output current. Use the following equation to
estimate the inductor value:
Based on the requirements described previously, select a 2.2 μH
inductor, such as the FDVE1040-2R2M from Toko, which has
a 6.8 mΩ DCR and a 11.4 A saturation current.
L = (V IN − VOUT ) × D
∆I L × f SW
where:
VIN = 12 V.
VOUT = 3.3 V.
D = 0.275.
∆IL = 1.8 A.
fSW = 600 kHz.
Rev. A | Page 18 of 24
Data Sheet
ADP2386
OUTPUT CAPACITOR SELECTION
The output capacitor is required to meet both the output voltage
ripple and load transient response requirements.
The 100 µF and 47 µF ceramic output capacitors have a derated
value of 62 µF and 32 µF.
RC = 2 × π × 3.3V × 94 μF × 60 kHz = 46.7 kΩ
0.6 V × 480 μs × 8.7 A/ V
To meet the output voltage ripple requirement, use the following
equation to calculate the ESR and capacitance value of the output
capacitor:
CCP = 0.002 Ω × 94 μF = 4.0 pF
46.7 kΩ
Choose standard components, as follows: RC = 44.2 kΩ,
CC = 1200 pF, and CCP = 4.7 pF.
RESR = ∆VOUT _ RIPPLE
∆I L
This calculation results in COUT_RIPPLE = 11.4 μF, and RESR = 18 mΩ.
To meet the ±5% overshoot and undershoot transient
requirements, use the following equations to calculate the
capacitance:
COUT_UV =
K OV × ∆I STEP × L
2
(VOUT + ∆VOUT _ OV ) 2 − VOUT
2
MAGNITUDE (dB)
COUT_OV =
Figure 34 shows the bode plot at 6 A. The cross frequency is
58 kHz, and the phase margin is 61°.
KUV × ∆I STEP × L
2 × (VIN − VOUT ) × ∆VOUT _ UV
2
where:
KOV = KUV = 2 are the coefficients for estimation purposes.
∆ISTEP = 4 A is the load transient step.
∆VOUT_OV = 5% VOUT is the overshoot voltage.
∆VOUT_UV = 5% VOUT is the undershoot voltage.
60
180
48
144
36
108
24
72
12
36
0
0
–12
–36
–24
–72
–36
–108
–48
–144
–60
1k
10k
100k
PHASE (Degrees)
8 × f SW
∆I L
× ∆VOUT _ RIPPLE
–180
1M
FREQUENCY (Hz)
This calculation results in COUT_OV = 63.1 μF, and COUT_UV = 24.5 μF.
According to the calculation, the output capacitance must be
greater than 63 μF, and the ESR of the output capacitor must be
smaller than 18 mΩ. It is recommended that one 100 μF/X5R/
6.3 V ceramic capacitor and one 47 μF/X5R/6.3 V ceramic
capacitor be used, such as the GRM32ER60J107ME20 and
GRM32ER60J476ME20 from Murata, with an ESR of 2 mΩ.
Figure 34. Bode Plot at 6 A
SOFT START TIME PROGRAM
The soft start feature allows the output voltage to ramp up in a
controlled manner, eliminating output voltage overshoot during
soft start and limiting the inrush current. Set the soft start time
to 4 ms.
COMPENSATION COMPONENTS
CSS =
For better load transient and stability performance, set the cross
frequency, fC, to fSW/10. In this case, fSW is running at 600 kHz;
therefore, the fC is set to 60 kHz.
10211-134
COUT_RIPPLE =
CC = (0.55 Ω + 0.002 Ω) × 94 μF = 1111 pF
46.7 kΩ
t SS _ EXT × I SS _UP
0.6
=
4 ms × 3.2 μA
= 21.3 nF
0.6 V
Choose a standard component value, as follows: CSS = 22 nF.
INPUT CAPACITOR SELECTION
Place a minimum 10 μF ceramic capacitor near the PVIN pin.
In this application, it is recommended that one 10 μF, X5R, 25 V
ceramic capacitor be used.
Rev. A | Page 19 of 24
ADP2386
Data Sheet
RECOMMENDED EXTERNAL COMPONENTS
Table 9. Recommended External Components for Typical Applications with 6 A Output Current
fSW (kHz)
300
600
1000
1
VIN (V)
12
12
12
12
12
12
12
5
5
5
5
5
5
12
12
12
12
12
5
5
5
5
5
5
12
12
12
5
5
5
5
5
5
VOUT (V)
1
1.2
1.5
1.8
2.5
3.3
5
1
1.2
1.5
1.8
2.5
3.3
1.5
1.8
2.5
3.3
5
1
1.2
1.5
1.8
2.5
3.3
2.5
3.3
5
1
1.2
1.5
1.8
2.5
3.3
L (µH)
1.5
2.2
2.2
3.3
3.3
4.7
4.7
1.5
1.5
2.2
2.2
2.2
2.2
1
1.5
2.2
2.2
3.3
1
1
1
1
1
1
1
1.5
1.5
0.47
0.47
0.68
0.68
0.68
0.68
COUT (µF) 1
680 + 2 × 100
680 + 2 × 100
680
680
470
3 × 100
100 + 47
680 + 2 × 100
680
680
470
3 × 100
3 × 100
3 × 100
3 × 100
2 × 100
100 + 47
100
680
470
3 × 100
2 × 100
100
100 + 47
100
100
100
3 × 100
2 × 100
100 + 47
100 + 47
100
100
RTOP (kΩ)
10
10
15
20
47.5
10
22
10
10
15
20
47.5
10
15
20
47.5
10
22
10
10
15
20
47.5
10
47.5
10
22
10
10
15
20
47.5
10
RBOT (kΩ)
15
10
10
10
15
2.21
3
15
10
10
10
15
2.21
10
10
15
2.21
3
15
10
10
10
15
2.21
15
2.21
3
15
10
10
10
15
2.21
RC (kΩ)
57.6
68.1
73.2
88.7
84.5
44.2
33
57.6
57.6
73.2
61.9
33
44.2
39
47
44.2
44.2
44.2
97.6
82
39
33
22
44.2
37.4
47
73.2
44.2
34.8
33
39
37.4
47
CC (pF)
2200
2200
2200
2200
2200
2200
2200
2200
2200
2200
2200
2200
2200
1200
1200
1200
1200
1200
1200
1200
1200
1200
1200
1200
680
680
680
680
680
680
680
680
680
CCP (pF)
150
120
100
82
47
8.2
4.7
150
120
100
82
10
8.2
10
8.2
4.7
4.7
2.2
68
47
10
8.2
4.7
4.7
3.3
2.2
2.2
8.2
6.8
4.7
4.7
3.3
2.2
680 μF: 4 V, Sanyo 4TPF680M; 470 μF: 6.3 V, Sanyo 6TPF470M; 100 μF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 μF: 6.3 V, X5R, Murata GRM32ER60J476ME20.
Rev. A | Page 20 of 24
Data Sheet
ADP2386
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Good printed circuit board (PCB) layout is essential for obtaining
the best performance from the ADP2386. Poor PCB layout can
degrade the output regulation, as well as the electromagnetic
interference (EMI) and electromagnetic compatibility (EMC)
performance. Figure 36 shows an example of a good PCB layout
for the ADP2386. For optimum layout, refer to the following
guidelines:



ADP2386
VIN
PVIN
CIN
BST
CBST
EN
RTOP
SYNC
RT
CVREG
GND PGND
CSS
PULL UP
PVIN
PGOOD
PVIN
EN
RT
SYNC
CSS
RT
CC
SS
RC
SS
CC
Figure 35. High Current Path in the PCB Circuit
PVIN
GND
FB
INPUT
BYPASS
CAP
PVIN
VREG
PVIN
BST
CVREG
GND
SW
SW
SW
SW
CBST
INPUT
BULK
CAP
+
PGND
PGND
PGND
PGND
PGND
PGND
SW
SW
RBOT
COMP
VREG
INDUCTOR
POWER GROUND PLANE
OUTPUT
CAPACITOR
VOUT
10211-034
VIA
BOTTOM LAYER TRACE
COPPER PLANE
Figure 36. Recommended PCB Layout
Rev. A | Page 21 of 24
10211-033
RT
COMP
RTOP
COUT
FB
ANALOG GROUND PLANE
RBOT
VOUT
L
SW
PGOOD
In addition, ensure that the high current path from the power
ground plane through the inductor and output capacitor
back to the power ground plane is as short as possible by
tying the PGND pins of the ADP2386 to the PGND plane
as close as possible to the input and output capacitors.
RC

CCP

Use separate analog ground planes and power ground
planes. Connect the ground reference of sensitive analog
circuitry, such as output voltage divider components, to
analog ground. In addition, connect the ground reference
of power components, such as input and output capacitors,
to power ground. Connect both ground planes to the
exposed GND pad of the ADP2386.
Place the input capacitor, inductor, and output capacitor as
close as possible to the IC, and use short traces.
Ensure that the high current loop traces are as short and as
wide as possible. Make the high current path from the input
capacitor through the inductor, the output capacitor, and the
power ground plane back to the input capacitor as short as
possible. To accomplish this, ensure that the input and output
capacitors share a common power ground plane.
Connect the exposed GND pad of the ADP2386 to a large,
external copper ground plane to maximize its power
dissipation capability and minimize junction temperature.
In addition, connect the exposed SW pad to the SW pins
of the ADP2386, using short, wide traces; or connect the
exposed SW pad to a large copper plane of the switching
node for high current flow.
Place the feedback resistor divider network as close as
possible to the FB pin to prevent noise pickup. Minimize
the length of the trace that connects the top of the feedback
resistor divider to the output while keeping the trace away
from the high current traces and the switching node to
avoid noise pickup. To further reduce noise pickup, place
an analog ground plane on either side of the FB trace and
ensure that the trace is as short as possible to reduce the
parasitic capacitance pickup.
ADP2386
Data Sheet
TYPICAL APPLICATIONS CIRCUITS
BST
PVIN
CIN
10µF
25V
CBST L1
0.1µF 1µH
EN
PGOOD
SYNC
RT
124kΩ
RTOP
10kΩ
1%
ADP2386
COUT1
470µF
6.3V
COUT2
10µF
6.3V
FB
RT
VREG
CVREG
1µF
VOUT = 1.2V
SW
COMP
SS
CCP
68pF
GND PGND
CSS
22nF
RC
66.5kΩ
CC
1.5nF
RBOT
10kΩ
1%
10211-035
VIN = 12V
Figure 37. Typical Applications Circuit, VIN = 12 V, VOUT = 1.2 V, IOUT = 6 A, fSW = 500 kHz
VIN = 12V
PVIN
CIN
10µF
25V
BST
EN
CBST
0.1µF
PGOOD
L1
1.5µH
SW
SYNC
RTOP
20kΩ
1%
ADP2386
RPGOOD
100kΩ
VOUT = 1.8V
COUT1
100µF
6.3V
COUT2
100µF
6.3V
COUT3
100µF
6.3V
FB
VREG
RT
100kΩ
RT
SS
COMP
CCP
8.2pF
GND PGND
RC
47kΩ
CC
1.2nF
RBOT
10kΩ
1%
10211-038
CVREG
1µF
Figure 38. Typical Applications Circuit Using Internal Soft Start, VIN = 12 V, VOUT = 1.8 V, IOUT = 6 A, fSW = 600 kHz
VIN = 12V
RTOP_EN
16.9kΩ
RBOT_EN
2kΩ
PVIN
BST
EN
CBST
0.1µF
PGOOD
SW
SYNC
RT
100kΩ
RTOP
22kΩ
1%
ADP2386
COMP
VREG
SS
VOUT = 5V
COUT
100µF
6.3V
FB
RT
CVREG
1µF
CSS
22nF
L1
3.3µH
GND PGND
CCP
2.2pF
RC
44.2kΩ
CC
1.2nF
RBOT
3kΩ
1%
10211-039
CIN
10µF
25V
Figure 39. Programming Input Voltage UVLO Rising Threshold at 11 V, Falling Threshold at 10 V, VIN = 12 V, VOUT = 5 V, IOUT = 6 A, fSW = 600 kHz
Rev. A | Page 22 of 24
Data Sheet
ADP2386
OUTLINE DIMENSIONS
PIN 1
INDICATOR
0.20
MIN
0.20
MIN
2.80
2.70
2.60
0.20 MIN
19
24
18
1
EXPOSED
PAD
0.50
BSC
0.35
0.25
EXPOSED
PAD
0.80
0.75
0.70
SEATING
PLANE
0.50
0.40
0.30
12
7
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
0.25
0.20
0.15
1.05
0.95
0.85
6
13
TOP VIEW
PIN 1
INDICATOR
1.50
1.40
1.30 0.45
0.20
MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD .
01-14-2013-B
4.10
4.00 SQ
3.90
Figure 40. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-24-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADP2386ACPZN-R7
ADP2386-EVALZ
ADP2386BB-EVALZ
1
Temperature Range
−40°C to +125°C
Package Description
24-Lead LFCSP_WQ, 7” Tape and Reel
Evaluation Board
Inverting Buck-Boost Evaluation Board
Z = RoHS Compliant Part.
Rev. A | Page 23 of 24
Package Option
CP-24-12
ADP2386
Data Sheet
NOTES
©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10211-0-4/13(A)
Rev. A | Page 24 of 24