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SBAS258A – JUNE 2002 – REVISED JULY 2002
! !
FEATURES
D 3.3V Single-Supply Operation
D Dual Simultaneous Sample-and-Hold Inputs
D Differential or Single-Ended Analog Inputs
D Single or Dual Parallel Bus Output
D 60dB SNR at fIN = 10.5MHz
D 73dB SFDR at fIN = 10.5MHz
D Low Power: 240mW
D 300MHz Analog Input Bandwidth
D 3.3V TTL/CMOS-Compatible Digital I/O
D Internal or External Reference
D Adjustable Reference Input Range
D Power-Down (Standby) Mode
D TQFP-48 Package
APPLICATIONS
D Digital Communications (Baseband Sampling)
D Video Processing
D Portable Instrumentation
D Ultrasound
DESCRIPTION
The ADS5203 is a dual 10-bit, 40MSPS Analog-to-Digital Converter (ADC). It simultaneously converts each
analog input signal into a 10-bit, binary coded digital
word up to a maximum sampling rate of 40MSPS per
channel. All digital inputs and outputs are 3.3V
TTL/CMOS compatible.
An innovative dual-pipeline architecture implemented in
a CMOS process and the 3.3V supply results in very low
power dissipation. In order to provide maximum flexibility, both top and bottom voltage references can be set
from user-supplied voltages. Alternatively, if no external
references are available, the on-chip internal references can be used. Both ADCs share a common reference to improve offset and gain matching. If external
reference voltage levels are available, the internal references can be powered down independently from the
rest of the chip, resulting in even greater power savings.
The ADS5203 is characterized for operation from
–40°C to +85°C and is available in a TQFP-48 package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
!" $%&$ ' ($ ' % )*
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Copyright 2002, Texas Instruments Incorporated
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SBAS258A – JUNE 2002 – REVISED JULY 2002
ORDERING INFORMATION
PRODUCT
PACKAGE–LEAD
PACKAGE
DESIGNATOR(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
ADS5203
TQFP–48
PFB
–40°C to +85°C
AZ5203
ADS5203IPFB
ADS5203
TQFP–48
PFB
–40°C to +85°C
AZ5203
ADS5203IPFBR
(1) For the most current specifications and package information, refer to our web site at www.ti.com.
TRANSPORT
MEDIA, QUANTITY
Tray, 250
Tape and Reel, 1000
This integrated circuit can be damaged by
ESD. Texas Instruments recommends that
all integrated circuits be handled with
appropriate precautions. Failure to observe proper
handling and installation procedures can cause
damage.
ESD damage can range from subtle performance
degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage
because very small parametric changes could cause
the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1).
Supply Voltage: AVDD to AGND, DVDD to DGND . . . . . . . . . . –0.5V to 3.6V
Supply Voltage: AVDD to DVDD, AGND to DGND . . . . . . . . . . –0.5V to 0.5V
Digital Input Voltage Range to DGND . . . . . . . . . . . . –0.5V to DVDD + 0.5V
Analog Input Voltage Range to AGND . . . . . . . . . . . . . –0.5V to AVDD + 0.5V
Digital Output Voltage Applied from Ext. Source to DGND . . . . . . . –0.5V to DVDD + 0.5V
Reference Voltage Input Range to AGND: VREFT, VREFB . . . . . . –0.5V to AVDD + 0.5V
Operating Free-Air Temperature Range, TA (ADS5203I) . . . –40°C to +85°C
Storage Temperature Range, TSTG . . . . . . . . . . . . . . . . . . –65°C to +150°C
Soldering Temperature 1.6mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . 300°C
(1) Stresses above these ratings may cause permanent damage. Exposure to
absolute maximum conditions for extended periods may degrade device
reliability. These are stress ratings only, and functional operation of the device
at these or any other conditions beyond those specified is not implied.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range, TA, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
3.0
3.3
3.6
V
Power Supply
AVDD
DVDD
DRVDD
Supply
Su
ly Voltage
Analog and Reference Inputs
Reference Input Voltage (top)
Reference Input Voltage (bottom)
Reference Voltage Differential
VREFT
VREFB
VREFT – VREFB
Reference Input Resistance
Reference Input Current
Analog Input Voltage, Differential
Analog Input Voltage, Single–Ended(1)
Analog Input Capacitance
Clock Input(2)
RREF
IREF
fCLK = 1MHz to 80MHz
fCLK = 1MHz to 80MHz
fCLK = 1MHz to 80MHz
fCLK = 80MHz
1.9
2.0
2.15
V
0.95
1.0
1.1
V
0.95
1.0
1.1
V
fCLK = 80MHz
VIN
VIN
CI
1650
Ω
0.62
mA
–1
1
CML – 1.0
CML + 1.0
8
0
V
V
pF
AVDD
V
Analog Outputs
CML Voltage
AVDD/2
2.3
CML Output Resistance
V
kΩ
Digital Inputs
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
2.4
Input Capacitance
Clock Period
DVDD
0.8
DGND
5
V
pF
12.5
ns
Clock HIGH or LOW
5.25
ns
25
ns
Pulse Duration
tw(CLKH) , tw(CLKL) (40MHz)
Clock HIGH or LOW
(1) Applies only when the signal reference input connects to CML.
(2) Clock pin is referenced to AVDD/AVSS.
11.25
ns
Pulse Duration
Clock Period
2
tc (80MHz)
tw(CLKH), tw(CLKL) (80MHz)
tc (40MHz)
V
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SBAS258A – JUNE 2002 – REVISED JULY 2002
ELECTRICAL CHARACTERISTICS
over recommended operating conditions with fCLK = 80MHz and use of internal voltage references, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply
AVDD
DVDD
DRVDD
IDD O
Operating
erating Su
Supply
ly Current
Power Dissipation
Standby Power
PD
PD(STBY)
tPD
56
62
AVDD = DVDD = DRVDD = 3.3V,
3 3V
CL = 10pF,
10pF fIN = 3.5MHz,
3 5MHz –1dBFS
1.7
2.2
15
26
PWDN_REF = ‘L’
240
290
PWDN_REF = ‘H’
220
240
95
150
STDBY = ‘H’, CLK Held HIGH or LOW
Power-Up Time for All References from Standby
Wake Up Time
tWU
External Reference
mA
mW
µW
550
ms
40
µs
Digital Inputs
High-Level Input Current on Digital Inputs incl. CLK
Low-Level Input Current on Digital Inputs incl. CLK
IIH
IIL
AVDD = DVDD = DRVDD = 3
3.6V
6V
–1
1
µA
–1
1
µA
Digital Outputs
High-Level Output Voltage
VOH
Low-Level Output Voltage
VOL
Output Capacitance
High-Impedance State Output Current to High-Level
High-Impedance State Output Current to Low-Level
CO
IOZH
IOZL
AVDD = DVDD = DRVDD = 3.0V at
IOH = 50µA, Digital Outputs Forced HIGH
AVDD = DVDD = DRVDD = 3.0V at
IOL = 50µA, Digital Outputs Forced LOW
2.8
0.04
V
0.2
V
+1
µA
+1
µA
5
AVDD = DVDD = DRVDD = 3
3.6V
6V
–1
–1
CLOAD = 10pF, Single–Bus Mode
CLOAD = 10pF, Dual–Bus Mode
Data Output Rise-and-Fall
Rise and Fall Time
2.96
pF
3
ns
5
ns
Reference Outputs
Reference Top Voltage
Reference Bottom Voltage
Differential Reference Votage
VREFTO
VREFBO
REFT – REFB
1.9
2
2.1
V
0.95
1
1.05
V
0.95
1.0
1.05
V
TA = –40°C
40°C to +85°C
–1.5
15
±0 4
±0.4
+1
+1.5
5
LSB
TA = –40°C to +85°C
–0.9
±0.5
+1
LSB
0.12
±1.5
%FS
0.28
±1.5
%FS
0.24
±1.5
%FS
Absolute Min/Max Values Valid and
Tested for AVDD = 3.3V
DC Accuracy
Integral Nonlinearity,
Nonlinearity End Point
Differential Nonlinearity
Missing Codes
Zero Error(3)
Full–Scale Error
Gain Error
INL
DNL
Internal
References(1)
Internal
References(2)
No Missing Codes Assured
AVDD = DVDD = DRVDD = 3
3.3V
3V
External References (3)
(1) Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full-scale. The point used as zero occurs ½LSB
before the first code transition. The full-scale point is defined as a level ½LSB beyond the last code transition. The deviation is measured from
the center of each particular code to the best-fit line between these two endpoints.
(2) An ideal ADC exhibits code transitions that are exactly 1LSB apart. DNL is the deviation from this ideal value. Therefore, this measure indicates
how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under test, (i.e., (last transition
level – first transition level)/(2n – 2)). Using this definition for DNL separates the effects of gain and offset error. A minimum DNL better than
–1LSB ensures no missing codes.
(3) Zero error is defined as the difference in analog input voltage—between the ideal voltage and the actual voltage—that will switch the ADC output
from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to ½LSB to the bottom reference level. The
voltage corresponding to 1LSB is found from the difference of top and bottom references divided by the number of ADC output levels (1024).
Full-scale error is defined as the difference in analog input voltage—between the ideal voltage and the actual voltage—that will switch the ADC
output from code 1022 to code 1023. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5LSB from the top
reference level. The voltage corresponding to 1LSB is found from the difference of top and bottom references divided by the number of ADC
output levels (1024).
3
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SBAS258A – JUNE 2002 – REVISED JULY 2002
DYNAMIC PERFORMANCE(1)
TA = TMIN to TMAX, AVDD = DVDD = DRVDD = 3.3V, fIN = –1dBFS, Internal Reference, fCLK = 80MHz, fS = 40MSPS, and Differential Input Range = 2Vp–p,
unless otherwise noted.
PARAMETER
Effective Number of Bits
Total Harmonic Distortion
Signal-to-Noise
g
Ratio
Signal-to-Noise
g
Ratio + Distortion
TEST CONDITIONS
ENOB
THD
SNR
SINAD
fIN = 3.5MHz
fIN = 10.5MHz
SFDR
Analog Input Bandwidth
2-Tone Intermodulation Distortion
A/B Channel Crosstalk
A/B Channel Offset Mismatch
IMD
9.3
fIN = 20MHz
fIN = 3.5MHz
TYP
MAX
UNIT
9.7
Bits
9.7
Bits
9.6
Bits
–71
dB
fIN = 10.5MHz
fIN = 20MHz
–71
–68
dB
fIN = 3.5MHz
fIN = 10.5MHz
60.5
dB
60.5
dB
fIN = 20MHz
fIN = 3.5MHz
60
dB
60
dB
60
dB
60
dB
75
dB
73
dB
fIN = 10.5MHz
fIN = 20MHz
Spurious-Free Dynamic
y
Range
g
MIN
fIN = 3.5MHz
fIN = 10.5MHz
57
69
–66
dB
fIN = 20MHz
See Note (2)
70.5
dB
300
MHz
f1 = 9.5MHz, f2 = 9.9MHz
–68
dBc
–75
0.016
dBc
1.75
% FS
A/B Channel Full-Scale Error Mismatch
0.016
1.0 % FS
(1) These specifications refer to a 25Ω series resistor and 15pF differential capacitor between A/B+ and A/B– inputs; any source impedance will
bring the bandwidth down.
(2) Analog input bandwidth is defined as the frequency at which the sampled input signal is 3dB down on unity gain and is limited by the input switch
impedance.
4
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SBAS258A – JUNE 2002 – REVISED JULY 2002
PIN CONFIGURATION
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
DA 9..0
NO.
1,13
12, 24
14-23
DB 9..0
2-11
O
48
26
I
O
Output Enable. A LOW on this terminal will enable the data output bus, COUT and COUT.
O
I
I
I
Inverted Latch Clock or multiplexer control for the Data Outputs. COUT is in tri-state during power–down.
DVSS
CLK
25
44
43
47
DVDD
AVDD
45
27,37,41
I
I
MODE
REFT
46
28,36,40
35
34
31
I
I
I
I
I/O
REFB
30
I/O
CML
32
O
PDWN_REF
33
42
39
38
29
I
I
I
I
DRVDD
DRVSS
OE
COUT
COUT
SELB
AVSS
B–
B+
STBY
A–
A+
TP
I
I
O
Supply Voltage for Output Drivers
Digital Ground for Output Drivers
Data Outputs for Bus A. D9 is MSB. This is the primary bus. Data from both input channels can be output on this bus
or data from the A channel only. Pins SELB and MODE select the output mode. The data outputs are in tri-state during
power-down (refer to Timing Options table).
Data Outputs for Bus B. D9 is MSB. This is the second bus. Data is output from the B-channel when dual bus output mode
is selected. The data outputs are in tri-state during power-down and single-bus modes (refer to Timing Options table).
Latch Clock for the Data Outputs. COUT is in tri-state during power-down.
Selects either single-bus data output or dual-bus data output. A LOW selects dual-bus data output.
Digital Ground
Clock Input. The input is sampled on each rising edge of CLK when using a 40MHz input and alternate rising edges when
using an 80MHz input. The clock pin is referenced to AVDD and AVSS to reduce noise coupling from digital logic.
Digital Supply Voltage
Analog Supply Voltage
Selects the COUT and COUT output mode.
Analog Ground
Negative Input for the Analog B Channel
Positive Input for the Analog B Channel
Reference Voltage Top. The voltage at this terminal defines the top reference voltage for the ADC. Sufficient filtering
should be applied to this input: the use of 0.1µF capacitor between REFT and AVSS is recommended. Additionally a 0.1µF
capacitor should be connected between REFT and REFB.
Reference Voltage Bottom. The voltage at this terminal defines the bottom reference voltage for the ADC. Sufficient
filtering should be applied to this input: the use of 0.1µF capacitor between REFB and AVSS is recommended. Additionally
a 0.1µF capacitor should be connected between REFT and REFB.
Common-Mode Level. This voltage is equal to (AVDD – AVSS)/2. An external capacitor of 0.1µF should be connected
between this terminal and AVSS when CML is used as a bias voltage. No capacitor is required if CML is not used.
Power-Down for Internal Reference Voltages. A HIGH on this terminal disables the internal reference circuit.
Standby Input. A HIGH on this terminal will power down the device.
Negative Input for the Analog A Channel
Positive Input for Analog A Channel
This pin must be connected to DVDD. It should not be left floating.
5
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SBAS258A – JUNE 2002 – REVISED JULY 2002
TIMING REQUIREMENTS
PARAMETER
Input Clock Rate
TEST CONDITIONS
MIN
fCLK
Conversion Rate
MAX
UNIT
1
TYP
80
MHz
1
40
MSPS
Clock Duty Cycle (40MHz)
45
50
55
%
Clock Duty Cycle (80MHz)
42
50
58
%
9
14
ns
Output Delay Time
td(o)
CL = 10pF
Mux Setup Time
ts(m)
9
10.4
ns
Mux Hold Time
th(m)
1.7
2.1
ns
Output Setup Time
ts(o)
CL = 10pF
9
10.4
ns
Output Hold Time
th(o)
CL = 10pF
1.5
2.2
ns
Pipeline Delay (latency, channels A and B)
td(pipe)
MODE = 0, SELB = 0
8
CLK Cycles
Pipeline Delay (latency, channels A and B)
td(pipe)
MODE = 1, SELB = 0
4
CLK Cycles
Pipeline Delay (latency, channel A)
td(pipe)
MODE = 0, SELB = 1
8
CLK Cycles
Pipeline Delay (latency, channel B)
td(pipe)
MODE = 0, SELB = 1
9
CLK Cycles
Pipeline Delay (latency, channel A)
td(pipe)
MODE = 1, SELB = 1
8
CLK Cycles
Pipeline Delay (latency, channel B)
td(pipe)
MODE = 1, SELB = 1
9
CLK Cycles
ns
Aperture Delay Time
td(a)
3
Aperture Jitter
tJ(a)
1.5
Disable Time, OE Rising to Hi–Z
tdis
5
8
ns
Enable Time, OE Falling to Valid Data
ten
5
8
ns
ps, rms
TIMING OPTIONS
MODE
SELB
TIMING DIAGRAM FIGURE
80MHz Input Clock, Dual-Bus Output, COUT = 40MHz
OPERATING MODE
0
0
1
40MHz Input Clock, Dual-Bus Output, COUT = 40MHz
1
0
2
80MHz Input Clock, Single-Bus Output, COUT = 40MHz
0
1
3
80MHz Input Clock, Single-Bus Output, COUT = 80MHz
1
1
4
6
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SBAS258A – JUNE 2002 – REVISED JULY 2002
TIMING DIAGRAMS
Sample A1 and B1
Analog_A
Analog_B
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CLK(1)
CLK40INT(2)
td(pipe)
ADCOUTA[9:0](3)
A1
A2
A3
A4
A5
B1
td(o)
B2
B3
B4
B5
td(pipe)
ADCOUTB[9:0](3)
DA[9:0]
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
A&B 4
A&B 5
td(o)
DB[9:0]
DAB[19:0] is used to illustrate the placement of the busses DA and DB
DAB[19:0]
A&B 1
A&B 2
ts(o)
th(o)
A&B 3
COUT
COUT
NOTES: (1) In this option CLK = 80MHz. (2) CLK40INT refers to 40MHz Internal Clock, per channel. (3) Internal signal only.
Figure 1. Dual Bus Output—Option 1.
Sample A1 and B1
Analog_A
Analog_B
1
2
3
4
5
6
7
8
9
10
CLK(1)
td(pipe)
ADCOUTA[9:0](2)
A1
A2
A3
A4
A5
B1
td(o)
B2
B3
B4
B5
td(pipe)
ADCOUTB[9:0](2)
DA[9:0]
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
A&B 3
A&B 4
A&B 5
td(o)
DB[9:0]
DAB[19:0] is used to illustrate the combined busses DA and DB
DAB[19:0]
A&B 1
A&B 2
ts(o)
th(o)
COUT
COUT
NOTE: (1) In this option CLK = 40MHz, per channel. (2) Internal signal only
Figure 2. Dual Bus Output—Option 2.
7
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SBAS258A – JUNE 2002 – REVISED JULY 2002
TIMING DIAGRAMS (Cont.)
Sample A1 and B1
Analog_A
Analog_B
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CLK(1)
CLK40INT(2)
td(pipe)
ADCOUTA[9:0](3)
A1
A2
A3
A4
A5
B1
td(o)
B2
B3
B4
B5
td(pipe)
ADCOUTB[9:0](3)
td(o)
DA[9:0]
A1 B1
A2 B2
A3 B3
th(o)
A4 B4
A5 B5
ts(o)
COUT
th(o)
ts(o)
COUT
NOTES: (1) In this option CLK = 80MHz. (2) CLK40INT refers to 40MHz Internal Clock, per channel. (3) Internal signal only.
Figure 3. Single Bus Output—Option 1.
Sample A1 and B1
Analog_A
Analog_B
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CLK(1)
CLK40INT(2)
td(pipe)
ADCOUTA[9:0](3)
A1
A2
A3
A4
A5
B1
td(o)
B2
B3
B4
B5
td(pipe)
ADCOUTB[9:0](3)
td(o)
DA[9:0]
A1 B1
th(o)
A2 B2
A3 B3
A4 B4
A5 B5
ts(o)
COUT
ts(m)
th(m)
COUT
NOTES: (1) In this option CLK = 80MHz. (2) CLK40INT refers to 40MHz Internal Clock, per channel. (3) Internal signal only.
Figure 4. Single Bus Output—Option 2.
8
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SBAS258A – JUNE 2002 – REVISED JULY 2002
TYPICAL CHARACTERISTICS
At TA = 25°C, AVDD = DVDD = DRVDD = 3.3V, fIN = –0.5dBFS, Internal Reference, fCLK = 80MHz, fS = 40MSPS, Differential Input Range = 2Vp-p,
25Ω series resistor, and 15pF differential capacitor at A/B+ and A/B– inputs, unless otherwise noted.
9
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SBAS258A – JUNE 2002 – REVISED JULY 2002
Typical Characteristics (Cont.)
At TA = 25°C, AVDD = DVDD = DRVDD = 3.3V, fIN = –0.5dBFS, Internal Reference, fCLK = 80MHz, fS = 40MSPS, Differential Input Range = 2Vp-p,
25Ω series resistor, and 15pF differential capacitor at A/B+ and A/B– inputs, unless otherwise noted.
10
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SBAS258A – JUNE 2002 – REVISED JULY 2002
PRINCIPLE OF OPERATION
The ADS5203 implements a dual high-speed, 10-bit,
40MSPS converter in a cost-effective CMOS process.
The differential inputs on each channel are sampled
simultaneously. Signal inputs are differential and the
clock signal is single-ended. The clock signal is either
80MHz or 40MHz, depending on the device
configuration set by the user. Powered from 3.3V, the
dual-pipeline design architecture ensures low-power
operation and 10-bit resolution. The digital inputs are
3.3V TTL/CMOS compatible. Internal voltage
references are included for both bottom and top
voltages. Alternatively, the user may apply externally
generated reference voltages. In doing so, the input
range can be modified to suit the application.
The ADC is a 5-stage pipelined ADC with 4 stages of
fully-differential switched capacitor sub-ADC/MDAC
pairs and a single sub-ADC in stage 5. All stages deliver
2 bits of the final conversion result. A digital error
correction is used to compensate for modest
comparator offsets in the sub-ADCs.
The analog input signal is sampled on capacitors CSP
and CSN while the internal device clock is low. The
sampled voltage is transferred to capacitors CHP and
CHN and held on these while the internal device clock
is high. The SHA can sample both single-ended and
differential input signals.
The load presented to the AIN pin consists of the
switched input sampling capacitor CS (approximately
2pF) and its various stray capacitances. A simplified
equivalent circuit for the switched capacitor input is
shown in Figure 6. The switched capacitor circuit is
modeled as a resistor RIN. fCLK is the clock frequency,
which is 40MHz at full speed, and CS is the sampling
capacitor. Using 25Ω series resistors and a differential
15pF capacitor at the A/B+ and A/B– inputs is
recommended to reduce noise.
NOTE: AIN can be any variation
of A or B inputs.
fCLK = 40MHz
SAMPLE-AND-HOLD AMPLIFIER
Figure 5 shows the internal SHA architecture. The
circuit is balanced and fully differential for good supply
noise rejection. The sampling circuit has been kept as
simple as possible to obtain good performance for
high-frequency input signals.
VCM
VCM = 0.5 S (V(A/B+) + V(A/B–))
Figure 6. Equivalent Circuit for the Switched
Capacitor Input.
ANALOG INPUT, DIFFERENTIAL
CONNECTION
Figure 5. SHA Architecture.
The analog input of the ADS5203 is a differential
architecture that can be configured in various ways
depending on the signal source and the required level
of performance. A fully differential connection will
deliver the best performance from the converter. The
analog inputs must not go below AVSS or above AVDD.
The inputs can be biased with any common-mode
voltage provided that the minimum and maximum input
voltages stay within the range AVSS to AVDD. It is
recommended to bias the inputs with a common-mode
voltage around AVDD/2. This can be accomplished
easily with the output voltage source CML, which is
equal to AVDD/2. CML is made available to the user to
help simplify circuit design. This output voltage source
is not designed to be a reference or to be loaded but
makes an excellent DC bias source and stays well
within the analog input common-mode voltage range
over temperature.
11
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SBAS258A – JUNE 2002 – REVISED JULY 2002
Table 1 lists the digital outputs for the corresponding
analog input voltages.
Table 1. Output Format for Differential Configuration
DIFFERENTIAL INPUT
VIN = (A+/B+) – (A–/B–), REFT – REFB = 1V
ANALOG INPUT VOLTAGE
DIGITAL OUTPUT CODE
VIN = +1V
3FFH
VIN = 0
200H
VIN = –1V
000H
DC–COUPLED DIFFERENTIAL ANALOG
INPUT CIRCUIT
Driving the analog input differentially can be achieved
in various ways. Figure 7 gives an example where a
single-ended signal is converted into a differential signal
by using a fully differential amplifier such as the
THS4141. The input voltage applied to VOCM of the
THS4141 shifts the output signal into the desired
common-mode level. VOCM can be connected to CML
of the ADS5203, the common-mode level is shifted to
AVDD/2.
Figure 8.
AC-Coupled Differential
Transformer.
Input
with
ANALOG INPUT, SINGLE–ENDED
CONFIGURATION
For a single-ended configuration, the input signal is
applied to only one of the two inputs. The signal applied
to the analog input must not go below AVSS or above
AVDD. The inputs can be biased with any common-mode
voltage provided that the minimum and maximum input
voltage stays within the range AVSS to AVDD. It is
recommended to bias the inputs with a common-mode
voltage around AVDD/2. This can be accomplished easily
with the output voltage source CML, which is equal to
AVDD/2. An example for this is shown in Figure 9.
Figure 7. Single-Ended to Differential Conversion
Using the THS4141.
Figure 9. AC–Coupled, Single-Ended Configuration.
AC–COUPLED DIFFERENTIAL ANALOG
INPUT CIRCUIT
Driving the analog input differentially can be achieved by
using a transformer-coupling, as illustrated in Figure 8.
The center tap of the transformer is connected to the voltage source CML, which sets the common-mode voltage
to AVDD/2. No buffer is required at the output of CML since
the circuit is balanced and no current is drawn from CML.
12
The signal amplitude to achieve full scale is 2Vp-p. The
signal, which is applied at A/B+ is centered at the bias
voltage. The input A/B– is also centered at the bias
voltage. The CML output is connected via a 4.7kΩ
resistor to bias the input signal. There is a direct
DC-coupling from CML to A/B– while this input is
AC-decoupled through the 10µF and 0.1µF capacitors.
The decoupling minimizes the coupling of A/B+ into the
A/B– path.
www.ti.com
SBAS258A – JUNE 2002 – REVISED JULY 2002
Table 2 lists the digital outputs for the corresponding
analog input voltages.
Table 2. Output Format for Single-Ended Configuration.
SINGLE–ENDED INPUT, REFT – REFB = 1V
ANALOG INPUT VOLTAGE
DIGITAL OUTPUT CODE
V(A/B+) = VCML + 1V
3FFH
V(A/B+) = VCML
200H
V(A/B+) = VCML – 1V
000H
REFERENCE TERMINALS
The ADS5203’s input range is determined by the voltages
on its REFB and REFT pins. The ADS5203 has an internal voltage reference generator that sets the ADC reference voltages REFB = 1V and REFT = 2V. The internal
ADC references must be decoupled to the PCB AVSS
plane. The recommended decoupling scheme is shown
in Figure 10. The internal reference voltages commonmode voltage is 1.5V.
DIGITAL INPUTS
Digital inputs are CLK, STDBY, PWDN_REF, OE, MODE,
and SELB. These inputs don’t have a pull-down resistor
to ground, therefore, they should not be left floating.
The CLK signal at high frequencies should be considered
as an ‘analog’ input. CLK should be referenced to AVDD
and AVSS to reduce noise coupling from the digital logic.
Overshoot/undershoot should be minimized by proper
termination of the signal close to the ADS5203. An
important cause of performance degradation for a
high-speed ADC is clock jitter. Clock jitter causes
uncertainty in the sampling instant of the ADC, in addition
to the inherent uncertainty on the sampling instant caused
by the part itself, as specified by its aperture jitter. There
is a theoretical relationship between the frequency f and
resolution (2N) of a signal that needs to be sampled on
one hand, and on the other hand the maximum amount
of aperture error dtmax that is tolerable. It is given by the
following relation:
dtmax = 1/[π f 2(N+1)]
As an example, for a 10-bit converter with a 20MHz input,
the jitter needs to be kept less than 7.8ps in order not to
have changes in the LSB of the ADC output due to the
total aperture error.
DIGITAL OUTPUTS
Figure 10. Recommended External Decoupling for
the Internal ADC Reference.
External ADC references can also be chosen. The
ADS5203 internal references must be disabled by tying
PWDN_REF HIGH before applying the external
reference sources to the REFT and REFB pins. The
external reference voltages common-mode voltage
should be 1.5V for best ADC performance.
The output of ADS5203 is an unsigned binary code.
Capacitive loading on the output should be kept as low as
possible (a maximum loading of 10pF is recommended)
to ensure best performance. Higher output loading
causes higher dynamic output currents and can,
therefore, increase noise coupling into the part’s analog
front end. To drive higher loads, the use of an output buffer
is recommended.
When clocking output data from ADS5203, it is important
to observe its timing relation to COUT. Please refer to the
timing section for detailed information on the pipeline
latency in the different modes.
For safest system timing, COUT and COUT should be used
to latch the output data, (see Figures 1 to 4). In Figure 4,
COUT can be used by the receiving device to identify
whether the data presently on the bus is from channel A
or B.
LAYOUT, DECOUPLING, AND GROUNDING
RULES
Figure 11. External ADC Reference Configuration.
Proper grounding and layout of the PCB on which the
ADS5203 is populated is essential to achieve the stated
performance. It is advised to use separate analog and
digital ground planes that are spliced underneath the IC.
The ADS5203 has digital and analog pins on opposite
sides of the package to make this easier. Since there is
no connection internally between analog and digital
grounds, they have to be joined on the PCB. It is advised
to do this at one point in close proximity to the ADS5203.
13
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SBAS258A – JUNE 2002 – REVISED JULY 2002
As for power supplies, separate analog and digital
supply pins are provided on the part (AVDD/DVDD). The
supply to the digital output drivers is kept separate as
well (DRVDD). Lowering the voltage on this supply to
3.0V instead of the nominal 3.3V improves performance
because of the lower switching noise caused by the
output buffers.
Due to the high sampling rate and switched-capacitor
architecture, the ADS5203 generates transients on the
supply and reference lines. Proper decoupling of these
lines is, therefore, essential.
NOTES
1. Integral Nonlinearity (INL)—Integral nonlinearity
refers to the deviation of each individual code from a line
drawn from zero to full-scale. The point used as zero
occurs ½LSB before the first code transition. The
full-scale point is defined as a level ½LSB beyond the
last code transition. The deviation is measured from the
center of each particular code to the true straight line
between these two endpoints.
2. Differential Nonlinearity (DNL)—An ideal ADC
exhibits code transitions that are exactly 1LSB apart. DNL
is the deviation from this ideal value. Therefore, this
measure indicates how uniform the transfer function step
sizes are. The ideal step size is defined here as the step
size for the device under test (i.e., (last transition level –
first transition level)/(2n – 2)). Using this definition for DNL
separates the effects of gain and offset error.
A minimum DNL better than –1LSB ensures no missing
codes.
3. Zero and Full-Scale Error—Zero error is defined as
the difference in analog input voltage—between the
ideal voltage and the actual voltage—that will switch the
ADC output from code 0 to code 1. The ideal voltage
level is determined by adding the voltage corresponding
to ½LSB to the bottom reference level. The voltage
corresponding to 1LSB is found from the difference of
top and bottom references divided by the number of
ADC output levels (1024).
Full-scale error is defined as the difference in analog
input voltage—between the ideal voltage and the actual
voltage—that will switch the ADC output from code
1022 to code 1023. The ideal voltage level is
determined by subtracting the voltage corresponding to
1.5LSB from the top reference level. The voltage
corresponding to 1LSB is found from the difference of
top and bottom references divided by the number of
ADC output levels (1024).
14
4. Analog Input Bandwidth—The analog input
bandwidth is defined as the max. frequency of a 1dBFS
input sine that can be applied to the device for which an
extra 3dB attenuation is observed in the reconstructed
output signal.
5. Output Timing—Output timing td(o) is measured
from the 1.5V level of the CLK input falling edge to the
10%/90% level of the digital output. The digital output
load is not higher than 10pF.
Output hold time th(o) is measured from the 1.5V level
of the COUT input rising edge to the 10%/90% level of
the digital output. The digital output is load is not less
than 2pF. Aperture delay td(A) is measured from the
1.5V level of the CLK input to the actual sampling
instant.
The OE signal is asynchronous. OE timing tdis is
measured from the VIH(MIN) level of OE to the
high-impedance state of the output data. The digital
output load is not higher than 10pF. OE timing ten is
measured from the VIL(MAX) level of OE to the instant
when the output data reaches VOH(min) or VOL(max)
output levels. The digital output load is not higher than
10pF.
6. Pipeline Delay (latency)—The number of clock
cycles between conversion initiation on an input sample
and the corresponding output data being made
available from the ADC pipeline. Once the data pipeline
is full, new valid output data is provided on every clock
cycle. The first valid data is available on the output pins
after the latency time plus the output delay time td(o)
through the digital output buffers. Note that a minimum
td(o) is not guaranteed because data can transition
before or after a CLK edge. It is possible to use CLK for
latching data, but at the risk of the prop delay varying
over temperature, causing data to transition one CLK
cycle earlier or later. The recommended method is to
use the latch signals COUT and COUT which are
designed to provide reliable setup and hold times with
respect to the data out.
7. Wake-Up Time—Wake-up time is from the
power-down state to accurate ADC samples being
taken, and is specified for external reference sources
applied to the device and an 80MHz clock applied at the
time of release of STDBY. Cells that need to power up
are the bandgap, bias generator, SHAs, and ADCs.
8. Power-Up Time—Power-up time is from the
power-down state to accurate ADC samples being
taken with an 80MHz clock applied at the time of release
of STDBY. Cells that need to power up are the bandgap,
internal reference circuit, bias generator, SHAs, and
ADCs.
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SBAS258A – JUNE 2002 – REVISED JULY 2002
PACKAGE DRAWING
15
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
ADS5203IPFB
ACTIVE
TQFP
PFB
48
250
ADS5203IPFBR
ACTIVE
TQFP
PFB
48
1000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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