ETC AK2358A

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[AK2358AI
ASAHI KASEI
1
F e a t u r e s
i
•1
•1
•1
•1
•1
•1
❑
•1
•1
❑
•1
❑
•1
•1
❑
•1
•1
❑
Built-in voice filter for cordless telephone, MSK MODEM (2400bps), COMPANDOR, and
scrambler circuit
Low / wide operation voltage range (1.9 V to 5. 5V)
Built-in COMPANDOR output transient response circuit and time constant circuit
No external component is needed for COMPANDOR
Built-in buffer amplifier for ceramic receiver driving.
Built-in electronic volume for ❑ icrophone sensitivity and modulator/demodulator
sensitivity
Receiving level switchable in 8 steps (-12 to +9dB)
Built-in muting function for voice transmitting and receiving
External adjustment for the limiter levelBuilt-in amplifier for transmission and reception gain adjustment
Low power CMOS and power-down function
Built-in 3.58MHz oscillator circuit
Scrambler circuit with frequency inversion. Two inversion frequencies can be
selected.
Bypassing the scrambler circuit available
Built-in frame detection function for the MSK demodulator
Control register and MSK MODEM data buffer controlled by serial interface
Few external component is necessary resulting cost reduction and small set size.
Package: 24 pin VSOP
1
B l o c k
D i a g r a m
microphone input
I
Transmission signal
output
3. 58MEz
T% D a t a / l x D a t a
Control data
frase d e t e c t i o n
Receptlnn s i g n a l
Receiver
Input
Recept 100 o u t p u t
1996 12
0151 E-00
-1
0
ul
m
M
o
.
A
I
T
.
5
4
I
I
I
.......................
TXAFSW
3:
TXHPF
+VR1
....................
Scrambler ~
Limiter
~zl!v
9
TDATA
TCLK
DIR
T
SCLK
D1/O
RDF/FD
Compressor
A
4
~ data buffer ~
--1- ~~~~a~isj ~
TC
IISK
_
Modulator
—
v
IISK
Demodulator
1
IISKHPF
9
v
N
BUFON
“
~
0
“ ” ~
I
I
..............
De-
‘r
RXAFSW
:., . . . . . . . . . . .
Re eiver 2
L
BUFOP
J
RECSW , . . . . . . . . . . . . . . . . .
*:-j
N3
44
“J&
I
Expander
4
\AMp3 j
‘3 . . . . . . . . . . . .
%
co
w
VR4
p# emphasis
+
De~
Scrambler
RXHPF
e
hJ22..j
n
>
Operating mode
E
cd
m
a.
[AK2358AI
ASAHI KASEI
1
D e s c r i p t i o n
I
The AK2358A, a base-band LSI for cordless telephone, has built-in voice filters, a 2400bps
MSK MODEM for data communication, a frame detection circuit, a COMPANDOR for noise
reduction, and scrambler circuits.
The CMOS process provides low power operation. Application of 24 pin VSOP package with
the feature of significant reduction of external component provides minimum mounting area.
The time constant circuit for the COhlPANDOR output transient response is built into the
LSI.
Using a 2400bps MSK MODEM for data communication has realized high data reliability and
high speed communication at the same time.
This LSI is suitable for cordless system telephones etc. which requires complicated
protocol control.
An oscillation circuit with a 3.58MHz crystal oscillator is built in, and no other
frequency source is required for the MSK MODEM. The oscillator also can be used for the
other DTMF generator etc.
The scrambler circuit uses the simple Inversion method with inversion of the voice
spectrum around the carrier frequency. Two inversion frequencies can be selected.
Built-in electronic volumes provided for transmission and reception part realize automatic
adjustment of the ❑ icrophone sensitivity and the modulator/demodulator sensitivity by
external EEPROM and ❑ icroprocessor.
The transmission part is composed of high-pass filter, compressor, pre-emphasis circuit,
scrambler, limiter, MSK modulator, splatter filter, electronic volume control, etc.
The reception part is composed of band pass filter, de-emphasis circuit, de-scrambler,
expander, buffer amplifier, MSK demodulator, frame detection circuit, electronic volume
control, etc.
■ Pin Arrangement
24 pin VSOP
lo
2 4 3 RAGND
2
2 3 -J RXIN
TXINC
3
2 2 -J RXINO
TXINOC
4
21 ~ BUFOP
LIMLVC
5
20 --J BUFON
MODC
6
19 -J RXAF
Vssc
7
18 3 RXAFIN
TCLKC
8
17 3 EXPOUT
TDATA~
9
16 3 VDD
DI/Oc
10
15 3 XIN
RDF/FDc
11
14 3
SCLK c
12
13 ~DIR
AGNDINC
TAGNDC
0151 E 00
XOUT
1996 12
[AK2358AI
ASAHI KASEI
C i r c u i t
[
Block
AMP1
TXHPF
Compressor
Pre-emphasis
Scrambler (Tx)
Limiter
Splatter filter
MSK modulator
AMP2
RXLPF
RXHPF
De-emphasis
De scrambler (Rx)
Expander
C o n f i g u r a t i o n
I
Function
The operational amplifier for voice signal transmission gain
adjustment and for the filter to eliminate aliasing noise by the
SCF(switched capacitor filter) in the following stage. Use an
external resistor and capacitor to set the gain less than 30dB and
the cut-off frequency to about 10kHz.
The SCF circuit to eliminate the low frequency component less
than 300Hz from the transmission voice signal.
The circuit to compress the amplitude of the transmission voice
signal.
The circuit to emphasis the high-frequency component of the
transmission voice signal to improve the S/N of the modulation
signal.
The circuit to inverse the transmission voice spectrum in regard
to the carrier frequency. Carrier frequency can be selected from
two frequencies by KEY. PCONT select to use the scrambler or the
pre-emphasis circuit.
The amplitude-limiting circuit to suppress the frequency deviation
of the modulation signal. The limitation level can be adjusted by
applying a DC voltage to the LIMLV pin. If the LIMLV pin is open,
the default limitation level is applied.
The SCF circuit to eliminate the high frequency component higher
than 3kHz from the limiter output signal or the MSK modulator
signal.
The circuit to generate a 2400bps MSK signal according to the
received digital signal logic from the TDATA pin.
The operational amplifier to adjust the reception demodulation
signal gain and for the filter to eliminate the aliasing noise of
the SCF in the following stage. Set the gain to less than 30dB
and the cut-off frequency to about 10kHz by external resister and
capacitor.
The SCF circuit to eliminate the high frequency component higher
than 3kHz from the limiter output signal or the MSK modulator
signal.
The SCF circuit to eliminate the low frequency component lower
than 300Hz from the reception voice signal.
The circuit to de-emphasis the emphasized signal by pre-emphasis
circuit.
The circuit to re- inverse the spectrum of the scrambled receiving
voice signal respect to the carrier frequency. Carrier frequency
can be selected from two candidates by a KEY. The de-scrambler(Rx)
or the de-emphasis circuit can be selected by PCONT.
The circuit to expand the signal amplitude compressed by the
compressor.
1996/’12
0151 Eoo
4-
ASAHI KASEI
[AK2358AI
Block
AMP3
7
r
AGND
Oscillation
circuit
VR1
P
VR2
VR3
r
VR4
Control register
and data buffer
Function
The operational amplifier used on the smoothing filter of the
reception SCF output. Set the gain to OdB and the cut-off
frequency to about 20kHz by external resister and capacitor.
The SCF circuit to eliminate the low frequency component lower
than 100Hz from the reception MSK signal.
The circuit to reproduce the 2400bps receiving data and the clock
from the received MSK signal in the RXIN pin.
The inverting and the non-inverting buffer amplifier to drive the
ceramic receiver.
The circuit to generate the reference voltage for the internal
analog signal.
The circuit to oscillate the 3.58 MHz reference clock using an
external crystal oscillator and resistor.
The volume to control the input amplitude of the transmission
voice signal. The adjustment range is -8dB to +7dB by ldB step.
The volume to control the MOD output amplitude. The adjustment
range is -4dB to +3.5dB by 0.5dB step.
The volume to control the input amplitude of the reception
demodulation signal. The adjustment range is -4dB to +3.5dB by
0.5dB step.
The volume to control the receiving voice amplitude. The
adjustment range is -12dB to +9dB by 3dB step.
The control register contlols the status of internal switches and
internal volumes of the LSI by serial data consists of 2 address
bits and 8 data bits. At the start up a power-on-reset circuit
works and the default values are set to the control register.
(see
control
I
Pin No.
1
map.)
Pin name
ACNDIN
P i n / F u n c t i o n
1 / 0
I
2
TAGND
o
3
TXIN
I
4
5
TXINO
LIMLV
o
0151 ”E-00
register
The data buffer stores 8 bits of the MSK receiving data to smooth
the signal interface with CPU.
I
I
Function
Analog ground input pin.
Connect the capacitor to stabilize the analog
ground.
Analog ground pin for the transmission system.
Connect the capacitor to stabilize the analog
ground.
Transmission voice input pin.
This is the inverting input pin for AMP1. It
composes a microphone amplifier with a ex~ernal
resister and a capacitor.
.4i111 output pin.
Limitation level adjustment pin.
The limitation level can be adjusted by applying a
I)C vollagc’ to this pin. The default limitation level
is adopted if no voltage is applied.
1996 12
ASAHI KASEI
Pin No.
6
[AK2358AI
Pin nane
1 / 0
MOD
o
7
8
Vss
—
TCLK
o
9
TDATA
I
DI/O
RFD/FD
1 / 0
11
12
13
14
SCLK
DIR
XOUT
I
I
I
15
16
17
18
X?N
VDD
EXPOUT
RXAFIN
o
19
RXAF
o
10
o
—
o
I
2 0
BUFON
21
22
23
BUFOP
RXINO
o
o
o
RXIN
I
24
RAGND
o
Function
Output pin of the modulated transmission signal.
A load impedance larger than 10kQ can be driven.
Negative power supply pin.
Clock output pin for the MSK data transmission.
A 2.4kHz clock is put out by setting the internal
register TDE to “O”. If the register is set to “l”,
it goes “H” level.
MSK transmission data input pin.
Data are latched synchronizing with the TCLK rising
edge.
Serial data input and output pin.
MSK signal reception flag output and Frame detection
signal output pin.
This pin puts out two types of information,
depending on the status of the internal register
FSL. If FSL is “l”, it is MSK signal reception mode,
so the pin reaches low after 8 bits of the MSK
reception signal have been written to the data
register. If FSL is “O”, it is the frame detection
signal output mode, so the low pulse is put out
after a frame pattern is detected.
Clock input pin for serial data 1/0.
Serial data 1/0 control pin.
Crystal oscillator connection pin.
The reference clock IC is generated by connecting a
3.58MHz crystal oscillator parallel to a lMQ
resistor between this pin and XIN pin. In case of
external clock operation, connect XOUT pin to YSS
and apply the clock to XIN.
Crystal oscillator connection pin.
Positive power supply pin.
Expander output pin.
Reception voice input pin.
This is the inverting input of AMP3. It composes a
smoothing filter by external resistor and capacitor.
Reception voice output pin.
This is the output pin of AMP3. A load impedance
more than 10kQ can be driven.
Receiver amplifier output pins.
Connect the ceramic receiver between these two pins.
f\MP2 output pin.
Demodulated receiving signal input pin.
This is the inverting input of AMP2. It composes a
prefilter with external resistor and capacitor.
\nalog ground pin for the reception system.
Connecl the capacitor to stabilize analog ground.
0151 E 00
1996:12
6
ASAHI KASEI
[AK2358AI
A b s o l u t e
I
Maximum
Ratings
1
VSS=OV; Note 1)
Parameter
Power supply voltage: (VDD)
Input current
(except the power supply pins)
Analog input voltage
Digital input voltage
Storage temperature
Symbol
VA+
min
max
Unit
“0.3
6.5
v
tlo
mA
IIN
VINA
-0.3
(VA+)+O.3
v
V,N~
Tstg
-0.3
-55
(VA+)+O. 3
130
v
“c
Note 1): All voltages with respect to the VSS pin.
Warning: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
I
R e c o m m e n d e d
O p e r a t i n g
C o n d i t i o n s
I
VSS=OV; Note 1)
Parameter
Operation temperature
Power supply voltage: (VDD)
Analog reference voltage
Current consumption
Mode O
Mode 1
Mode 2
Mode 3
Symbol
Ta
VD+
AGND
IddO
Iddl
Idd2
Idd3
min
-lo
1.9
typ
max
Unit
70
“c
2.0
l/2VD+
5.5
v
0.1
0.8
1.9
2.9
10
mA
0.9
1.4
5.5
v
Note 1): All voltages with respect to the VSS pin.
0151-E-00
1996 12
- 7
ASAHI KASEI
[AK2358AI
A n a l o g
1
C h a r a c t e r i s t i c
s
I
f=lkHz, PCONT=”l”, TC=”l”, EM=”l”, VR1 to VR4=OdB: unless otherwise specified,
OdBm=O.775Vrms
OdBx=-5dBm at AVDD=2V Note 8)
1) TX system
Parameter
Standard input level
@TXINO
Absolute gain
TXINO-MOD
Note 1)
Limiter level
JiOD lkHz
Note 1)
No external R
Adjustment range by
external R
Compressor linearity TXINO-MOD Note 1) 2)
TXINO=-44dBx
I
TXINO=-50dBx
Noise without input
TXINO~MOD
Note 1) 3)
Compressor distortion TXINO+MOD
TXINO=-10dBx
Transmission MSK
@MOD
Note 1)
signal level
1.2kHz signal output
Transmission MSK
@MOD
Note 1)
signal distortion
1.2kHz signal output
typ
min
max
Unit
dBx
dB
-lo
2.0
3.5
5.0
-4.5
-3.5
-2.5
-2.5
-20
-24
-4.5
]
-17.0
-20.0
-3.5
I
I
dBx
-14
-16
-36.5
I dB
dBm
-35
dB
-2.5
dBx
-32
dB
2) RX system
Parameter
Standard input level
@RXINO
Absolute gain
RXINO-BUFON,BUFOP
Note 1)
RXINO-BUFON,BUFOP
Expander linearity
Note 1) 4)
RXINO=-25dBx
RXINO=-30dBx
RXINO-BUFON,BUFOP
Noise with no input
Note 1) 3 )
Expander distortion
RXINO+RXAF
RXINO=-5dBx
Reception MSK
@RXINO
signal level
1.2kHz signal output
0151-E-00
min
-1.5
-33.0
-45.0
-14
typ
-lo
0
-30.0
“40. o
-7
max
I
Unit
dBx
+1.5
dB
-27.0
dB
-35.0
-70
dBm
-35
dB
-1
dBx
1996 12
-8
ASAHI KASEI
[AK2358AI
3) Overall characteristics
Parameter
Absolute gain TXINO~BUFON, BUFOP
Note 5)
TXINO=-10dBx KEY=”O” or “1”
TXINO~BUFON, BUFOP Note 3) 5)
Distortion
TXINO=-10dBx KEY=”O” or “l”
Crosstalk
@BUFON,BUFOP
Note 1)
Transmission ~ Reception
TC=”O”
TXINO=OdBx
@MOD
Crosstalk
Note 1)
Reception ~ Transmission
T.~=?*(j.
RXINO=OdBx
typ
min
6)
max
o
6)
-50
+4. o
Unit
dB
-43
dB
-60
dBx
-56.5
dBx
7)
7)
4) Filter characteristics
Parameter
Transmission overall characteristics (See Fig.1)
TXINO ~ MOD
100Hz
TC=” O” EM=”l” PCONT=”l”
300Hz
Relative value with OdB gain
2. 5kHz
a t lkHz
3kHz
5kHz
Reception overall characteristics (See Fig.2)
RXINO ~ EXPOUT
100Hz
TC=” O” EM=”l” PCONT=”l”
250Hz
Relative value with OdB gain
300Hz
a t lkHz
3kHz
5kHz
min
typ
max
-12
6.5
6.5
-10.5
-40
-9
9.5
9
-10.5
8
8
12
10.5
-9
Unit
dB
9.5
-7
-4
13.5
dB
-7.5
-15
Note 1) With the external circuit shown in the application circuit example.
Note 2) Relative value with OdB as the MOD output level at the time of input of standard
input level (-10dBx) to TXINO.
Note 3) With the C-message filter.
Note 4) Relative value with OdB as the BUFON, BUFOP output level at the time of input of
standard input level (-10dBx) to RXINO.
Note 5) With the external circuit shown in the application circuit example.
Further, the AhlP2 gain should be -3.5dB, and MOD and RXIN should be in loop
connection.
Note 6) TC=,T,$$, PCONT=”O”
Note 7) ~c=~,()*~, PCONT=”O”
Note 8) The dBx is standardized unit valid for various power supply voltages from 1.9 to
5.5V. If the voltage is 2V, OdBx should be -5dBm. With the other voltage as X iV],
O d B x z -5 + 20 log (X2) [dBm].
0151-E 00
1996 12
ASAHI KASEI
[AK2358AI
•l Filter characteristics
GA IN(dB)
10
0
-lo
-20
-30
-40
-50
10
FREQUENCY
Fig. 1
-
Transmission overall characteristics
10
0
-lo
-20
-30
-40
-50
/
I
,02
,01
I
,03
,04
FREQUENCY
Fig. 2
Reception overall characteristics
ICI
“
ASAHI KASEI
[AK2358AI
L e v e l
[
D i a g r a m
I
1) TX system
UK
klodul ator
f-lkHz
TXINO
Pref i I ter
(AUP1)
OS30dB
TXAF
~
MOD
H~ddE3+w:i.H AUP j-=
Cross point
-lOdBx
O:jdB
Limiter level
-ldh
+3.5dB
0:: “~dB
.Scraable
....................
...............
-3. SdBx(USKs19nsl level)
$.5
-6.3dBx(referencs level)
..................
........ .......
................
14
...............
-23.5dBx
-Z6.sdnx
. . . . . . . . . . . . . . . . . . . . .,
...................
......................
....................
......................
.....................
2) RX system
f-1 kHz
RXINO
EXPOUT
RXAF
‘“~PJ:’Ho:~dBH’’’4’’”r=’c:’
-b.&t-
dBx
10
.
0
~~
-10
.
.
.
....
-23
-25
-20
I
-4, /
-45 j /
-50 /
-44d0x
I
I
“ “’””
Note) The dtlx is standardized unit valid for various power supply voltages from 1.9 to
5.5V. [f lhe voltage is 2V, OdBx should be 5dBm. With the other voltage as X [V],
OdBx
5 ~ 20 log (X/2) [dBml.
0151-E 00
1996/’12
11 “
ASAHI KASEI
[AK2358AI
Diz ital
I
C h a r a c t e r i s t i c
I
s
1 . DC Characteristics
Parameter
I
High-level input voltage 1
Low-level input voltage 1
Hi~h-level inuut voltage 2
Low-level input voltage 2
V1”’VD+
High-level input current
Low-level input current V,,’ov
Hizh-level outDut Voltaze I.H’O. lIIIA
l
Low-level
outDut voltage 1~,
I
Pin
]Svmbol] min I tvu I
max
I Unit I
v
I 70%VD+ I
(1)
~lH
I
30%VD+
/
v
(1)
VIL
v I
I 80!%VDti
I
(2)
VIH
v
20%VD+
(2)
VIL
10
PA
(l)(2)
IIH
PA
-lo
(l)(2)
IIL
90%VD+
v
(3)
v(-).
I
I 0.3 I v I
=0.6mAl (3) I Vfi, I
(l). TDATA. DI/O
(2) SCLK, DIR
(3) TCLK, RDF, DI/O
2. AC Characteristics
Parameter
Master clock frequency
MSK modulator timing
TDE Falling to TCLK Rising
TCLK period
TDE Rising to TXAFSW Falling
TDATA Set up time
TDATA Hold time
TDATA Hold time2
MSK demodulator timing
RCLK Period & FD pulse width
Serial data input timing
Clock pulse width 1
Clock pulse width 2
SDATA Set Up time
SDATA Hold time
DIR Set up time
DIR Hold time
DIR falling to SCLK falling time
SCLK;DIR input rising time
SCLK;DIR input falling time
RDF falling to SCLK falling time
SCLK rising to RDF falling time
I Svmbol I
f;lk
❑ in
T1
T2
T3
TS
TH
TH2
2
1
1
2
T
402.2
ta
tb
tc
td
te
tf
tg
th
ti
tj
tk
500
I
tvr) I
3.579545
!
max
208.3
416.7
ps
ps
ms
/us
/ls
,LLS
416.7
fis
ns
ns
ns
ns
ns
ns
ns
500
100
100
100
100
100
1
1
100
600
I Unit
MHz
/L S
jl S
ns
ns
199612
0151-E 00
12
[AK2358AI
TCLK
I
TX AFSW Note)
( Internal registsr )
TDE
Note)
( I n t e r n a l rsgister )
I
I
I
~~
~
::
I’DATA
MOD
Voice signal
Voice signal
MSK modulator
:
<
ta
:tb:
,,
,:.
:
SCLK
llJ1 . . . . . . . . . . . . . . . ..~
DI/O
..................
Ao
;.
Dl
$0
-~:
~
DIR
~“”””””””””””””””
-1
i
:tg~
w
:.....-.0. 8DVDD
SCLK/DIR input
Note) The timing to rewrite the internal registers TXAFSW and TDE is synchronized with the
falling edge of DIR.
o151-f”oo
-13-
.
)
1
\
1
1
1
C’4
:
1+
.
.
1
:
.
n
m.
s.
.
:
Q
a
0
4
a
n.
:.
IA
.-
>,.
.
*
—
a
L
*
:*
,
)
.
I
r
t-l
al
o
\
a
MSK demodulator
1996/12
ASAHI KASEI
[AK2358AI
I
R e g i s t e r
C o n t r o l
I
M a p
■ Register composition
Address
A l AO
D7
D6
D5
D4
Data
D3
D2
TDE
Control register 1
0
0
FSL
BS2
BS 1
FCLN
PCONT
Volume register
Volume register
Control register 2 +
volume register
Reception data register
o
1
0
1
1
1
1
RECSW
1
1
1
TC
FRPT
KEY
“SW
‘SW
VR4
VR1
VR2
EM
D1 DO
TXAF RXAF
VR3
MSK MODEM reception data
The-reception data register is a read only register, and the others are write only
registers.
The reception data register has no address information proceeding to the Data.
Set the all bits D4 to D7 of volume register address “01” to “l”. If they are set to “O”,
it changed to test mode,
■ Register map
1) Control register 1
Address
Al AO
o
0
(Default)
Data
D7
FSL
1
D6
BS2
1
D5
BS1
D4
FCLN
0
0
D3
PCONT
1
D2
TDE
1
D1
TXAFSW
DO
RXAFSW
0
0
a) Transmission signal control
TDE
1
1
TXAFSW
o
1
0
1
Transmission output
Voice signal
Mute
MSK signal
b) Reception signal control
RXAFSW
1
o
o
RECSW
—
1
RXAF
Mute
ON
0
ON
I BUFOP/BUFON
Mute
Mute
ON
c) Scrambler circuit ON/OFF
I
I
PCONT
1
!I
o
I
I
!1
I
BvDass (Scrambler OFF)
Scrambler works (ON)
0151-E-00
I
I
1996/12
-15-
AS.!HI KASEI
d) Frame detection circuit ON/OFF
FCLN
1
o
The frame detection function is not used (OFF).
The frame detection function is used (ON).
Note) FCLN automatically changes from O to 1 when a synchronized frame is detected.
e) Power-down mode
BS2
BS1
Mode name
1
o
1
o
1
1
0
0
modeO
m o d e l
mode2
mode3
Voice system +
transmission MSK
OFF
OFF
OFF
ON
Reception MSK
Oscillator
OFF
OFF
ON
ON
OFF
ON
ON
ON
f) RDF/FD selection
FSL
1
o
The MSK signal reception flag (RDF) is put out from the
RDF/FD pin.
The frame detection signal (FD) is put out from the RDF/FD
pin.
2) Control register 2
Address
Al AO
1
1
(Default)
Data name
KEY
FRPT
EM
TC
Data
D7
TC
1
D6
EM
1
D5
FRPT
D4
KEY
D3
0
1
1
I D2 I D1 I DO
VR3
0
0
0
Function
Carrier inverting frequency
“ 1 “: 3.107kHz
“O”: 3.290kHz
Frame detector detection pattern “l”: 1100010011010110 (base unit)
“O”: 1001001100110110 (portable unit)
Emphasis circuit
“ 1 “: Passage (ON)
“O”: Bypass (OFF)
COMPANDOR circuit
“l”: Passage (ON)
3) Volume register
Address
A l AO
o
1
1
0
1
1
Data
D7
1
VR23
TC
D6
1
VR22
EM
D5
1
\’R21
FRPT
D4
1
VR20
KEY
D3
RECSW
VR13
VR33
0151-E 00
D2
VR42
VR12
VR32
D1
VR41
VR1l
VR31
DO
VR40
VR1O
VR30
1996/12
16 -
ASAHI KASEI
[AK2358AI
a ) VR1 volume control
VR13
o
0
0
0
0
0
o
0
1
1
1
1
1
1
1
1
VR12
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VR1l
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VRIO
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VR21
VR31
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VR20
VR30
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Volume gain (dB)
–8. O
–7. o
–6. O
–5. o
–4. o
– 3 . 0
–2. o
– 1 . 0
0
+ 1 . 0
+2. o
+ 3 . 0
+4. o
+5. o
+6. O
+7. o
b) VR2, VR3 volume control
VR23
VR33
o
0
o
0
o
o
o
o
1
1
1
1
1
1
1
1
VR22
VR32
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Volume gain (dB)
–4. o
– 3 . 5
–3. o
– 2 . 5
– 2 . 0
– 1 . 5
– 1 . 0
–o. 5
0
+ 0 . 5
+1.0
+1.5
+ 2 . 0
+2.5
+3.0
+3.5
0151 -EOO
1996i12
17
-
ASAHI KASEI
[AK2358AI
c) VR4 volume contro
I
I
T242
VR41
o
o
o
0
0
0
–12
1
1
1
0
0
1
1
0
–9
–6
–3
0
+3
+6
+9
o
1
1
1
1
VR40
Volume ~ain (dB)
1
1
0
1
0
1
I
Note) By reset, the gain of all volumes are set to OdB and RECSW bit is changed
to “o”.
4) MSK MODEM reception data
Data
D7
RD7
Data name
RDO
t
RD7
D6
RD6
D5
RD5
D4
RD4
D3
RD3
D2
RD2
D1
RD1
Function
“1”:1.2kHz
“0”:2.4kHz
MSK reception data
RD7 is the first received data.
0151 E-00
18
DO
RDO
ASAHI KASEI
[AK2358AI
MSK
I
Modem
i
MSK signal transmission flow
MSK signal transmission
TDE=”O” and
TXAFSW=”l” a r e s e t .
:
MSK
transmission start
I
MSK transmission data
are transmitted
synchronized to TCLK.
: During MSK transmission
Transmission of the
N
: MSK data transm ssion comp etion
TDE= “1”
I
TXAFSW= “O”
I
: Switching to voice signal
(1) Set the serial register “TDE” to “O” and “TXAFSW” to “l”, so that ilSK transmission
state is provided.
(2) A 2400Hz clock is put out from TCLK. Synchronizing with lhe rising edge of TCLK,
AK2358A reads the MSK transmission data from TDATA pin and put out them to MOD pin.
bit, “TDE” of the serial
(3) After the transmission of the necessary number of signal
.
register is set to “l”.
(4) f\fterwards, before switcl ing to a voice signal transmission mode, wait at least 2ms
after “TDE” has set to “ “ to complete the MSK signal final bit transm ssion.
Then set TX}\FSW register to “o”.
0151-E-00
1996’12
-19”
[AK2358AI
ASAHI KASEI
MSK Signal Reception
USK signal reception
Y
I
FSL set to “O”.
: Set so that a frame detection signal (FD) is put out from
the RDF/FD pin.
>
r
N
: Synchronization frame detection?
: Reception voice mute
: Set so that an USK signal reception flag (RDF) is put out
from the RDF/FD pin.
N
: Reception of 8 bit of data?
Reception data read i ng
: Reading of 8 bit of data, change to ROF/FD= “H”
I
: Waiting for the next synchronization frame
(1) If the internal register “FCLN” is “O”, the internal nodes RDATA, RCLK are fixed to
“1”.
( 2 ) After a synchronization frame is detected, FD goes to “L” during the period “T”, then
FCLN is set to “l”.
(3) RDATA and RCLK put out the data following to the synchronized frame pattern, and these
are stored in the internal buffer.
(4) After 8 bit of reception data have been entered to the internal buffer, RDF goes “L”.
(5) After the CPU detect that RDF is “L”, it puts out 8 clock bits to SCLK, then read 8
bit of reception data from the SDATA pin.
(6) With input of 8 clock bits to SCLK, RDF goes “H”.
(7) Afterwards, by repeating the steps (4) and (5) the necessary data bits are read.
(8) After the necessary data have been read, DIR goes “H”, “FCLN” is set to “O” via the
serial interface, the internal nodes RDAT;\ and RCLK are set to “l”, then the system
waits for the next synchronization frame.
i
1996/12
0151”E-00
-20”
/
I
I
ASAHI KASEI
[AK2358AI
1
A p p l i c a t i o n
C i r c u i t
Example
I
ZApplication Circuit
OAMP 1
Use as a transmitting microphone amplifier.
The gain should be less than 30dB. To
eliminate high frequency noise component over than 100kHz from input signal, 1st order
or 2nd order anti-aliasing filter is necessary. The following drawing is one example of
the 2nd order anti-aliasing filter, which has 30dB gain and 10kHz cut-off frequency.
TXINO
~3
tJ
/ /\
A
C1=2200PF
C2=33PF
.
TXINR2
&
AblPl
Rl=R2=10k L?
cl
R3=330k Q
<
LS1
@Smoothing filter for MOD output signal
Realize low-pass filter to eliminate l12kHz clock signal component from MOD pin
output signal. The following is one example of the 1st order low-pass filter which has
8.7kHz cut-off frequency. 10kQ of the modulator load resistor provide 3.3dB signal
attenuation.
C2
R
R=3.9k Q
MOD
+-q
‘ll
‘L
cl=4700pF
C2=0. lpF
RL=lOk Q
(Load resistance of MOD)
0AMP2
The amplifier for the receiving gain adjustment and anti-aliasing filtering to
eliminate high frequency noise component over 100kHz. The gain should be less than 30dB.
The following is an example of the 2nd order low pass filter, which has 20 dB gain and
40kHz cut-off frequency.
..
RXINO
C1=560PF
C2=27PF
.
Rl=lOk Q
R2=9. lkC?
AMP2
R3=100k Q
<
LSI
0151 E 00
1996/12
21 -
[AK2358AI
ASAHI KASEI
OAMP3
The smoothing filter to eliminate 448kHz clock component from EXPOUT signal is
Adding the
provided by this amplifier. Also it works to adjust the receiving gain.
other pass signal may be possible. The following is one example of the 1st order low-pass
filter, which has OdB gain , 19kHz cut-off frequency.
IEXPOUT
C2 Ill
Cl=150pF
RXAFIN
C 2 = 0 . 0 2 2 ,uF
Rl=R2=56k Q
R2
cl
+
RXAF
@
AMP3 +
L S I
OAGND stabilizing capacitor
To stabilize the AGND potential, connect capacitors larger than 0.3LLF between TAGND
pin, RAGND pin and AVSS pin. Also between AGNDIN pin and AYSS pin some capacitor is
necessary to reduce the ripple of the power.
C=l #F
L S I
OVDD stabilizing capacitor
To reduce the noise on VDD, connect capacitors between VDD and VSS.
VDD
CI-22,UF
(Aluminium Electrolytic Capacitor)
VDD
cl
+
C2
C2-O.l,UF (Ceramic Capacitor)
Vss
*
<
L S I
1996/12
0151 E-00
22 -
ASAHI KASEI
[AK2358AI
OCrystal oscillator
- Crystal resonator , resistor and capacitors should be connected as shown Fig.3 for
on-chip oscillator operation.
- For external clock operation, if the high(H) level of the input clock signal
amplitude equals to or is greater than 1.5V, and the low(L) level equals to or is
smaller than 0.5V, then connection should be ❑ ade as shown in Fig.4.
If the input clock signal amplitude (peak-to-peak) equals to or is smaller than
IV, and equals to or is greater than 200mV, then AC coupling should be as
illustrated in Fig.5.
Fig.3
Fig.4
IT
XIN
O.OIPF
l~External clock signal
lM Q
I XOUT
fig.5
OLimit level adjusting resistor
The limiting level can be controled externally by applying DC voltage to LIMIV pin.
Applied DC voltage should be larger than TAGND, then the limiting level is shown as
TAGND*Va(V), while Va is the voltage between LIMIV and TAGND. Keeping LIMIV pin open
provides default limit level. See following example.
VDD
LIMLV
R=50k Q
R
.+!
L
S
Vss
I
0151 E 00
1996/12
23 -
ASAHI KASEI
I
[AK2358AI
P a c k a g e
I
■ Marking
HUHIRUNHHHH
AKM
AK2358A
o
XXXYZ
UHNIIHHIIHHH
[Contents of XXXYZI
XXX: Date of manufacture
Last digit of the year, week number of the year as 2 digits
Y: Production lot number
Z: Assembled place
■ Shape and dimensions of the package
24 pin VSOP
l-t%
0.1
!!P
(NN
$+
q’
—
Note:
Dimensions marked by *
do not include residual res in.
_
o
0-10.
Detail of part A
(Material] Resin: Low s[ress type epoxy resin
Lead frame: Cu
0151 E-00
1996/’12
24
IMPORTANT NOTICE
● These ~roducts andtheir specifications aresubject tochange without notice. Eeforeconsidering anyuseor application,
Ltd. (AKMI
consult the Asahi Kasei Microsystems Co..
.,
, sales office or authorized distributor concerning their current
status.
● AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of
any information contained herein.
● Any export of these products, or devices or systems containing therm, may require an export license or other official
approval under the Iaw and regulations otthecountry of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
● ✌AKM pro&cts are neither intended nor authorized for use as critical components in any safety, life support, or other
hazard related device orsystem, and AKM assumes no responsibility relating to any such use, except with the express
written consent of the Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for
applications ifl medicine, aerospace, nuclear energy, orotherfie[ds, in which its failure to function or perform may
reasonably be expected to result in IOSS of life or in significant injury or damage to person or property.
(b) A critical component is one whose failure to function or perform May reasonably be expected to result, whether
directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must
therefore meet very high standards of performance and reliability.
. It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes Ofl or otherwise plaCeS the
product with a third party to notify that paw in advanCe of the above content and conditions, and the buyer or distributor
a!greeS tO aSSUflle afly and all responsibility and liability for and hold AKM harrn]ess from any and all CIaiMS ariSiflg frOlll
the use of said product in the absence of such notification.