[AKD4753-A] AKD4753-A AK4753 Evaluation Board Rev.2 GENERAL DESCRIPTION The AKD4753-A is an evaluation board for AK4753, 2-in, 4-out CODEC with DSP Functions. The AKD4753-A has the Digital Audio I/F and can achieve the interface with digital audio systems via optical connector. ■ Ordering guide AKD4753-A --- Evaluation Board for AK4753 (Control software and USB cable are packed with this.) FUNCTION • RCA connectors for analog audio input/output • Optical connector for digital audio input • On-board digital audio interface (AK4118A) • Potentiometers for Volume and Bass gain control • USB connector for serial control interface •1k bits EEPROM D3.3V DVDD AVDD Regulator 3.3V +5V GND Regulator USB 3.3V EEPROM USB PIC4550 AINL AINR PORT4 LOUT1 AK4753 Opt In AK4118A (DIR) ROUT1 ROUT2 PORT1 LOUT1 SAIN1 Volume SAIN2 Bass Gain Potentiometer 10 Pin Header DSP I2C PORT3 PORT2 10 Pin Header Figure 1. AKD4753-A Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. KM103902 2011/01 -1- [AKD4753-A] Evaluation Board Manual ■ Operation sequence 1) Set up the power supply lines Name of jack +5V Color of jack Red Used for Open / Connect Regulator T2: AVDD, DVDD of AK4753, Digital Logic Should be always connected When default setting. AVDD Red AVDD of AK4753 DVDD Red DVDD of AK4753 D3.3V Red Digital Logic AGND Black Analog Ground Should be always connected when AVDD of AK4753 is not supplied from regulator T2. In this case “JP13” is set to “Open”. Should be always connected when DVDD of AK4753 is not supplied from regulator T2. In this case “JP14” is set to “Open”. Should be always connected when Digital Logic is not supplied from regulator T2. In this case “JP15” is set to “Open.” Should be always connected. DGND Black Digital Ground Should be always connected. Default Setting +5V Open Open Open GND GND Table 1. Set up the power supply lines Each supply line should be distributed from the power supply unit. 2) Setup the evaluation mode, jumper pins (2-1) External Slave Mode (a) Evaluation of using DIR of AK4118A <default> (b) All interface signals including master clock are fed externally (2-2) External Master Mode (a) Evaluation of using DIR of AK4118A (2-3) PLL Slave Mode (a) Evaluation of using DIR AK4118A (b) All interface signals including master clock are fed externally (2-4) PLL Master Mode (a) All interface signals including master clock are fed externally 3) Power on The AK4118A should be reset once bringing S1 (AK4118-PDN) “L” upon power-up. The AK4753 should be reset once bringing S2 (AK4753-PDN) “L” upon power-up. KM103902 2011/01 -2- [AKD4753-A] ■ Evaluation mode 1) External Slave Mode (a) Evaluation of D/A using DIR of AK4118A. <default> In case of AK4753 evaluation using AK4118A, it is necessary to correspond to audio interface format for AK4753 and AK4118A.Please use AK4118A in the master mode. PORT1(RX) is used. Nothing should be connected to PORT3(DSP) and J7(MCKI). XTL EXT GND JP4 AK4753-BICK DIR EXT JP5 AK4753-SDATA DIR EXT JP6 AK4753-LRCK DIR JP7 AK4753-MCLK MCKI DIR EXT JP3 EXT Figure 2. Setting of D/A using DIR of AK4118A (b) All interface signals including master clock are fed externally. PORT3(DSP) is used. Nothing should be connected to PORT1(RX) and J7(MCKI). JP4 AK4753-BICK XTL EXT GND DIR EXT JP5 AK4753-SDATA DIR EXT SLAVE DIR JP7 AK4753-MCLK EXT JP18 MCLK_SEL JP17 MODE_SEL MASTER JP6 AK4753-LRCK MCKI DIR EXT JP3 MUTEN MCLK Figure 3. Setting of all interface signals including master clock are fed externally KM103902 2011/01 -3- [AKD4753-A] 2) External Master Mode (a) Evaluation of D/A using DIR of AK4118A. In case of AK4753 evaluation using AK4118A, it is necessary to correspond to audio interface format for AK4753 and AK4118A.Please use AK4118A in the slave mode. PORT1(RX) is used. Nothing should be connected to PORT3(DSP) and J7(MCKI). XTL EXT GND JP4 AK4753-BICK DIR EXT JP5 AK4753-SDATA DIR EXT JP6 AK4753-LRCK DIR JP7 AK4753-MCLK MCKI DIR EXT JP3 EXT Figure 4. Setting of D/A using DIR of AK4118A 3) PLL Slave Mode (a) Evaluation of D/A using DIR of AK4118A. In case of AK4753 evaluation using AK4118A, it is necessary to correspond to audio interface format for AK4753 and AK4118A.Please use AK4118A in the master mode. PORT1(RX) is used. Nothing should be connected to PORT3(DSP) and J7(MCKI). XTL EXT GND JP4 AK4753-BICK DIR EXT JP5 AK4753-SDATA DIR EXT JP6 AK4753-LRCK DIR JP7 AK4753-MCLK MCKI DIR EXT JP3 EXT Figure 5. Setting of D/A using DIR of AK4118A (b) All interface signals including master clock are fed externally. PORT3(DSP) is used. Nothing should be connected to PORT1(RX) and J7(MCKI). JP4 AK4753-BICK XTL EXT GND DIR EXT JP5 AK4753-SDATA DIR EXT SLAVE DIR JP7 AK4753-MCLK EXT JP18 MCLK_SEL JP17 MODE_SEL MASTER JP6 AK4753-LRCK MCKI DIR EXT JP3 MUTEN MCLK Figure 6. Setting of all interface signals including master clock are fed externally KM103902 2011/01 -4- [AKD4753-A] 4) PLL Master Mode (a) All interface signals including master clock are fed externally. (a-1) Setup the MCKI. X1(X’Tal) or J7(MCKI) are used. Nothing should be connected to PORT1(RX). (a) When using X1(X’Tal) JP7 AK4753-MCLK JP3 JP7 AK4753-MCLK XTL EXT GND XTL EXT GND MCKI DIR EXT MCKI DIR EXT JP3 (b) When using J7(MCKI) Figure 7. Setup the MCKI (a-2) Other Setting (BICK, LRCK and SDATA). PORT3(DSP) is used. Nothing should be connected to PORT1(RX). JP4 AK4753-BICK DIR EXT JP5 AK4753-SDATA DIR EXT JP17 MODE_SEL MASTER SLAVE JP6 AK4753-LRCK DIR EXT JP18 MCLK_SEL MUTEN MCLK Figure 8. Other Setting (BICK, LRCK and SDATA) KM103902 2011/01 -5- [AKD4753-A] ■ EEP-ROM operation setting JP8 JP10 JP9 WP PC-SCL PC-SDA 1) When you write the setting from Control Soft to EEPROM. At this time, please fix the EXTEE switch (See Table 5) to "L". Figure 9. Setting of EEP-ROM operation1 JP9 PC-SCL JP8 WP PC-SDA JP10 2) When you load the setting from EEPROM to AK4753. Please change the EXTEE switch (See Table 5) from "L" to "H" after setting JP8, JP9 and JP10. Figure 10. Setting of EEP-ROM operation2 KM103902 2011/01 -6- [AKD4753-A] ■ Jumper pins setting [JP1 (SAIN1)]: The selection of connection to SAIN1 pin. SHORT : Connection. (Default) OPEN : Unconnection. [JP2 (SAIN2)]: The selection of connection to SAIN2 pin. SHORT : Connection. (Default) OPEN : Unconnection. [JP8 (PC-SCL)]: The selection of SCL signal. SHORT : When you write the setting in EEPROM. OPEN : When you load the setting from EEPROM. (Default) [JP9 (WP)]: The selection of Write Protect setting of EEPROM. SHORT : Write protect is Disable. OPEN : Write protect is Enable. (Default) [JP10 (PC-SDA)]: The selection of SDA signal. SHORT : When you write the setting in EEPROM. OPEN : When you load the setting from EEPROM. (Default) [JP11]: Not to use. [JP12 (GND)]: Analog ground and Digital ground. SHORT : Common. (Default) OPEN : Separated. [JP16 (TEST)]: The selection of connection to TEST pin. SHORT : Connect to VDD. OPEN : Connect to GND. (Default) ■ Potentiometer setting [R5]: Volume control Upper - side: 0dB Lower - side: Mute (-∞) [R7]: Bass control Upper - side: +12dB Lower - side: -12dB R5 SAIN1 R7 SAIN2 Figure 11. Potentiometers KM103902 2011/01 -7- [AKD4753-A] ■ DIR SW Setting Upper-side is “ON(H)” and lower-side is “OFF(L)”. [S3] (SW DIP-4): Mode setting for AK4118A. No. Name ON (“H”) 1 2 3 4 OCKS0 OCKS1 DIF0 DIF1 OFF (“L”) AK4118A Master Clock Setting See Table 3 AK4118A Audio Interface Format Setting See Table 4 Default OFF OFF ON OFF Table 2. Mode Setting for AK4118A OCKS1 OCKS0 MCKO1 L H H L L H 256fs 512fs Not to use Default Table 3. Setting for AK4118A Master Clock Setting DIF2 Fixed ”H” DIF1 L L H H DIF0 L H L H SDTO 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S LRCK H/L O L/H O H/L I L/H I BICK 64fs 64fs 64-128fs 64-128fs O O I I Default Table 4. Setting for AK4118A Audio Interface Format Setting [S4] (SW DIP-2): Mode setting for AK4753. No. Name ON (“H”) OFF (“L”) Default 1 2 EXTEE BYPASS EEP-ROM Download Mode DSP Bypass Mode Serial Control Mode Normal Operation OFF OFF Table 5. Mode Setting for AK4753 KM103902 2011/01 -8- [AKD4753-A] ■ Function of the Toggle SW Upper-side is “H” and lower-side is “L”. [S1] (AK4118-PDN): Resets the AK4118A. Keep “H” during normal operation. The AK4118A should be resets once bringing “L” upon power-up. [S2] (AK4753-PDN): Resets the AK4753. Keep “H” during normal operation. The AK4753 should be resets once bringing “L” upon power-up. ■ Indication for LED [LED1] (STO): Monitor STO pin of the AK4753. LED turns on when Read error of EEPROM has occurred to AK4753. [LED2] (EFR): Monitor INT0 pin of the AK4118A. LED turns on when some error has occurred to AK4118A. ■ Control Port It is possible to control AKD4753-A via general USB port. Connect cable with the USB port on board and PC. Control software is packed with this board. The software operation sequence is included in the evaluation board manual. KM103902 2011/01 -9- [AKD4753-A] ■ Analog Input / Output Circuits 1) Analog Inputs (a) AINL, AINR J1 AINR C2 + 2 3 4 5 1 AINR 1u R1 (open) J3 AINL C4 + 2 3 4 5 1 AINL 1u R3 (open) Figure 12. Circuit diagram of AINL and AINR (b) SAIN1, SAIN2 SAIN1 R5 AVDD 10k C9 (OPEN) SAIN2 R7 10k C12 (OPEN) Figure 13. Circuit diagram of SAIN1 and SAIN2 KM103902 2011/01 - 10 - [AKD4753-A] 2) Analog Outputs (a) STEREO Mode (Full-differential) LOUT+ TEST1 LOUT+ C1 + J2 LOUT1 ROUT- 10u C3 (OPEN) LOUT- J5 ROUT2 10u R2 C8 (OPEN) (open) TEST2 LOUT- C5 + J4 ROUT1 ROUT+ 10u C6 (OPEN) TEST3 ROUT- C7 + R6 (open) TEST4 ROUT+ C10 + J6 LOUT2 10u R4 C11 (OPEN) (open) R8 (open) Figure 14. Circuit diagram of STEREO Mode (b) 2.1-channel Mode LOUT1 TEST1 LOUT+ C1 + J2 LOUT1 SW- 10u C3 (OPEN) ROUT1 10u C8 (OPEN) R2 (open) TEST2 LOUT- C5 + J4 ROUT1 SW+ 10u C6 (OPEN) (open) J5 ROUT2 R6 (open) TEST4 ROUT+ C10 + 10u C11 (OPEN) R4 TEST3 ROUT- C7 + J6 LOUT2 R8 (open) Figure 15. Circuit diagram of 2.1-channel Mode (c) 4-channel Mode (Single-ended) LOUT1 TEST1 LOUT+ C1 + J2 LOUT1 ROUT2 10u C3 (OPEN) ROUT1 J5 ROUT2 10u R2 C8 (OPEN) (open) TEST2 LOUT- C5 + J4 ROUT1 LOUT2 10u C6 (OPEN) TEST3 ROUT- C7 + R6 (open) TEST4 ROUT+ C10 + J6 LOUT2 10u R4 C11 (OPEN) (open) R8 (open) Figure 16. Circuit diagram of 4-channel Mode KM103902 2011/01 - 11 - [AKD4753-A] Control Soft Manual ■ Evaluation Board and Control Soft Settings 1. Set an evaluation board properly. 2. Connect Evaluation board to PC with USB cable. USB control is recognized as HID (Human Interface Device) on the PC. When it can not be recognized correctly please Connect Evaluation board to PC with USB cable. 3. Proceed evaluation by following the process below. ■Operation Screen 1. Start up the control program following the process above. 2. After the evaluation board’s power is supplied, the AK4753 must be reset once bring S2 (AK4753-PDN) “L” to “H”. 3. The operation screen is shown below. Figure 17. Window of Control Soft KM103902 2011/01 - 12 - [AKD4753-A] ■Operation Overview Function, register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs. Buttons which are frequently used such as register initializing button “Write Default”, are located outside of the switching tab window. Refer to the “■Dialog Boxes” for details of each dialog box setting. 1. [Port Reset]: For when connecting to USB I/F board (AKDUSBIF-B) Click this button after the control soft starts up when connecting USB I/F board (AKDUSBIF-B). 2. [Write Default]: Register Initializing When the device is reset by a hardware reset, use this button to initialize the registers. 3. [All Write]: Executing write commands for all registers displayed. 4. [All Read]: Executing read commands for all registers displayed. 5. [Save]: Saving current register settings to a file. 6. [Load]: Executing data write from a saved file. 7. [All Reg Write]: “All Reg Write” dialog box is popped up. 8. [Data R/W]: “Data R/W” dialog box is popped up. 9. [Sequence]: “Sequence” dialog box is popped up. 10. [Sequence(File)]: “Sequence(File)” dialog box is popped up. 11. [EEPROM Write]: Executing EEPROM write. 12. [Read]: Reading current register settings and display on to the Register area on the right of the main window. This is different from [All Read] button, it does not reflect to a register map, only displaying hexadecimal. KM103902 2011/01 - 13 - [AKD4753-A] ■ Tab Functions 1. [Function]: Function control This tab is for function control. Each operation is executed by the function buttons on the left side of the screen. Figure 18.Window of [Function] KM103902 2011/01 - 14 - [AKD4753-A] 1-1. [Mode Setting]: Power Management and Signal Path Setting When [Mode Setting] button is clicked, the window as shown in opens. This window is for Power Management and Signal Path Setting. Refer to the datasheet for register settings of the AK4753. Figure 19. Window of [Mode Setting] 1-2. [PLL Setting]: System Clock and Audio I/F Setting When [PLL Setting] button is clicked, the window as shown in opens. This window is for System Clock and Audio I/F Setting. Refer to the datasheet for register settings of the AK4753. Figure 20. Window of [PLL Setting] KM103902 2011/01 - 15 - [AKD4753-A] 1-3. [Volume Setting]: Volume Setting When [Volume Setting] button is clicked, the window as shown in opens. This window is for Volume Setting. Refer to the datasheet for register settings of the AK4753. Figure 21. Window of [Volume Setting] 1-3-1. Register map The volume can be controlled by slide bars. A register writing is made on every slide bar move. After the volume slide is moved, it is reflected on to the register map and data writing dialog box. 1-3-2. Volume Control by Slide bar Slide bar is moved to the selected value Figure 22. Volume Control by Slide bar The volume can also be changed by writing a value in a dialog box. The slide bar is moved to the value that written in the dialog box. Use the mouse or arrow keys on the keyboard for small adjustments. KM103902 2011/01 - 16 - [AKD4753-A] 1-4. [Digital Filter Setting]: Filter Setting A calculation of a coefficient of Digital Programmable Filters such as HPF / LPF and EQ filters, a register writing and a frequency response checking of HPF / LPF and EQ filters can be made. When [Digital Filter Setting] button is clicked, the window as shown in opens. Refer to the datasheet for register settings of the AK4753. Figure 23. Window of [Digital Filter Setting] KM103902 2011/01 - 17 - [AKD4753-A] 1-4-1. Parameter Setting (1) Please set a parameter of each Filter. Parameter Function Sampling Rate HPF Cut Off Frequency Setting Range Sampling frequency (fs) 7350Hz ≤ fs ≤ 48000Hz High pass filter cut off frequency 1.042x10-3 ≤ fc/fs ≤ 0.24 LPF Cut Off Frequency Low pass filter cut off frequency 5.208x10-3 ≤ fc/fs ≤ 0.24 5 Band Equalizer EQ1-5 Center Frequency EQ1-5 Band Width EQ1-5 Gain EQ1-5 Center Frequency EQ1-5 Band Width EQ1-5 Gain (Note 1) (Note 2) 3.125x10-3 ≤ fon/fs < 0.4969 fbn/fs ≤ 0.25 -1≤ Gain < 3 Table 6. Parameter Setting Note 1. A gain difference is a bandwidth of 3dB from center frequency. Note 2. When a gain is smaller than 0 , EQ becomes a notch filter. (2) “HPF LPF Enable” , “HPF” ,”LPF” , “EQ1”, “EQ2”, “EQ3”, “EQ4”, “EQ5” Please set ON/OFF of Filter with a check button. When checked it, Filter becomes ON. When “Notch Filter Auto Correction” is checked, perform automatic correction of the center frequency of the notch filter is executed. Figure 24. Filter ON/OFF setting button KM103902 2011/01 - 18 - [AKD4753-A] 1-4-2. A calculation of a register A register set value is displayed when push a [Register Setting] button. When a value out of a setting range is set, error message is displayed, and a calculation of register setting is not carried out. Figure 25. A register setting calculation result Followings are the cases when a register set value is updated. (1) When [Register Setting] button was pushed. (2) When [F Response] button was pushed. (3) When [UpDate] button was pushed on a frequency characteristic indication window. (4) When set ON/OFF of a check button “HPF LPF Enable”, “HPF” ,”LPF”,“EQ1”, “EQ2”, “EQ3”, “EQ4”, “EQ5” KM103902 2011/01 - 19 - [AKD4753-A] 1-4-3. Indication of a frequency characteristic A frequency characteristic is displayed when push a [F Response] button. Then, a register set point is also updated. Change "Frequency Range", and indication of a frequency characteristic is updated when push a [UpDate] button. Figure 26. A frequency characteristic indication result Followings are the cases when a register set value is updated. (1) When [Register Setting] button was pushed. (2) When [F Response] button was pushed. (3) When [UpDate] button was pushed on a frequency characteristic indication window. (4) When set ON/OFF of a check button “HPF LPF Enable”, “HPF” ,”LPF”,“EQ1”, “EQ2”, “EQ3”, “EQ4”, “EQ5” KM103902 2011/01 - 20 - [AKD4753-A] 1-4-4. Filter Setting The filter setting can be executed by dragging the number to 1-5 in the mouse. Band Width can be adjusted in the operation of Center Frequency and Gain right-clicking in the operation of the left-click. After it moves, a set value is reflected. It moves by the left-click. Figure 27. Filter Setting(Left-clicking operation) Band Width is revokable when sideways moving to right-click. Figure 28. Filter Setting(Right-clicking operation) KM103902 2011/01 - 21 - [AKD4753-A] 1-5. [Limiter Setting]: Limiter Setting When [Limiter Setting] button is clicked, the window as shown in opens. This window is for Limiter Setting. Refer to the datasheet for register settings of the AK4753. Figure 29. Window of [Limiter Setting] KM103902 2011/01 - 22 - [AKD4753-A] 2. [REG]: Register Map This tab is for a register writing and reading. Each bit on the register map is a push-button switch. Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red). Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray) Grayout registers are Read Only registers. They can not be controlled. The registers which is not defined in the datasheet are indicated as “---”. Figure 30. Window of [REG] KM103902 2011/01 - 23 - [AKD4753-A] 2-1. [Write]: Data Writing Dialog It is for when changing two or more bits on the same address at the same time. Click [Write] button located on the right of the each corresponded address for a pop-up dialog box. When checking the checkbox, the register will be “H” or “1”, when not checking the register will be “L” or ”0”. Click [OK] to write setting value to the registers, or click [Cancel] to cancel this setting. Figure 31. Window of [Register Set] 2-2. [Read]: Data Read Click [Read] button located on the right of the each corresponded address to execute register reading. After register reading, the display will be updated regarding to the register status. Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red). Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray) Please be aware that button statuses will be changed by Read command. KM103902 2011/01 - 24 - [AKD4753-A] 3. [Tool]: Testing Tools This tab screen is for evaluation testing tool. Click buttons for each testing tool. Figure 32. Window of [Tool] KM103902 2011/01 - 25 - [AKD4753-A] 3-1. [Repeat Test]: Repeat Test Dialog Click [Repeat Test] button to open repeat test setting dialog box. Figure 33. Window of [Repeat Test] 3-2. [Loop Setting]: Loop Setting Dialog Click [Loop Setting] button to open loop setting dialog box. Figure 34. Window of [Loop] KM103902 2011/01 - 26 - [AKD4753-A] ■Dialog Boxes 1. [All Reg Write]: ALL Register Write Click [All Reg Write] button in the main window to open register setting files. Register setting files saved by [SAVE] button can be applied. Figure 35. Window of [All Reg Write] [Open (left)] [Write] [Write All] [Help] [Save] [Open (right)] [Close] : Selecting a register setting file (*.akr). : Executing register writing. : Executing all register writings. Writings are executed in descending order. : Help window is popped up. : Saving the register setting file assignment. The file name is “*.mar”. : Opening a saved register setting file assignment “*. mar”. : Closing the dialog box and finish the process. *Operating Suggestions (1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be stored in the same folder. (2) When register settings are changed by [Save] button in the main window, re-read the file to reflect new register settings. KM103902 2011/01 - 27 - [AKD4753-A] 2. [Data R/W]: Data Read/Write Click the [Data R/W] button in the main window for data read/write dialog box. Data write is available to specified address. Figure 36. Window of [Data R/W] Address Box Data Box Mask Box [Write] [Close] : Input data address in hexadecimal numbers for data writing. : Input data in hexadecimal numbers. : Input mask data in hexadecimal numbers. This is “AND” processed input data. : Writing to the address specified by “Address” box. : Closing the dialog box and finish the process. Data writing can be cancelled by this button instead of [Write] button. *The register map will be updated after executing [Write] or [Read] commands. KM103902 2011/01 - 28 - [AKD4753-A] 3. [Sequence]: Sequence Click [Sequence] button to open register sequence setting dialog box. Register sequence can be set in this dialog box. Figure 37. Window of [Sequence] 3-1. Sequence Setting Set register sequence by following process bellow. (1)Select a command Use [Select] pull-down box to choose commands. Corresponding boxes will be valid. < Select Pull-down menu > · No_use · Register · Reg(Mask) · Interval · Stop · End : Not using this address : Register writing : Register writing (Masked) : Taking an interval : Pausing the sequence : Finishing the sequence KM103902 2011/01 - 29 - [AKD4753-A] (2)Input sequence [Address] : Data address [Data] : Writing data [Mask] : Mask [Data] box data is ANDed with [Mask] box data. This is the actual writing data. When Mask = 0x00, current setting is hold. When Mask = 0xFF, the 8bit data which is set in the [Data] box is written. When Mask =0x0F, lower 4bit data which is set in the [Data] box is written. Upper 4bit is hold to current setting. [Interval] : Interval time Valid boxes for each process command are shown bellow. · No use · Register · Reg(Mask) · Interval · Stop · End : None : [Address], [Data], [Interval] : [Address], [Data], [Mask], [Interval] : [Interval] : None : None 3-2. Control Buttons The function of Control Button is shown bellow. [Start] [Help] [Save] [Open] [Close] : Executing the sequence : Opening a help window : Saving sequence settings as a file. The file name is “*.aks”. : Opening a sequence setting file “*.aks”. : Closing the dialog box and finish the process. 3-3. Stop of the sequence When “Stop” is selected in the sequence, processing is paused and it starts again when [Start] button is clicked. Restarting step number is shown in the “Start Step” box. When finishing the process until the end of sequence, “Start Step” will return to “1”. The sequence can be started from any step by writing the step number to the “Start Step” box. Write “1” to the “Start Step” box and click [Start] button, when restarting the process from the beginning. KM103902 2011/01 - 30 - [AKD4753-A] 4. [Sequence(File)] : Sequence(File) Click [Sequence(File)] button to open sequence setting file dialog box. Those files saved in the “Sequence setting dialog” can be applied in this dialog. Figure 38. Window of [Sequence(File)] [Open (left)] [Start] [Start All] [Help] [Save] [Open(right)] [Close] : Opening a sequence setting file (*.aks). : Executing the sequence setting. : Executing all sequence settings. Sequences are executed in descending order. : Pop up the help window. : Saving sequence setting file assignment. The file name is “*.mas”. : Opening a saved sequence setting file assignment “*. mas”. : Closing the dialog box and finish the process. *Operating Suggestions (1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mas” should be stored in the same folder. (2) When “Stop” is selected in the sequence the process will be paused and a pop-up message will appear. Click “OK” to continue the process. Figure 39. Window of [Sequence Pause] KM103902 2011/01 - 31 - [AKD4753-A] 5. [EEPROM] : Write Press the [EEPROM Write] button. Register setting wrings to EEPROM. The following messages are displayed according to the result of processing. ・Writing failure Figure 40. Window of [Writing failure] ・Writing success Figure 41. Window of [Writing success] KM103902 2011/01 - 32 - [AKD4753-A] Measurement Result [Measurement condition] • Measurement Unit • MCLK • BICK • fs • Power Supply • Band Width • Measurement Mode • Temperature : Audio Precession System Two Cascade : 11.2896MHz (DAC) 12.288MHz (ADC to DAC) : 64fs : 44.1kHz : AVDD=DVDD=3.3V : 22Hz ~ 22kHz : External Slave Mode (DAC) External Slave Mode (ADC to DAC) : Room Temperature [Measurement Result] 1. DAC a). Single-ended, LOUT1/ROUT1, LOUT2/ROUT2 RL=Open Parameter S/(N+D) (0dBFS Input) D-Range (-60dB Input, A-weighted) S/N (No Signal, A-weighted) Output Voltage Lch1 Result / Rch1 Lch2 Result / Rch2 Unit 88.7 / 88.1 88.3 / 88.1 dB 99.2 / 98.7 99.2 / 98.3 dB 99.2 / 98.7 99.2 / 98.5 dB 2.40 / 2.40 2.40 / 2.40 Vpp Lch Result / b). Differential, LOUT/ROUT, RL=Open Parameter Rch Unit S/(N+D) (0dBFS Input) D-Range (-60dB Input, A-weighted) S/N (No Signal, A-weighted) 87.5 / 87.8 dB 102.8 / 103.3 dB 103.1 / 103.3 dB Output Voltage ±2.40 / ±2.40 Vpp KM103902 2011/01 - 33 - [AKD4753-A] 2. ADC to DAC a). Single-ended, LOUT1/ROUT1, LOUT2/ROUT2 RL=Open Parameter S/(N+D) (-1dBFS Input) D-Range (-60dB Input, A-weighted) S/N (No Signal, A-weighted) Lch1 Result / Rch1 Lch2 Result / Rch2 Unit 86.4 / 86.3 86.5 / 86.3 dB 95.1 / 95.0 95.1 / 95.0 dB 95.1 / 95.0 95.1 / 95.0 dB Lch Result / b). Differential, LOUT/ROUT, RL= Open Parameter S/(N+D) (-1dBFS Input) D-Range (-60dB Input, A-weighted) S/N (No Signal, A-weighted) KM103902 Rch Unit 85.8 / 85.7 dB 96.5 / 96.5 dB 96.5 / 96.5 dB 2011/01 - 34 - [AKD4753-A] PLOT DATA 1-a). DAC Single-ended [LOUT1/ROUT1 pins] AK4753 FFT [LOUT1/ROUT1] fs=44.1kHz, fin=1kHz 0dBFS Input, External Slave Mode +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Figure 42. FFT(0dBFS Input) AK4753 FFT [LOUT1/ROUT1] fs=44.1kHz, fin=1kHz, -60dBFS Input, External Slave Mode +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k Hz Figure 43. FFT(-60dB Input) KM103902 2011/01 - 35 - [AKD4753-A] AK4753 FFT [LOUT1/ROUT1] fs=44.1kHz, fin=1kHz, No Signal, External Slave Mode +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 44. FFT(No Signal) AK4753 THD+N vs. Input Level [LOUT1/ROUT1] fs=44.1kHz, fin=1kHz, External Slave Mode -50 -55 -60 -65 -70 -75 d B r -80 A -90 -85 -95 -100 -105 -110 -115 -120 -140 -120 -100 -80 -60 -40 -20 +0 dBFS Figure 45. THD+N vs. Input Level KM103902 2011/01 - 36 - [AKD4753-A] AK4753 THD+N vs. Input Frequency [LOUT1/ROUT1] fs=44.1kHz, 0dBFS Input, External Slave Mode -50 -55 -60 -65 -70 -75 d B r -80 A -90 -85 -95 -100 -105 -110 -115 -120 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 46. THD+N vs. Input Frequency AK4753 Linearity [LOUT1/ROUT1] fs=44.1kHz, fin=1kHz, EXT Slave Mode +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 47. Linearity KM103902 2011/01 - 37 - [AKD4753-A] AK4753 Frequency Response [LOUT1/ROUT1] fs=44.1kHz, 0dBFS Input, External Slave Mode +1 +0.8 +0.6 +0.4 +0.2 d B r +0 A -0.2 -0.4 -0.6 -0.8 -1 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 48. Frequency Response AK4753 Crosstalk [LOUT1/ROUT1] fs=44.1kHz, 0dBFS Input, External Slave Mode +0 T TT T T -10 -20 -30 -40 -50 -60 d B -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k Hz Figure 49. Crosstalk KM103902 2011/01 - 38 - [AKD4753-A] PLOT DATA 1-b). DAC Differential [LOUT/ROUT pins] AK4753 FFT [LOUT+-/ROUT+-] fs=44.1kHz, fin=1kHz, 0dBFS Input, External Slave Mode +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Figure 50. FFT(0dBFS Input) AK4753 FFT [LOUT+-/ROUT+-] fs=44.1kHz, fin=1kHz, -60dBFS Input, External Slave Mode +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k Hz Figure 51. FFT(-60dB Input) KM103902 2011/01 - 39 - [AKD4753-A] AK4753 FFT [LOUT+-/ROUT+-] fs=44.1kHz, fin=1kHz, No Signal, External Slave Mode +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 52. FFT(No Signal) AK4753 THD+N vs. Input Level [LOUT+-/ROUT+-] fs=44.1kHz, fin=1kHz, External Slave Mode -50 -55 -60 -65 -70 -75 d B r -80 A -90 -85 -95 -100 -105 -110 -115 -120 -140 -120 -100 -80 -60 -40 -20 +0 dBFS Figure 53. THD+N vs. Input Level KM103902 2011/01 - 40 - [AKD4753-A] AK4753 THD+N vs. Input Frequency [LOUT+-/ROUT+-] fs=44.1kHz, 0dBFS Input, External Slave Mode -50 -55 -60 -65 -70 -75 d B r -80 A -90 -85 -95 -100 -105 -110 -115 -120 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 54. THD+N vs. Input Frequency AK4753 Linearity [LOUT+-/ROUT+-] fs=44.1kHz, fin=1kHz, EXT Slave Mode +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 55. Linearity KM103902 2011/01 - 41 - [AKD4753-A] AK4753 Frequency Response [LOUT+-/ROUT+-] fs=44.1kHz, 0dBFS Input, External Slave Mode +1 +0.8 +0.6 +0.4 +0.2 d B r +0 A -0.2 -0.4 -0.6 -0.8 -1 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 56. Frequency Response AK4753 Crosstalk [LOUT+-/ROUT+-] fs=44.1kHz, 0dBFS Input, External Slave Mode +0 -10 -20 -30 -40 -50 -60 d B -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k Hz Figure 57. Crosstalk KM103902 2011/01 - 42 - [AKD4753-A] PLOT DATA 2-a). ADC to DAC Single-ended [LOUT1/ROUT1 pins] AK4753 FFT [LOUT1/ROUT1] fs=44.1kHz, fin=1kHz, -1dBFS Input +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 58. FFT(-1dBFS Input) AK4753 FFT [LOUT1/ROUT1] fs=44.1kHz, fin=1kHz, -60dBFS Input +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k Hz Figure 59. FFT(-60dBFS Input) KM103902 2011/01 - 43 - [AKD4753-A] AK4753 FFT [LOUT1/ROUT1] fs=44.1kHz, fin=1kHz, No Signal +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 60. FFT(No Signal) AK4753 THD+N vs. Input Level [LOUT1/ROUT1] fs=44.1kHz, fin=1kHz -50 -55 -60 -65 -70 -75 d B r -80 A -90 -85 -95 -100 -105 -110 -115 -120 -140 -120 -100 -80 -60 -40 -20 dBr Figure 61. THD+N vs. Input Level KM103902 2011/01 - 44 - [AKD4753-A] AK4753 THD+N vs. Input Frequency [LOUT1/ROUT1] fs=44.1kHz, -1dBFS Input -50 -55 -60 -65 -70 -75 d B r -80 A -90 -85 -95 -100 -105 -110 -115 -120 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 62. THD+N vs. Input Frequency AK4753 Linearity [LOUT1/ROUT1] fs=44.1kHz, fin=1kHz +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr Figure 63. Linearity KM103902 2011/01 - 45 - [AKD4753-A] AK4753 FrequencyResponse [LOUT1/ROUT1] fs=44.1kHz, -1dBFS Input +0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 d B r -1.4 -1.6 A -1.8 -2 -2.2 -2.4 -2.6 -2.8 -3 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 64. Frequency Response AK4753 Crosstalk [LOUT1/ROUT1] fs=44.1kHz, -1dBFS Input +0 TT TTT T -10 -20 -30 -40 -50 -60 d B -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k Hz Figure 65. Crosstalk KM103902 2011/01 - 46 - [AKD4753-A] PLOT DATA 2-b). ADC to DAC Differential [LOUT/ROUT pins] AK4753 FFT [LOUT+-/ROUT+-] fs=44.1kHz, fin=1kHz, -1dBFS Input +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 66. FFT(-1dBFS Input) AK4753 FFT [LOUT+-/ROUT+-] fs=44.1kHz, fin=1kHz, -60dBFS Input +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k Hz Figure 67. FFT(-60dBFS Input) KM103902 2011/01 - 47 - [AKD4753-A] AK4753 FFT [LOUT+-/ROUT+-] fs=44.1kHz, fin=1kHz, No Signal +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 68. FFT(No Signal) AK4753 THD+N vs. Input Level [LOUT+-/ROUT+-] fs=44.1kHz, fin=1kHz -50 -55 -60 -65 -70 -75 d B r -80 A -90 -85 -95 -100 -105 -110 -115 -120 -140 -120 -100 -80 -60 -40 -20 dBr Figure 69. THD+N vs. Input Level KM103902 2011/01 - 48 - [AKD4753-A] AK4753 THD+N vs. Input Frequency [LOUT+-/ROUT+-] fs=44.1kHz, -1dBFS Input -50 -55 -60 -65 -70 -75 d B r -80 A -90 -85 -95 -100 -105 -110 -115 -120 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 70. THD+N vs. Input Frequency AK4753 Linearity [LOUT+-/ROUT+-] fs=44.1kHz, fin=1kHz +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr Figure 71. Linearity KM103902 2011/01 - 49 - [AKD4753-A] AK4753 FrequencyResponse [LOUT+-/ROUT+-] fs=44.1kHz, -1dBFS Input +0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 d B r -1.4 -1.6 A -1.8 -2 -2.2 -2.4 -2.6 -2.8 -3 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 72. Frequency Response AK4753 Crosstalk [LOUT+-/ROUT+-] fs=44.1kHz, -1dBFS Input +0 T TT T TT T -10 -20 -30 -40 -50 -60 d B -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k Hz Figure 73. Crosstalk KM103902 2011/01 - 50 - [AKD4753-A] Revision History Date (YY/MM/DD) 10/09/17 10/09/30 Manual Revision KM103900 KM103901 Board Revision 0 1 Reason Contents First Edition Description Change Measurement results ware changed. Board Modification Schematic circuit diagram was changed. 11/01/28 KM103902 2 Description Change Control soft manual was changed. Measurement results ware changed. Board Modification AK4753: Rev.A → Rev.B IMPORTANT NOTICE ! These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. ! Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. ! Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ! AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. ! It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. KM103902 2011/01 - 51 - 5 4 3 2 J1 + C2 1 J2 LOUT1 1 LOUT1 + 2 3 4 5 D LOUT+ TEST1 C1 AINR 1 2 3 4 5 AINR 10u R1 1u C3 (OPEN) (open) R2 (open) D VSS1 VSS1 LOUTTEST2 J3 AINL C4 C5 + + 2 3 4 5 1 AINL R3 1 ROUT1 1u 10u C6 (OPEN) (open) J4 ROUT1 2 3 4 5 R4 (open) C C VSS1 ROUTTEST3 VSS1 + C7 J5 ROUT2 1 ROUT2 2 3 4 5 SAIN1 10u R5 C8 (OPEN) AVDD 10k R6 (open) VSS1 C9 (OPEN) VSS1 B B + SAIN2 10u 10k C11 (OPEN) VSS1 J6 LOUT2 1 LOUT2 R7 C12 ROUT+ TEST4 C10 R8 2 3 4 5 (open) (OPEN) VSS1 A A Title AKD4753-A - 52 5 4 3 Size A Date: Document Number Rev 1 AIN / AOUT Wednesday, September 29, 2010 2 Sheet of 1 1 5 3 2 SAIN1 VSS2 1 SAIN2 4 AK4753-PDN 5 VSS1 VSS1 CN1 TEST5 PDN 12 SAIN2 TEST8 VSS1 13 D VSS1 VSS2 JP16 TEST R52 5 4 3 2 1 CD NC VSS VDD OUT TEST7 AVDD DVDD 14 15 17 18 19 16 TEST6 SAIN1 U2 S-80923CNMC 20 D 21 22 44pin_2 R10 C72 (open) EXTEE C16 (OPEN) 11 9 10 TEST12 AINR SAIN2 SAIN1 TEST 11 12 FLT 14 PDN 51 EXTEE R12 13 16 EESDA 24 15 EESDA TEST11 EESDA (OPEN) CN3 23 VSS2 C14 R11 10k VSS2 CN2 JP2 SAIN2 TEST10 TEST C71 (open) TEST9 FLT C15 4.7n JP1 SAIN1 10k C13 4.7n 100k TEST15 EESCL 51 17 EESCL AINL 8 TEST14 SDA 18 SDA VSS1 7 8 C17 0.1u R15 27 51 19 SCL MUTEN 20 28 29 R16 STO LOUT1 5 ROUT1 4 ROUT2 3 0 30 R18 51 22 R20 51 23 LRCK LOUT2 2 R22 51 24 BICK VCOM 1 SDTI TEST25 0 31 32 TEST27 TEST28 ROUT1 4 ROUT2 3 LOUT2 BYPASS TEST26 0 LOUT2 C22 (OPEN) C23 C24 0.1u 2.2u TEST29 VSS1 2 TEST30 VSS1 DVDD DVDD 32 NC 1 31 REG VSS2 30 XTO DVDD 29 28 44pin_3 27 NC B 26 25 VSS2 5 ROUT2 VCOM XTI/MCKI BICK 33 LOUT1 TEST24 C21 (OPEN) R21 LRCK AK4753-BICK 6 ROUT1 C20 (OPEN) R19 SDTI AK4753-LRCK AVDD TEST22 C19 (OPEN) R17 TEST23 AK4753-SDTI 7 LOUT1 0 AK4753 STO 6 VSS1 AVDD 10u TEST20 MUTEN TEST21 21 AVDD U1 TEST19 TEST18 C18 + 51 SCL STO C VSS1 R13 TEST17 MUTEN AINL TEST16 26 SCL AINR 9 AINL R14 25 SDA 10 TEST13 EESCL C VSS1 AINR B 44pin_1 XTL EXT GND C25 0.1u JP3 DVDD 2.2u + C27 X1 1 C26 2 TEST31 10u 12.288MHz C28 C29 10p 10p REG DVDD VSS2 TEST37 44 EXTEE TEST36 43 42 41 40 VSS2 TEST34 39 38 MCLK TEST33 37 36 35 VSS2 TEST32 34 BYPASS TEST35 EXTEE R23 0 CN4 44pin_4 A A EXTEE VSS2 BYPASS AK4753-MCLK VSS2 VSS2 Title AKD4753-A - 53 - Size C Date: 5 4 3 2 Document Number Rev 1 AK4753 Wednesday, September 29, 2010 1 Sheet 2 of 5 5 4 3 2 1 47u L1 2 D3.3V 1 DVDD PORT1 RX 3 GND OUT 2 1 4118-VCC U3 10u 0.1u TORX147 D3.3V + C31 C30 C32 + VCC C33 10u D3.3V 10k R27 470 R28 10k R29 470 1 2 3 4 5 6 7 0.1u DGND DGND R30 10k 51 + 2 10 8 6 4 2 37 38 INT1 39 R AVDD 41 R24 R25 2.2k 2.2k PC-SCL VCC 6A 6Y 5A 5Y 4A 4Y 14 13 12 11 10 9 8 SCL C34 SDA 0.1u PC-SDA D AK4753-PDN 74HC07 A1-10PA-2.54DSA 40 VSS3 1A 1Y 2A 2Y 3A 3Y GND PORT2 VCOM 42 RX0 NC 43 44 RX1 TEST1 46 RX2 VSS4 RX3 1 4118-VCC 45 C35 10u 48 R31 47 D R26 INT0 36 OCKS0/CSN/CAD0 35 AK4118-OCKS0 OCKS1/CCLK/SCL 34 AK4118-OCKS1 IPS0/RX4 NC EFR DGND 9 7 5 3 1 SCL SDA SDA(ACK) DGND uP-I/F D3.3V 3 AK4118-DIF0 DIF0/RX5 K D3.3V CM0/CDTO/CAD1 PDN 31 XTI 30 XTO 29 R32 D1 HSU119 DIF1/RX6 6 VSS1 7 DIF2/RX7 8 IPS1/IIC 10k AK4118-PDN A 33 32 LED1 LED2 STO U4 AK4118A 1 3 ATE1D-2M3 AK4118-PDN H S1 2 L AK4118-PDN EFR U5 1 2 3 4 5 6 7 C36 0.1u C DGND 9 P/SN DAUX 28 10 XTL0 MCKO2 27 XTL1 BICK 26 SDTO 25 51 D2 HSU119 A 0.1u C39 AK4753-SDTI 1 L ATE1D-2M3 AK4753-PDN R38 24 51 AK4753-LRCK DIR + R40 C C37 0.1u DGND 10k H S2 C38 0.1u DGND S3 JP7 R39 EXT DIR MCKI 4118-VCC D3.3V R34 1k EFR JP6 AK4753-LRCK EXT 10u C42 + 51 3 R37 DIR 0.1u C40 10u C41 R33 1k D3.3V STO JP5 AK4753-SDTI LRCK MCKO1 VSS2 22 23 DVDD VOUT/GP7 21 20 COUT/GP5 UOUT/GP6 19 18 TX1/GP3 TX0/GP2 BOUT/GP4 17 16 15 DGND 14 13 TVDD NC/GP1 VIN/GP0 14 13 12 11 10 9 8 R36 AK4753-BICK EXT 12 VCC 6A 6Y 5A 5Y 4A 4Y 74HC14 K R35 DIR 2 11 1A 1Y 2A 2Y 3A 3Y GND D3.3V JP4 AK4753-BICK EXT DGND K CM1/CDTI/SDA K 5 A TEST2 A 4 AK4118-DIF1 51 D3.3V 5.1 8 7 6 5 4118-VCC AK4753-MCLK AK4753-MCLK 1 OCKS0 OCKS1 DIF0 DIF1 AK4118-OCKS0 AK4118-OCKS1 AK4118-DIF0 AK4118-DIF1 RP1 SW DIP-4 H B 1 2 3 4 4 3 2 1 L J7 B MCKI 47k 2 3 4 5 DGND DGND D3.3V DGND R57 10k 10 8 6 4 2 9 7 5 3 1 U9 SDATA LRCK BICK MCLK PORT3 DGND A1-10PA-2.54DSA DSP D3.3V C68 0.1u 4 1A1 1B1 13 5 1A2 1B2 12 2 1DIR 1OE 15 6 2A1 2B1 11 STO 7 2A2 2B2 10 MUTEN 3 2DIR 2OE 14 1 VCCA VCCB 16 8 GND GND 9 D3.3V C67 0.1u 74AVC4T245 DGND A JP18 JP17 MCLK U10 4 1A1 1B1 13 5 1A2 1B2 12 2 1DIR 1OE 15 6 2A1 2B1 11 7 2A2 2B2 3 2DIR 2OE 14 SEL D3.3V C69 0.1u A 10 1 VCCA VCCB 16 8 GND GND 9 D3.3V C70 0.1u Title 74AVC4T245 DGND 5 4 - 54 3 Size A2 Date: 2 AKD4753-A Document Number Rev 1 DIR (AK4118) Wednesday, September 29, 2010 1 Sheet 3 of 5 5 4 3 2 1 S4 1 2 DVDD DVDD 4 3 EXTEE BYPASS SW DIP-2 H EEPROM R41 R42 R43 47k 2.2k 2.2k L R44 47k U6 D R45 47k D C66 0.1u 1 A0 VCC 8 2 A1 WP 7 3 A2 SCL 6 4 VSS SDA 5 24LC01B D3.3V DGND EESCL JP8 PC-SCL JP10 PC-SDA PC-SCL JP9 WP EESDA PC-SDA DGND C C + + USB-VDD C43 10u C44 10u DGND USB-RST 18 C47 0.1u VDD1 VSS1 29 6 VSS0 MCLR_N/Vpp/RE3 12 13 33 34 NC/ICCK/ICPGC NC/ICDT/ICPGD NC/ICRST_N/ICVpp NC/ICPORTS 30 31 OSC1/CLKI OSC2/CLKO/RA6 25 26 27 RE0/AN5/CK1SPP RE1/AN6/CK2SPP RE2/AN7/OESPP RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0/CSSPP RB3/AN9/CPP2/VPO RB2/AN8/INT2/VMO RB1/AN10/INT1/SCK/SCL RB0/AN12/INT0/FLT0/SDI/SDA DGND B 28 C46 0.1u VDD0 U7 R47 100k DGND C45 0.1u 7 R46 4.7k JP11 1 2 3 4 5 17 16 15 14 11 10 9 8 SILK-SCREEN 1: VDD 2: MCLR 3: PGD 4: PGC 5: GND HEADER 5 DGND B C48 22p C54 X2 20MHz 470n 37 PIC18F4550 TQFP 44-PIN PC-SCL PC-SDA 51 51 19 20 21 22 23 24 38 39 40 41 2 3 4 5 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2/UOE_N RC2/CCP1/P1A 32 35 36 RC4/D-/VM RC5/D+/VP RC6/TX/CK RC7/RX/DT/SDO 42 43 44 1 T1 +5V LM1084 1 + VUSB DGND R48 R49 RD0/SPP0 RD1/SPP1 RD2/SPP2 RD3/SPP3 RD4/SPP4 RD5/SPP5/P1B RD6/SPP6/P1C RD7/SPP7/P1D RA0/AN0 RA1/AN1 RA2/AN2/Vref-/CVref RA3/AN3/Vref+ RA4/T0CKI/C1OUT/RCV RA5/AN4/SS_N/HLVDIN/C2OUT C51 C50 10u 0.1u GND C49 22p IN +3.3V OUT 3 C52 2 XTI XTO + 0.1u C53 10u PORT4 DGND R50 R51 1 2 3 4 22 22 VUSB DD+ GND A A USB(B type) DGND PIC18F4550 Title AK4753-A Size B Date: 5 4 3 - 55 - 2 Document Number Rev 1 EEPROM Wednesday, September 29, 2010 Sheet 1 4 of 5 5 4 3 2 1 D D T2 5V 8 7 6 5 +5V C55 + C56 0.1u 10u 3.3V NC NC Vin Vout Vcont PCL NC GND VSS1 1 2 3 4 VSS2 TK73633AME C57 0.1u + C58 10u R53 0 JP12 GND VSS1 R54 0 DGND VSS1 DGND VSS1 AVDD T3 LM1084 IN OUT (open) C (open) C61 C60 C62 (open) (open) +5V J8 1 + 2 AVDD 1 TJ-563 (RED) DVDD + C59 47u C63 J9 (open) 1 TJ-563 (RED) 2 + L2 (short) 3 2 (open) R56 3.3V 1 GND 5V 1 R55 JP13 AVDD VSS1 C AVDD J10 1 TJ-563 (RED) DVDD VSS1 JP14 DVDD L3 (short) J11 2 DVDD D3.3V 1 TJ-563 (RED) 1 1 + 2 C64 47u VSS2 J12 AGND 1 TJ-563 (BLACK) VCC JP15 D3.3V L4 (short) 2 B VSS1 1 J13 DGND D3.3V 1 TJ-563 (BLACK) + C65 B DGND 47u DGND A A Title Size A3 - 56 - Date: 5 4 3 2 AKD4753-A Document Number Rev 1 POWER Wednesday, September 29, 2010 Sheet 1 5 of 5 - 57 - - 58 - - 59 - - 60 -