APL3201 Li+ Battery Charger with Thermal Regulation Features General Description • Programmable Charge Current Up to 1A • Charge Status Output Pins The APL3201 is a constant-current/constant-voltage linear charger for single cell Li+ batteries. • Soft-Start Limits Inrush Current • 4.2V Charge Voltage with ±1% Accuracy • Fixed 55mA Prequal Charge Current • Thermal Limiting Simplifies Board Design • External Thermistor Monitor • Enable/Disable Control • 3mm x 3mm DFN-10 Package (DFN3x3-10) • Disable Charging When VIN > 6.4V • Lead Free and Green Devices Available The APL3201 needs no external MOSFET or diodes, and accepts input voltage up to 6.0V. The small packages and low external component count make the APL3201 ideally suited for portable applications. On-chip thermal limiting simplifies PC board layout and allows optimum charging rate without the thermal limits imposed by worst-case battery and input voltage. When the APL3201 thermal limit is reached, the charger does not shut down but simply reduces charging current. Ambient or battery temperature can be monitored with an external thermistor. When the temperature is out of range, charging pauses. Other features include the STAT1 and 2 outputs to indicate four charge states, and the EN input, switches the (RoHS Compliant) APL3201 on or off. The APL3201 is available in 3mmx3mm DFN-10 package, Applications and operates over the -40°C to +85°C temperature range. • PDAs • MP3 Players • Cell Phones • Wireless Appliances Simplified Application Circuit INPUT Voltage Pin Configuration VIN STAT1 VIN STAT1 ISET GND EN 1 2 3 4 5 EP (Bottom) 10 BATT 9 BYP 8 STAT2 7 REF 6 THRM LI+ CELL BATT BYP STAT2 REF EN ISET GND THRM NTC THERMISTOR DFN3x3-10 (Top View) Note : EP should be connected to GND plane for better heat dissipation ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 1 www.anpec.com.tw APL3201 Ordering and Marking Information Package Code QA : DFN3x3-10 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APL3201 Assembly Material Handling Code Temperature Range Package Code APL3201 QA: APL 3201 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol VIN VEN, VBATT, VTHRM ICHG TJ TSTG TL (Note 1) Parameter Rating Unit VIN to GND -0.3 to 7 V EN, STAT1, STAT2, BATT, THRM to GND -0.3 to 7 V Charging Current 1.2 A Maximum Junction Temperature 150 °C -65 to 150 °C 260 °C Storage Temperature Range Maximum Lead Soldering Temperature, 10 Seconds Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA Parameter Junction To Air Thermal Resistance (Note 2) DFN3x3-10 Typical Value Unit 50 °C/W Note 2 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of DFN-10 is soldered directly on the PCB. Recommended Operating Conditions Symbol Parameter VIN VIN To GND ICHG Charging Current Range Unit 4.35 to 6.0 V 0.1 to 1 A TJ Junction Temperature -40 to 125 °C TA Ambient Temperature -40 to 85 °C Copyright ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 2 www.anpec.com.tw APL3201 Electrical Characteristics Refer to the typical application circuit. These specifications apply over VIN=5V, VBATT=4.2V, VTHRM=VREF/2, TJ= -40~125°C, TA= -40~85°C, unless otherwise specified. Typical values are at TA=25°C. Symbol Parameter Test Conditions APL3201 Unit Min. Typ. Max. VEN = 0V - 0.6 1.2 mA VEN = 5V, ICHG=0A - 2 4 mA 3.90 4.05 4.2 V 0.15 0.25 0.35 V - 4.20 - V -0.5 - 0.5 % % SUPPLY CURRENT IIN VIN Supply Current UNDER-VOLTAGE-LOCKOUT VIN UVLO Threshold VIN Rising VIN UVLO Hysteresis BATTERY VOLTAGE AND REFERENCE VOLTAGE VBATT BATT Regulation Voltage BATT Regulation Voltage Accuracy TA=25°C, VIN=4.35~6.0V TA =-40~85°C (TJ=-40~125°C) BATT Prequel Voltage Threshold Prequel Threshold Hysteresis VREF REF Regulation Voltage -1 - 1 2.8 3 3.2 V - 70 - mV - 3 - V REF Voltage Accuracy IREF=0~500µA, TJ=-40~125°C, VIN=4.35V~6.0V -2 - 2 % REF Maximum Output Current REF=GND - 1.5 - mA 100 - 1000 mA BATTERY CHARGING AND PRECHARGING CURRENT ICHG Charging Current Range ICHG=KSET x VSET / RSET, Without thermal regulation VSET ISET Regulation Voltage Without thermal regulation - 1 - V ISET Regulation Voltage Accuracy TJ=-40~125°C, VIN=4.35~6.0V -1 - 1 % Maximum ISET Output Current ISET=GND - 1.8 - mA Charging Current Set Factor 0.1A≤ICHG≤1A 940 1000 1060 - KSET Prequel Charging Current VBATT<2.8V 35 55 70 mA % of charger current set at ISET 8 12.5 19 % Hysteresis - 12.5 - % VIN to BATT Dropout Voltage ICHG=1A, VIN=5V - 250 450 mV VIN to BYP Dropout Voltage IBYP=5mA, VIN=5V - 300 - mV 0.79 0.81 0.82 VREF - 0.03 - VREF 0.28 0.29 0.30 VREF - 0.03 - VREF - 120 - °C 50 100 150 mV Charge-Done Current Threshold DROPOUT VOLTAGES THERMISTER MONITOR AND DIE TEMPERATURE REGULATION THRM Cold Trip Level VTHRM Rising THRM Cold Trip Level Hysteresis THRM Hot Trip Level VTHRM Falling THRM Hot Trip Level Hysteresis Die Thermal Regulation Limit THRM Disable Voltage Threshold Copyright ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 3 www.anpec.com.tw APL3201 Electrical Characteristics (Cont.) Refer to the typical application circuit. These specifications apply over VIN=5V, VBATT=4.2V, VTHRM=VREF/2, TJ= -40~125 °C, TA= -40~85°C, unless otherwise specified. Typical values are at TA=25°C. Symbol Parameter Test Conditions APL3201 Unit Min. Typ. Max. 4 7 12 ms SOFT-START AND REVSRSE CURRENT TSS Soft-Start Interval ICHG=0A to Fast-Charging Current BATT Input Current VIN=0V, VBATT=4.2V - - 8 µA BATT Shutdown Input Current VEN=0V, VIN=5V, VBATT=4.2V - - 4 µA STAT1, STAT2 Logic-Low Output Sinking 10mA - - 0.4 V STAT1, STAT2 Off-Leakage Current VSTAT1, 2=5V, VIN=0V - - 1 µA LOGIC INPUT/OUTPUTS EN Logic Input-High Level 1.6 - - V EN Logic Input-Low Level - - 0.4 V EN Input Bias Current - - 1 µA Pin Description PIN FUNCTION NO. NAME 1 VIN 2 STAT1 3 ISET Charging Current Setting Pin. Connecting a resistor from this pin to GND set the fast-charge current when the VIN is powering the charger. 4 GND Ground. 5 EN 6 THRM 7 REF 8 STAT2 Charge Status Output Pin 2. This pin is an active-high, open-drain output pin. Input Supply Pin. Provides power to the charger, VIN can range from 4.35V to 6.0V and should be bypassed with at least a 4.7µF capacitor. Charge Status Output Pin 1. This pin is an active-high, open-drain output pin. Charging Enable/Disable Control Pin. Drive EN high to begin charging, and EN low to stop charging. External Thermistor Connection Pin. THRM pauses charging when an externally connected thermistor (10kΩ at +25°C) is at less than 0°C or greater than +50°C. Connecting this pin to GND disables this function. 3V Reference Voltage Output Pin. Sources up to 500µA to bias the external thermistor. Bypass with 0.1µF to GND. REF loading does not affect BATT regulation accuracy. 9 BYP Bias Supply Pin for Internal Circuitry. Bypass with a 2.2µF capacitor to GND. 10 BATT Charger Output Pin. Connect this pin to the positive terminal of a Li+ battery. - EP Exposed Pad. Connect a large ground plane for maximum package heat dissipation. Connect directly to GND under the IC. Copyright ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 4 www.anpec.com.tw APL3201 Typical Operating Characteristics VIN Supply Current vs. VIN Input Voltage VIN Supply Current vs. VIN Input Voltage 4 4 VEN = 0V 3 VIN Supply Current (mA) VIN Supply Current (mA) VEN = 5V 2 1 3 2 1 0 0 0 1 2 3 4 5 6 0 7 1 2 VIN Input Voltage (V) 3 4 5 6 7 VIN Input Voltage (V) Off-Battery Leakage Current vs. Off-Battery Leakage Current vs. BATT Voltage VIN Input Voltage 8 Off-Battery Leakage Current (uA) Off-Battery Leakage Current (uA) 10 VEN = 0V VBATT =4.2V 8 6 4 2 0 VEN = 0V VIN = 0V 6 4 2 0 0 1 2 3 4 5 6 7 0 VIN Input Voltage (V) 1 2 3 Charge Current vs. Ambient Temperature 5 BATT Voltage vs. Junction Temperature 4.25 1200 VIN = 5V 4.24 1000 4.23 800 BATT Voltage (V) Charge Current (mA) 4 BATT Voltage (V) ICHG = set to 1A VBATT = 3.9V VIN =5V 600 400 4.22 4.21 4.2 4.19 4.18 4.17 200 4.16 0 -40 -20 0 20 40 60 80 100 4.15 -40 -20 120 Copyright ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 0 20 40 60 80 100 120 140 Junction Temperature (°C) Ambient Temperature (°C) 5 www.anpec.com.tw APL3201 Typical Operating Characteristics (Cont.) Charge Current vs. BATT Voltage Charge Current vs. (VIN-VBATT) 1200 1200 1000 Charge Current (mA) Charge Current (mA) ICHG = set to 1 A VIN = 5V, VEN = 5V ICHG = set to 1A 1000 800 600 400 200 800 ICHG = set to 750mA 600 400 200 0 0 0 1 2 3 4 5 0 BATT Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 0.2 0.4 0.6 0.8 1 V IN-V BATT (V) 6 www.anpec.com.tw APL3201 Operating Waveforms VIN Hot-Plug Power-Up Enable in Fast Charge VBATT=3.9V, VIN=5V CH1: VIN (5V/div) CH2: VBATT (2V/div) CH3: VSTAT1 (5V/div) CH4: ICHG (0.5A/div) Time: 5ms/div VBATT=3.9V, VIN=5V CH1: VEN (5V/div) CH2: VSTAT1 (5V/div) CH3: VSTAT2 (5V/div) CH4: ICHG (1A/div) Time: 20ms/div Enable in Precharge Enable in Charge Done VBATT=2.7V, VIN=5V CH1: VEN (5V/div) CH2: VSTAT1 (5V/div) CH3: VSTAT2 (5V/div) CH4: ICHG (50mA/div) Time: 20ms/div Copyright ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 VBATT=4.2V, VIN=5V CH1: VEN (5V/div) CH2: VSTAT1 (5V/div) CH3: VSTAT2 (5V/div) CH4: ICHG (50mA/div) Time: 20ms/div 7 www.anpec.com.tw APL3201 Block Diagram VIN Current sense BYP BATT 0.25 Ω 3.0V VREF REF STAT1 Charge Controller STAT2 EN ISET Thermistor Comparator Thermal Regulation THRM GND Typical Application Circuit 5V BATT VIN R2 C1 4.7µF R3 Li+ Cell C2 2.2µF 1.5KΩ 1.5KΩ ISET R1 STAT1 2KΩ STAT2 BYP REF C3 2.2µF C4 0.1µF R4 10KΩ ON THRM EN R5 NTC Thermistor 10KΩ at 25℃ OFF GND Designation C1 C2 C3 Description 4.7µF, 10V, X5R, 0805 Murata GRM188R61A475K 2.2µF, 6.3V, X5R, 0603 Murata GRM188R60J225K 2.2µF, 10V, X5R, 0603 Murata GRM188R61A225K Murata website: www.murata.com Copyright ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 8 www.anpec.com.tw APL3201 Function Description Precharge Current minimum battery voltage, maximum input voltage, and When the APL3201 is powered with a battery connected, the IC first detects if the cell voltage is ready for full charge maximum ambient temperature. When the APL3201 thermal limit is reached, the charger does not shut down current. If the cell voltage is less than the prequal level (3V typ), the battery is precharged with a 55mA current but simply reduces charging current. This allows the board design to be optimized for compact size and typical until the cell reaches the proper level. The full charging current, as set by ISET pin, is then applied. thermal conditions. The APL3201 reduces charging current to keep its die temperature below +120°C. The Charging Current Setting APL3201’s DFN3x3-10 package includes a bottom metal plate that reduces thermal resistance between the die The charge current is programmed by using a resistor and the PC board. The external pad should be soldered to a large ground plane. This helps dissipate power and from the ISET pin to the ground. The battery charge current is 1000 times the current out of the ISET pin. The keeps the die temperature below the thermal limit. The APL3201’s thermal regulator is set for a +120°C die battery charge current is calculated by the following equation: temperature. ICHG =KSET x VSET / RSET External Thermistor Monitor (THRM) Where The APL3201 features an internal window comparator to monitor battery pack temperature or ambient temperature VSET is ISET regulation voltage (nominal=1V). KSET is the charging current set factor (nominal=1000). with an external negative temperature coefficient thermistor. In typical systems, temperature is monitored The charging current set factor and the ISET regulation voltage are shown in the Electrical Characteristics. The to prevent charging at ambient temperature extremes (below 0°C or above +50°C). When the temperature ISET regulation voltage is reduced by thermal regulation function. moves outside these limits, charging is stopped. If the V THRM returns to within its normal window, charging Enable (EN) resumes. Connect THRM to GND when not using this feature. Note that the temperature monitor at THRM en- The enable input, EN, switches the charging of APL3201 tirely separates from the on-chip temperature limiting discussed in the Thermal Regulation section. The input on or off. With EN high, the APL3201 can begin charging. When EN is low, charging stops, REF is shutdown, and thresholds for the THRM input are 0.74 x VREF for the COLD trip point and 0.29 x VREF for the HOT trip point. STAT1 and STAT2 outputs are off (high). Battery Full Indication REF Charge-done occurs when ICHG falls to 12.5% of the current set by RSET and the charger is in voltage mode (VBATT near 4.2V). After the APL3201 enunciates the charge-done 10kΩ signal, it keeps operating in voltage mode without turning off the charger. The STAT1 is turned off (high) and STAT2 Thermistor 10kΩ at +25°C To Regulator 100mV THRM TCOLD is turned on (low) when the charger is into charge-done state. THOT Thermal Regulation FFigure 1. Thermistor Sensing Block Diagram On-chip thermal limiting in the APL3201 simplifies PC board layout and allows charging rates to be automatically optimized without constraints imposed by worst-case Copyright ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 9 www.anpec.com.tw APL3201 Function Description (Cont.) Charge Status Outputs Disable Charging for VIN>6.4V The open-drain STAT1 and STAT2 outputs indicate four charger operations are shown in Table 1. The two out- When input voltage is over 6.4V overvoltage threshold, puts can be used to drive LEDs or communicate to the host processor. Note that OFF indicates the open-drain will be turned on until the input voltage is below the OVP transistor is turned off. is 7V. If the input voltage is over 7V the IC may be damaged. CHARGE STATE STAT1 STAT2 Precharge in progress ON ON Fast charge in progress ON OFF Charge done OFF ON Charge suspended OFF OFF the charging of APL3201 will be turned off. The charging threshold. The absolute maximum rating of input voltage Table 1. Status Pin Summary Soft-Start The APL3201 includes a soft-start function to control the rise rate of the charging current rising from zero to the fast-charging current level in constant current mode. During charger soft-start, the APL3201 ramps up the voltage on ISET pin with constant well-controlled slew rate. The charging current is proportional to the ISET voltage. The soft-start interval is 7ms (typical), which is independent of the fast-charging current level. ICHG 4.2V VBATT 3.0V Charge Done Full Charge Precharge Constant Current Mode Voltage Mode Figure 2. Typical Charging Profile Copyright ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 10 www.anpec.com.tw APL3201 Applicaiton Information where: TJ=device junction temperature STAT Pins The STAT1 and STAT2 outputs indicate four charger TA= ambient temperature PD=device power dissipation operations. These two pins can be used to drive LEDs or communicate to the host processor. When status pins are monitored by a processor, there should be a 10kΩ The device power dissipation, PD, is the function of the pull-up resistor to connect each status pin and the VCC of the processor; furthermore, when the status is viewed by charge rate and the voltage drop across the internal FET. It can be calculated by the following equation: the LED, the LED with a current rating is less than 10mA and a resistor should be selected to connect the LED in PD = (VIN − VBATT ) × ICHG series, so the current will be limited to the desired current value. The resistor is calculated by the following PCB Layout Consideration equation: R2,3 = The APL3201 is packaged in a thermally enhanced QFN ( VIN − VLED _ ON) PD package. The package includes a thermal pad to provide an effective thermal contact between the device and the In other words, the LED and resistor between the input and each status pin shoule be in series. printed circuit board. Connecting the exposed pad to a large copper ground plane on the backside of the circuit Capacitor Selection board through several thermal vias for heatsinking is recommended. Connecting the battery to BATT as close Typically, a 4.7µF ceramic capacitor is used to connect to the device as possible provides accurate battery voltage sensing. All decoupling capacitors and filter capaci- from VIN to GND. For high charging current, it is recommended to use a larger input bypass capacitance to re- tors should be placed as close as possible to the device. duce supply noise. There is a ceramic capacitor connecting from BATT to GND for proper stability. To work The high-current charge path into VIN and from the BATT pin must be short and wide to minimize voltage drops. well with most application, at least a 2.2µF X5R ceramic capacitor is required. Thermal Consideration The APL3201 is available in a thermally enhanced QFN package with an exposed pad. It is recommended to connect the exposed pad to a large copper ground plane on the backside of the circuit board through several thermal vias for heatsinking. The exposed pad transfers heat away from the device, allowing the APL3201 to charge the battery with maximum current while minimizing the increase in die temperature. The most common measure of package thermal performance is thermal resistance measured from the device junction to the air surrounding the package surface (θJA). The θJA can be calculated by the following equation: θJA = TJ − TA PD Copyright ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 11 www.anpec.com.tw APL3201 Package Information DFN3x3-10 D E A b Pin 1 A1 D2 A3 L E2 Pin 1 Corner e S Y M B O L DFN3x3-10 MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.80 1.00 0.031 0.039 A1 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF b 0.18 0.30 0.007 0.012 D 2.90 3.10 0.114 0.122 D2 2.20 2.70 0.087 0.106 E 2.90 3.10 0.114 0.122 E2 1.40 1.75 0.055 0.069 0.50 0.012 e 0.50 BSC L 0.30 K 0.20 0.020 BSC 0.020 0.008 Note : 1. Followed from JEDEC MO-229 VEED-5. Copyright ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 12 www.anpec.com.tw APL3201 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application DFN3x3-10 A H T1 C d D W E1 F 178.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 8.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 3.30±0.20 3.30±0.20 1.30±0.20 (mm) Devices Per Unit Package Type DFN3x3-10 Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 Quantity 3000 13 www.anpec.com.tw APL3201 Taping Direction Information DFN3x3-10 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 14 www.anpec.com.tw APL3201 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT ESD Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 15 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV, VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APL3201 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 16 www.anpec.com.tw