ASM5I9772A June 2005 rev 0.3 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Features The ASM5I9772A features one on-chip crystal oscillator and two LVCMOS reference clock inputs and provides 12 Output frequency range: 8.33 MHz to 200 MHz Input frequency range: 6.25 MHz to 125 MHz outputs partitioned in three banks of four outputs each. 2.5V or 3.3V operation Each bank divides the VCO output per SEL(A:C) settings, Split 2.5V/3.3V outputs see Functional Table. ±2% max Output duty cycle variation These dividers allow output to input ratios of 8:1, 6:1, 5:1, 12 clock outputs: drive up to 24 clock lines 4:1, 3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4, 1:1, and 5:6. Each One feedback output LVCMOS-compatible output can drive 50Ω series or Three reference clock inputs: crystal or LVCMOS parallel-terminated 300pS max output-output skew terminated transmission lines, each output can drive one or Phase-locked loop (PLL) bypass mode two traces, giving the device an effective fanout of 1:24. ‘SpreadTrak’ Output enable/disable Pin-compatible with CY29772, MPC9772 and MPC972 Industrial temperature range: –40°C to +85°C 52 pin 1.0 mm TQFP package transmission lines. For series- The PLL is ensured stable given that the VCO is configured to run between 200 MHz and 500 MHz. This allows a wide range of output frequencies from 8 MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal RoHS Compliance VCO is running at multiples of the input reference clock set Functional Description by the feedback divider, see Frequency Table. The ASM5I9772A is a low-voltage high-performance When PLL_EN is LOW, PLL is bypassed and the reference 200 MHz PLL-based zero delay buffer, designed for high- clock directly feeds the output dividers. This mode is fully speed clock-distribution applications. static and the minimum input clock frequency specification does not apply. Block Diagram XIN XOUT VCO_SEL PLL_EN REF_SEL D 0 TCLK0 0 TCLK1 TCLK_SEL 1 Phase Detector VCO Q Sync Frz 1 QA0 QA1 QA2 QA3 LPF FB_IN D Q Sync Frz FB_SEL2 QB0 QB1 QB2 QB3 MR#/OE Power-On Reset /4,/6,/8,/12 D Q Sync Frz QC0 QC1 /4,/6,/8,/10 SELA(0,1) 2 SELB(0,1) 2 SELC(0,1) 2 /2/4,/6,/8 D Q Sync Frz D Q Sync Frz FB_OUT D Q Sync Frz SYNC 0 /4,/6,/8,/10 /2 1 QC2 QC3 Sync Pulse FB_SEL(0,1) 2 Data Generator SCLK SDATA Output Disable Circuitry 12 INV_CLK Alliance Semiconductor 2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. ASM5I9772A June 2005 rev 0.3 SELB1 SELB0 SELA1 SELA0 QA3 VDDQA QA2 VSS QA1 VDDQA QA0 VSS VCO_SEL Pin Configuration 52 51 50 49 48 47 46 45 44 43 42 41 40 AVSS 1 39 VSS MR#/OE 2 38 QB0 SCLK 3 37 VDDQB SDATA 4 36 QB1 FB_SEL2 5 35 VSS 34 QB2 33 VDDQB PLL_EN 6 REF_SEL 7 ASM5I9772A TCLK_SEL 8 32 QB3 TCLK0 9 31 FB_IN TCLK1 10 30 VSS XIN 11 29 FB_OUT XOUT 12 28 VDD AVDD 13 27 FB_SEL0 FB_SEL1 SYNC VSS QC0 VDDQC QC1 SELC0 QC2 SELC1 VDDQC QC3 VSS INV_CLK 14 15 16 17 18 19 20 21 22 23 24 25 26 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 2 of 15 ASM5I9772A June 2005 rev 0.3 Pin Description1 Pin Name I/O Type Description 11 XIN I Analog Crystal oscillator input. 12 XOUT O Analog Crystal oscillator output. 9 TCLK0 I, PU LVCMOS LVCMOS/LVTTL reference clock input. 10 TCLK1 I, PU LVCMOS LVCMOS/LVTTL reference clock input. 44, 46, 48, 50 QA(3:0) O LVCMOS Clock output bank A. 32, 34, 36, 38 QB(3:0) O LVCMOS Clock output bank B. 16, 18, 21, 23 QC(3:0) O LVCMOS 29 FB_OUT O LVCMOS 31 FB_IN I, PU LVCMOS Clock output bank C. Feedback clock output. Connect to FB_IN for normal operation. Feedback clock input. Connect to FB_OUT for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. 25 SYNC O LVCMOS 6 PLL_EN I, PU LVCMOS 2 MR#/OE I, PU LVCMOS Synchronous pulse output. This output is used for system synchronization. PLL enable/bypass input. When Low, PLL is disabled/bypassed and the input clock connects to the output dividers. Master reset and Output enable/disable input. See Table 2 8 TCLK_SEL I, PU LVCMOS LVCMOS Clock reference select input. See Table 2. 7 REF_SEL I, PU LVCMOS LVCMOS/LVPECL Reference select input. See Table 2. 52 VCO_SEL I, PU LVCMOS VCO Operating frequency select input. See Table 2. 14 INV_CLK I, PU LVCMOS QC(2,3) Phase selection input. See Table 2. 5, 26, 27 FB_SEL(2:0) I, PU LVCMOS Feedback divider select input. See Table 6. 42, 43 SELA(1,0) I, PU LVCMOS Frequency select input, Bank A. See Table 3. 40, 41 SELB(1,0) I, PU LVCMOS Frequency select input, Bank B. See Table 4. 19, 20 SELC(1,0) I, PU LVCMOS Frequency select input, Bank C. See Table 5. 3 SCLK I, PU LVCMOS Serial Clock input. 4 45, 49 33, 37 22, 17 13 SDATA VDDQA VDDQB VDDQC AVDD I, PU Supply Supply Supply Supply LVCMOS VDD VDD VDD VDD Serial Data input. 2.5V or 3.3V Power supply for bank A output clocks2,3. 2.5V or 3.3V Power supply for bank B output clocks.2,3 2.5V or 3.3V Power supply for bank C output clocks. 2,3 2.5V or 3.3V Power supply for PLL. 2,3 28 VDD Supply VDD 2.5V or 3.3V Power supply for core and inputs.2,3 1 AVSS Supply Ground Analog Ground. 15, 24, 30, 35, 39, 47, 51 VSS Supply Ground Common Ground. Note: 1.PU = Internal pull up, PD = Internal pull down. 2. A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their high-frequency filtering characteristics will be cancelled by the lead inductance of the traces. 3 AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, and VDDQC power supply pins. 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 3 of 15 ASM5I9772A June 2005 rev 0.3 ‘SpreadTrak’ Many systems being designed now utilize a technology When a zero delay buffer is not designed to pass the called Spread Spectrum Frequency Timing Generation. Spread Spectrum feature through, the result is a ASM5I9772A is designed so as not to filter off the Spread significant amount of tracking skew which may cause Spectrum feature of the Reference Input, assuming it problems in the systems requiring synchronization. exists. Table 1. Frequency Table Feedback Output Divider ÷4 VCO Input Clock * 4 Input Frequency Range (AVDD = 3.3V) 50 MHz to 125 MHz Input Frequency Range (AVDD =2.5V) 50 MHz to 95 MHz ÷6 Input Clock * 6 33.3 MHz to 83.3 MHz 33.3 MHz to 63.3 MHz ÷8 Input Clock * 8 25 MHz to 62.5 MHz 25 MHz to 47.5 MHz ÷10 Input Clock * 10 20 MHz to 50 MHz 20 MHz to 38 MHz ÷12 Input Clock * 12 16.6 MHz to 41.6 MHz 16.6 MHz to 31.6 MHz ÷16 Input Clock * 16 12.5 MHz to 31.25 MHz 12.5 MHz to 23.75 MHz ÷20 Input Clock * 20 10 MHz to 25 MHz 10 MHz to 19 MHz ÷24 Input Clock * 24 8.3 MHz to 20.8 MHz 8.3 MHz to 15.8 MHz ÷32 Input Clock * 32 6.25 MHz to 15.625 MHz 6.25 MHz to 11.8 MHz ÷40 Input Clock * 40 5 MHz to 12.5 MHz 5 MHz to 9.5MHz Table 2. Function Table (Configuration Controls) Control Default 0 1 REF_SEL 1 TCLK0, TCLK1 Crystal oscillator TCLK_SEL 1 TCLK0 TCLK1 VCO_SEL 1 VCO÷2 (low input frequency range) VCO÷1 (high input frequency range) PLL_EN 1 Bypass mode, PLL disabled. The input clock connects to the output dividers PLL enabled. The VCO output connects to the output dividers INV_CLK 1 QC2 and QC3 are in phase with QC0 and QC1 QC2 and QC3 are inverted (180° phase shift) with respect to QC0 and QC1 1 Outputs disabled (three-state) and reset of the device. During reset/output disable the PLL feedback loop is open and the VCO running at its minimum frequency. The device is reset by the internal power-on reset (POR) circuitry during power-up. Outputs enabled MR#/OE 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 4 of 15 ASM5I9772A June 2005 rev 0.3 Table 5. Function Table (Bank C) Table 3. Function Table (Bank A) VCO_SEL SELA1 SELA0 QA(0:3) VCO_SEL SELC1 SELC0 QC(0:3) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ÷8 ÷12 ÷16 ÷24 ÷4 ÷6 ÷8 ÷12 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ÷4 ÷8 ÷12 ³16 ÷2 ÷4 ÷6 ÷8 Table 4. Function Table (Bank B) Table 6. Function Table (FB_OUT) VCO_SEL SELB1 SELB0 QB(0:3) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ÷8 ÷12 ÷16 ÷20 ÷4 ÷6 ÷8 ÷10 VCO_SEL FB_SEL2 FB_SEL1 FB_SEL0 FB_OUT 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ÷8 ÷12 ÷16 ÷20 ÷16 ÷24 ÷32 ÷40 ÷4 ÷6 ÷8 ÷10 ÷8 ÷12 ÷16 ÷20 Absolute Maximum Conditions Parameter Description VDD DC Supply Voltage VDD VIN VOUT DC Operating Voltage DC Input Voltage DC Output Voltage VTT Output termination Voltage LU RPS TS TA TJ ØJC ØJA Latch-up Immunity Power Supply Ripple Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESDH ESD Protection (Human Body Model) FIT Failure in Time Condition Functional Relative to VSS Relative to VSS Functional Ripple Frequency < 100 kHz Non-functional Functional Functional Functional Functional Min Max Unit -0.3 5.5 V 2.375 -0.3 -0.3 3.465 VDD+ 0.3 VDD+ 0.3 V V V - VDD ÷2 V 200 -65 -40 - 150 +150 +85 +150 23 55 mA mVp-p °C °C °C °C/W °C/W 2000 - V Manufacturing test 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 10 ppm 5 of 15 ASM5I9772A June 2005 rev 0.3 DC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C) Parameter Description Condition Min Typ Max Unit - - 0.7 V 1.7 – 1.8 - - VDD+0.3 0.6 -100 V V V µA VIL= VDD - - 100 µA PLL Supply Current AVDD only - 5 10 mA Quiescent Supply Current All VDD pins except AVDD - - 8 mA IDD Dynamic Supply Current Outputs loaded @ 100 MHz - 135 - mA CIN Input Pin Capacitance ZOUT Output Impedance VIL Input Voltage, Low LVCMOS VIH VOL VOH IIL Input Voltage, High Output Voltage, Low1 Output Voltage, High1 Input Current, Low2 LVCMOS IOL= 15mA IOH= –15mA VIL= VSS IIH Input Current, High2 IDDA IDDQ - 4 - pF 14 18 22 Ω Note: 1. Driving one 50Ωparallel-terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 Ωseries-terminated transmission lines 2. Inputs have pull-up or pull-down resistors that affect the input current. DC Electrical Specifications (VDD= 3.3V ± 5%, TA= –40°C to +85°C) Parameter Description Condition Min Typ Max Unit VIL Input Voltage, Low LVCMOS - - 0.8 V VIH Input Voltage, High LVCMOS 2.0 - VDD + 0.3 V VOL Output Voltage, Low1 IOL= 24 mA - - 0.55 VOH IIL Output Voltage, High1 Input Current, Low2 IOL= 12 mA IOH= –24 mA VIL= VSS 2.4 - - 0.30 -100 V µA IIH Input Current, High2 VIL= VDD - - 100 µA IDDA PLL Supply Current AVDD only - 5 10 mA IDDQ Quiescent Supply Current All VDD pins except AVDD - - 8 mA IDD Dynamic Supply Current Outputs loaded @ 100 MHz - 225 - mA CIN Input Pin Capacitance - 4 - pF ZOUT Output Impedance 12 15 18 Ω V Note: 1. Driving one 50Ωparallel-terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 Ωseries-terminated transmission lines 2. Inputs have pull-up or pull-down resistors that affect the input current. 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 6 of 15 ASM5I9772A June 2005 rev 0.3 AC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C)1 Parameter Description fVCO fXTAL VCO Frequency Crystal Frequency Range fin Input Frequency frefDC tr, tf Input Duty Cycle TCLK Input Rise/FallTime fMAX Maximum Output Frequency fSCLK Serial Clock Frequency DC Output Duty Cycle tr, tf Output Rise/Fall times Propagation Delay (static phase offset) t(φ) tsk(O) Output-to-Output Skew tsk(B) tPLZ, HZ tPZL, ZH Bank-to-Bank Skew Output Disable Time Output Enable Time BW PLL Closed Loop Bandwidth (–3 dB) Condition Min Typ Max Unit 200 10 50 33.3 25 20 16.6 12.5 10 8.3 6.25 5 - 380 25 95 63.3 47.5 38 31.6 23.75 19 15.8 11.8 9.5 MHz MHz 0 - 200 fMAX < 100 MHz fMAX > 100 MHz 0.6V to 1.8V 25 100 50 33.3 25 20 16.6 12.5 10 8.3 47.5 45 0.1 - 75 1.0 190 95 63.3 47.5 38 31.6 23.75 19 15.8 20 52.5 55 1.0 TCLK to FB_IN -125 - 125 - 1.3–2.0 0.7–1.3 0.9–1.3 0.6–1.1 0.6–0.9 0.4–0.6 0.6–0.9 75 100 150 400 10 10 - see Table 7 ÷4 Feedback ÷6 Feedback ÷8 Feedback ÷10 Feedback ÷12 Feedback ÷16 Feedback ÷20 Feedback ÷24 Feedback ÷32 Feedback ÷40 Feedback Bypass mode (PLL_EN = 0) 0.7V to 1.7V ÷2 Output ÷4 Output ÷6 Output ÷8 Output ÷10 Output ÷12 Output ÷16 Output ÷20 Output ÷24 Output Skew within Bank A Skew within Bank B Skew within Bank C ÷4 Feedback ÷6 Feedback ÷8 Feedback ÷10 Feedback ÷12 Feedback ÷16 Feedback ÷20 Feedback MHz % nS MHz MHz % nS pS pS pS nS nS MHz Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed by characterization and are not 100% tested. 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 7 of 15 ASM5I9772A June 2005 rev 0.3 AC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C) (Continued)6 Parameter tJIT(CC) tJIT(PER) Description Cycle-to-Cycle Jitter Period Jitter Condition Min Typ Max Unit Same frequency (125 MHz) RMS (1σ) Same frequency Multiple frequencies Same frequency (125 MHz) RMS (1σ) Same frequency Multiple frequencies - 7 30 pS - 6 150 435 30 pS 45 - 75 235 150 pS tJIT(φ) I/O Phase Jitter - tLOCK Maximum PLL Lock Time - - 1 mS Min Typ Max Unit - 500 25 125 83.3 62.5 50 41.6 31.25 25 20.8 15.625 12.5 200 75 1.0 200 125 83.3 62.5 50 41.6 31.25 25 20.8 20 52 55 1.0 MHz MHz fMAX< 100 MHz fMAX > 100 MHz 0.55V to 2.4V 200 10 50 33.3 25 20 16.6 12.5 10 8.3 6.25 5 0 25 100 50 33.3 25 20 16.6 12.5 10 8.3 48 45 0.1 TCLK to FB_IN, same VDD -125 - 125 pS - - 75 100 pS AC Parameters (VDD= 3.3V ± 5%, TA= –40°C to +85°C)6 Parameter Description fVCO fXTAL VCO Frequency Crystal Frequency Range fin Input Frequency frefDC tr, tf Input Duty Cycle TCLK Input Rise/FallTime fMAX Maximum Output Frequency fMAX Maximum Output Frequency (continued) fSCLK Serial Clock Frequency DC Output Duty Cycle tr, tf Output Rise/Fall times Propagation Delay (static phase offset) t(φ) tsk(O) Output-to-Output Skew Condition see Table 7 ÷4 Feedback ÷6 Feedback ÷8 Feedback ÷10 Feedback ÷12 Feedback ÷16 Feedback ÷20 Feedback ÷24 Feedback ÷32 Feedback ÷40 Feedback Bypass mode (PLL_EN = 0) 0.8V to 2.0V ÷2 Output ÷4 Output ÷6 Output ÷8 Output ÷10 Output ÷12 Output ÷16 Output ÷20 Output ÷24 Output Skew within Bank A Skew within Bank B 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. MHz % nS MHz MHz MHz % nS 8 of 15 ASM5I9772A June 2005 rev 0.3 AC Parameters (VDD= 3.3V ± 5%, TA= –40°C to +85°C) (Continued)6 Parameter Description Condition Skew within Bank C Min Typ Max - - 150 Unit tsk(B) Bank-to-Bank Skew - - 325 pS tPLZ, HZ Output Disable Time - - 8 nS tPZL, ZH Output Enable Time - - 8 nS ÷4 Feedback - 1.3 - 2.0 - ÷6 Feedback - 0.7 - 1.3 - ÷8 Feedback - 0.9 - 1.3 - ÷10 Feedback - 0.6 - 1.1 - ÷12 Feedback - 0.6 - 0.9 - ÷16 Feedback - 0.4 - 0.6 - ÷20 Feedback - 0.6 - 0.9 - Same frequency (125 MHz) RMS (1σ ) - 7 30 Same frequency - - 100 BW tJIT(CC) tJIT(PER) PLL Closed-Loop Bandwidth (–3 dB) Cycle-to-Cycle Jitter Period Jitter tJIT(φ) I/O Phase Jitter tLOCK Maximum PLL Lock Time MHz pS Multiple frequencies - - 375 Same frequency (125 MHz) RMS (1σ ) - 6 30 Same frequency - 45 75 Multiple frequencies - - 225 I/O same VDD - - 150 pS - - 1 mS Sync Output In situations where output frequency relationships are not integer multiples of each other, the SYNC output provides a signal for system synchronization. The ASM5I9772A monitors the relationship between the QA and the QC output clocks. It provides a low going pulse, one period in duration, one period prior to the coincident rising edges of the QA and QC outputs. pS The duration and the placement of the pulse depend on the higher of the QA and QC output frequencies. The following timing diagram illustrates various waveforms for the SYNC output. Note that the SYNC output is defined for all possible combinations of the QA and QC outputs even though under some relationships the lower frequency clock could be used as a synchronizing signal. 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 9 of 15 ASM5I9772A June 2005 rev 0.3 VCO 1:1 Mode QA QC SYNC 2:1 Mode QA QC SYNC 3:1 Mode QA QC SYNC 3:2 Mode QA QC SYNC 4:1 Mode QA QC SYNC 4:3 Mode QA QC SYNC 6:1 Mode QA QC SYNC Figure 1 Power Management The individual output enable / freeze control of the ASM5I9772A allows the user to implement unique power management schemes into the design. The outputs are stopped in the logic ‘0’ state when the freeze control bits are activated. The serial input register contains one programmable freeze enable bit for 12 of the 14 output clocks. The QC0 and FB_OUT outputs cannot be frozen with the serial port. This avoids any potential lock up situation should an error occur in the loading of the serial data. An output is frozen when a logic ‘0’ is programmed and enabled when a logic ‘1’ is written. The enabling and freezing of individual outputs is done in such a manner as to eliminate the possibility of partial “runt” clocks. The serial input register is programmed through the SDATA input by writing a logic ‘0’ start bit followed by 12 NRZ freeze enable bits. The period of each SDATA bit equals the period of the free running SCLK signal. The SDATA is sampled on the rising edge of SCLK. 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 10 of 15 ASM5I9772A June 2005 rev 0.3 Start Bit D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 Figure 2. D0-D3 are the control bits for QA0-QA3, respectively D4-D7 are the control bits for QB0-QB3, respectively D8-D10 are the control bits for QC1-QC3, respectively D11 is the control bit for SYNC Table 7. Suggested Oscillator Crystal Parameters Parameter Description Conditions TC Frequency Tolerance TS Frequency Temperature Stability TA Aging CL Load Capacitance Effective Series Resistance (ESR) RESR (TA–10° to +60°C) Min Typ Max Unit – – ±1100 PPM – – ± 100 PPM (First three years @ 25°C) – – 5 PPM/Yr The crystal’s rated load – 20 – pF – 40 80 Ohm Zo = 50 ohm Pulse Generator Z = 50 ohm RT = 50 ohm VTT VTT Figure 3. LVCMOS_CLK AC Test Reference for VDD = 3.3V/2.5V VDD LVCMOS_CLK VDD/2 GND VDD FB_IN VDD/2 t(φ) GND Figure 4. LVCMOS Propagation Delay t(φ), Static Phase Offset 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 11 of 15 ASM5I9772A June 2005 rev 0.3 VDD VDD/2 GND tP T0 DC = tP / T0 x 100% Figure 5. Output Duty Cycle (DC) VDD VDD/2 GND VDD VDD/2 tSK(0) GND Figure 6. Output-to-Output Skew, tsk(O) 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 12 of 15 ASM5I9772A June 2005 rev 0.3 Package Information 52-lead TQFP Package SECTION A-A Dimensions Symbol Inches Min Max Millimeters Min Max A …. 0.0472 … 1.2 A1 0.0020 0.0059 0.05 0.15 A2 0.0374 0.0413 0.95 1.05 D 0.4646 0.4803 11.8 12.2 D1 0.3898 0.3976 9.9 10.1 E 0.4646 0.4803 11.8 12.2 E1 0.3898 0.3976 9.9 10.1 L 0.0177 0.0295 0.45 0.75 L1 0.03937 REF 1.00 REF T 0.0035 0.0079 0.09 0.2 T1 0.0038 0.0062 0.097 0.157 b 0.0102 0.0150 0.26 0.38 b1 0.0106 0.0130 0.27 0.33 R0 0.0031 0.0079 0.08 0.2 a 0° 7° 0° 7° e 0.0256 BASE 0.65 BASE 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 13 of 15 ASM5I9772A June 2005 rev 0.3 Ordering Information Part Number Marking Package Type Operating Range ASM5I9772A-52-ET ASM5I9772A 52-pin TQFP, Tray Industrial ASM5I9772A-52-ER ASM5I9772A 52-pin TQFP – Tape and Reel Industrial ASM5I9772AG-52-ET ASM5I9772AG 52-pin TQFP, Tray, Green Industrial ASM5I9772AG-52-ER ASM5I9772AG 52-pin TQFP – Tape and Reel, Green Industrial Device Ordering Information A S M 5 I 9 7 7 2 A G - 5 2 - E T R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 14 of 15 ASM5I9772A June 2005 rev 0.3 Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: ASM5I9772A Document Version: 0.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. 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Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 15 of 15