Power Supply IC Series for TFT-LCD Panels
12V Input Multi-channel
System Power Supply IC
BD8166EFV
No.09035EBT14
●Description
The BD8166EFV is a system power supply for the TFT-LCD panels used for liquid crystal TVs.
Incorporates two high-power FETs with low on resistance for large currents that employ high-power packages, thus driving
large current loads while suppressing the generation of heat. A charge pump controller is incorporated as well, thus greatly
reducing the number of application components.
●Features
1) Step-up and step-down DC/DC converter
2) Incorporates 2-A N-channel FET.
3) Incorporates positive/negative charge pumps.
4) Incorporates a gate shading function.
5) Input voltage limit: 6 V to 18 V
6) Feedback voltage: 1.25 V ± 1.6%
7) Switching frequency: 500 kHz
8) Protection circuit: Undervoltage lockout protection circuit
Thermal shutdown circuit
Overcurrent protection circuit
Short protection circuit of timer latch type
9) HTSSOP-B40 Package
●Applications
Power supply for the TFT-LCD panels used for LCD TVs
●Absolute maximum ratings (Ta = 25℃)
Parameter
Symbol
Limit
Unit
Vcc, PVCC
19
V
Vo1 voltage
Vo1
19
V
Vo2 voltage
Vo2
40
V
IG Voltage
IGH
7
V
Power supply voltage
Maximum junction temperature
Power dissipation
Tjmax
150
℃
Pd
4700*1
mW
Operating temperature range
Topr
-40 to 85
℃
Storage temperature range
Tstg
-55 to 150
℃
* Reduced by 37.6 mW/℃ over 25℃, when mounted on a glass epoxy 4-layer board (70 mm 70 mm 1.6 mm)
(Copper foil on back 70 mm 70 mm).
●Recommended Operating Ranges (Ta = 25℃)
Parameter
Symbol
Limit
VCC, PVCC
Vo1 voltage
Vo1
8
18
V
Vo2 voltage
Vo2
—
39
V
I G Voltage
IGH
—
5
V
SW current
SW1, SW2
—
2
A
Power supply voltage
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1/17
Max.
18
Unit
Min.
6
V
2009.07 - Rev.B
Technical Note
BD81666EFV
●Electrical characteristics (Unless otherwise specified, Ta = 25°C, VCC = 15 V, Ta = 25℃)
1. DC/DC Converter Block
Limit
Parameter
Symbol
Unit
Min.
Typ.
Max.
Conditions
[Soft start block SS1 and SS2]
SS source current
Iso
6
10
14
µA
Vss = 1.0 V
SS sinking current
Isi
0.5
2
—
mA
Vss = 1.0 V
Clamp voltage
Vcl
1.7
1.9
2.1
V
FB input bias current 1 and 2
IFB1, 2
—
0.4
1.5
µA
VFB = 0.5 V
Feedback voltage 1 and 2
VFB1, 2
1.230
1.250
1.270
V
Buffer
Voltage gain
AV
—
200
—
V/V
COMP sinking current
IoI
1
2
4
mA
VFB = 1.5 V, COMP = 1.5 V
COMP source current
Ioo
-12
-6
-2
mA
VFB = 1.0 V COMP = 1.0 V
On resistance on high side
Ron h
—
200
300
mΩ
Io = 1A*
On resistance on low side
Ron l
—
2
3
Ω
Ioff
—
0.2
—
mA
Current limit
Insw
2
—
—
A
Maximum duty ratio
DMax
—
97
—
%
[Error amp block FB1 and FB2]
[Switch output block SW1 and SW2]
Off current
Io = 20 mA*
*
2. Positive/Negative Charge Pump Block
Parameter
Symbol
Limit
Min.
Typ.
Max.
Unit
Conditions
[Error amp block FB3 and FB4]
Input bias current 3
IFB3
—
0.1
0.5
µA
Input bias current 4
IFB4
—
0.1
0.5
µA
Feedback voltage 3
VFB3
1.18
1.25
1.32
V
Feedback voltage 4
VFB4
1.18
1.25
1.32
V
SS source current
IDSO
3
5
7
µA
VDLS = 0.5 V
SS sinking current
IDSI
0.2
0.5
—
mA
VDLS = 0.5 V
Startup voltage
VST
0.52
0.65
0.78
V
N-channel on resistance
RON_NC
—
4
8
Ω
Io = 20 mA*
P-channel on resistance
RON_PC
—
4
8
Ω
Io = 20 mA*
[Delay start block SS3 and SS4]
[Switch block C1L, C2L, and C3]
○Design guarantee (No total shipment inspection is made.)
*This product is not designed for protection against radio active rays.
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2/17
2009.07 - Rev.B
Technical Note
BD81666EFV
●Electrical characteristics (Unless otherwise specified, Ta = 25℃, VCC = 15 V, Ta = 25℃)
3. Gate Shading Block
Limit
Parameter
Symbol
Unit
Min.
Typ.
Max.
Conditions
[Output block Vo2GS and GSOUT]
N-channel on resistance
Ron_NGS
—
10
15
Ω
Io = 20 mA*
P-channel on resistance
Ron_PGS
—
55
80
Ω
Io = 20 mA*
N-channel leak current
ILEAK_NGS
—
—
10
µA
P-channel leak current
ILEAK_PGS
—
—
10
µA
IGH voltage
IGH
1.9
2.9
5
V
IGL voltage
LGL
—
0
0.9
V
IG sinking current
IIG
8
16.5
25
µA
[Input block IG]
IG = 3.3 V
4. Overall
Parameter
Symbol
Limit
Unit
Conditions
Min.
Typ.
Max.
VREF
2.84
2.90
2.96
V
∆V
—
5
20
mV
VREG
4.5
5.0
5.5
V
∆V
—
50
100
mV
Fosc
400
500
600
kHz
IFL
—
—
10
µA
Ron_FL
—
1
—
kΩ
SCP lease current
Iscp
6
10
14
µA
Threshold voltage
Vth_scp
0.96
1.2
1.44
V
Off sinking current
IOFFS
1
3
—
mA
Voso
-10
0
10
mV
Input bias current
Ibo
—
0.1
1
µA
Drive current
Ioo
50
100
350
mA
Slew rate
SRo
5
12
—
V/MS
GB product
GBW
—
12
—
MHz
High output voltage
Voho
Vol-0.3
Vol-0.1
—
V
Io = -5 mA
Low output voltage
Vohl
—
0.1
0.3
V
Io = 5 mA
VUVLO
4.8
5.1
5.4
V
Icc
3.0
4.5
6.0
mA
[Reference voltage block VREF]
Reference voltage
Load stability
IREF = 1 mA
[Regulator circuit block VREG]
REG output voltage
Load stability
IREG = 10 mA
[Oscillator block]
Frequency
[Protection detection block FAULT]
Off-leak current
On resistance
[Short protection block SCP]
SCP = 0.5 V
[VCOM block]
Input offset voltage
[Low voltage protection circuit]
Detection voltage
[Overall]
Average current consumption
Standby current
○Design guarantee (No total shipment inspection is made.)
*This product is not designed for protection against radio active rays.
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3/17
2009.07 - Rev.B
Technical Note
BD81666EFV
●Reference Data (Unless otherwise specified, Ta = 25℃)
60
6
85℃
25℃
4
-40℃
2
0
50
25℃
4
2
-40℃
0
0
5
10
15
20
0
5
15
25℃
-40℃
30
20
10
0
0
20
10
20
30
40
SUPPLY VOLTAGE : VO2[V]
Fig.2 Standby Circuit Current 2
Fig.3 Standby Circuit Current 3
4
4
2.9
3
2
-40℃
1
85℃
25℃
VREF29 VOLTAGE : VREF29[V]
Fig.1 Standby Circuit Current 1
0
25℃
3
-40℃
2
85℃
1
0
0
5
10
15
20
0
10
Fig.4 Internal Reference
Line Regulation
30
85℃
-0.2
25℃
-0.3
-0.4
-40℃
1
1.5
1.6
100
1.2
10
0.8
0
Fig.7 DC/DC Error Amp Input
Bias Current
5
10
15
0.01
0.001
20
-40℃
30
0
0
0.4
0.8
1.2
1.6
COMP VOLTAGE : VCOMP1[V]
Fig.10 Error Output
Voltage vs Duty
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100
125
0.01
10
1
0.1
0.001
0.1
1
600
SWITCHING FREQUENCY : f[kHz] .
DELAY TIME [ms]
25℃
60
75
Fig.9 Soft Start Capacity vs
Delay Time
Fig.8 DC/DC Error Amp
Feedback Voltage
85℃
50
SS1,2 CAPACITOR [μF]
100
90
25
1
SUPPLY VOLTAGE : VCC[V]
FB VOLTAGE : VFB1,2[V]
120
0
0.1
0.4
2
-25
Fig.6 Internal Reference vs
Temperature
0
-0.5
0.5
2.6
AMBIENT TEMPERATURE : Ta[℃]
DELAY TIME [ms]
FEEDBACK VOLTAGE : VFB1,2[V]
0
0
2.7
2.5
-40
-50
40
Fig.5 Internal Reference
Load Regulation
0.1
-0.1
20
2.8
VREF29 CURRENT : IREF29[mA]
SUPPLY VOLT AGE : VCC[V]
FB INPUT CURRENT : IFB1,2[μA]
10
40
SUPPLY VOLTAGE : VO1 [V]
VREF29 VOLTAGE : VREF29[V]
VREF29 VOLTAGE : VREF29[V]
.
SUPPLY VOLTAGE : VCC [V]
SWITCHING Duty : Duty[%]
85℃
85℃
STANDBY CURRENT : IVO2[µA]
6
CIRCUITCURRENT : IVO1[mA]
CIRCUIT CURRENT : ICC[mA]
.
.
8
0.01
SS3,4 CAPACITOR [μF]
Fig.11 Delay Start
Capacity vs Delay Time
4/17
0.1
550
500
450
400
-50
-25
0
25
50
75
100
AMBIENT TEMPERATURE : Ta [℃]
Fig.12 Switching Frequency vs
Temperature
2009.07 - Rev.B
Technical Note
BD81666EFV
●Reference Data (Unless otherwise specified, Ta = 25℃)
100
1
0.1
0.001
0.01
OUTPUT VOLTAGE : VCOM[V]
INPUT CURRENT : IV+,IV-[uA]
.
10
DELAY TIME [ms]
20
1.6
1.2
0.8
0.4
15
0
5
SCP CAPACITOR [μF]
10
15
20
85℃
10
-40℃
5
0
-300
0
0.1
25℃
25
Fig.13 SCP Capacity
vs Delay Time
-200
-100
0
100
200
300
OUTPUT CURRENT : ICOM[mA]
INPUT VOLTAGE : V+,V- [V]
Fig.15 COM Load Regulation
Fig.14 COM Input Bias Current
OFFSET VOLTAGE : VOFFSET[mV]
1.6
35V
1.2
IG
15V
0.8
3.3V
0.4
Vo2GS
-6V
0
0
5
10
15
20
25
VCOM VOLTAGE : VCOM[V]
Fig.17 Start-up Sequence
100
90
90
80
80
70
70
60
50
40
30
50
40
30
20
10
10
1000
100
60
20
0
100
OUTPUT CURRENT[mA]
Fig.19 Output Current vs
Efficiency (Vo1)
400
1000
80
8
200
400
600
800
1000
ISW[mA]
Fig.22 DC/DC SW On Resistance
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10
12
14
16
Fig.20 Output Current vs
Efficiency (VDD)
Fig.21 Total Efficiency
140
180
120
150
100
80
60
40
18
120
90
60
30
0
0
0
20
SUPPLY VOLTAGE[V]
20
0
40
OUTPUT CURRENT[mA]
Cx VOLTAGE [mV]
Cx VOLTAGE [mV]
.
VSW[mV]
160
60
10000
320
240
80
0
0
100
10000
Fig.18 Gate-shading Waveform
TOTAL EFFICIENCY[%] .
100
EFFICIENCY [%]
EFFICIENCY [%]
.
Fig.16 VCOM Offset Voltage
0
20
40
60
80
100
Cx CURRENT [mA]
Fig.23 Charge Pump N-channel
On Resistance
5/17
0
20
40
60
80
100
Cx CURRENT [mA]
Fig.24 Charge Pump
P-channel On Resistance
2009.07 - Rev.B
Technical Note
BD81666EFV
●Pin Assignment Diagram
●Block Diagram
VDD
29
VCC
35
FAULT
VREG
11
CURRENT
SENSE
VREG
PGND2
PGND1
SW2
SW1
SW2
SW1
BOOT2
BOOT1
PVCC2
PVCC1
VREF29
UVLO
TSD
VREF
31
FAULT
LOGIC
36
D
SLOPE
SOFT
START
34
FB1
SCP
S D
SS2
VCOM
FB4
Vo2
C3
C1L
Vo1
C2L
VGH
VDD
3.3V/2A
2
3
＋
R V
PWM
－
VREG
SLOPE
SW2
1
4
＋
ERR
－
23
COMP2
17
PGND2
FB2
BOOT2
VO1
VO2
7
VGH
VO1
SS3
FB3
POSITIVE
CHARG
PUMP
＋
ERR
－
12
C2L
C1L
VGH
VO2GS
GATE
SHADING
CONTROLLER
26
＋
VCOM
－
15
GSOUT
NEGATIVE
CHARGE
PUMP
－
ERR
＋
25
VCOM
36V/30mA
With G/S
16
14
FB4
FB3
19
18
CPGND
VO2
22
DELAY
START
13
IG
CPGND
PVCC2
SW2
R
SOFT
START
6
FB2
V－
GSOUT
FB1
BOOT1
5
33
V＋
IG
PGND1
40
OCP
COMP1
8
SS3
SW1
SENSE
VCC
FB3
VO1
39
37
SS4
FAULT
V
CURRENT
32
VREF29
GND
R
＋
ERR
－
FB1
COMP1
FB2
S
＋
R
PWM
R
－
VREG
SS1
SS1
COMP2
SW1
38
OSC
VREG
SS2
VIN
15V
PVCC1
OCP
24
VGL
C3
-9V/30mA
FB4
DELAY
START
TIMER
LATCH
VO1
27
V-
28
30
V+
10
SS4
20
21
VREF
9
GND CPGND CPGND
SCP
Fig. 25 Pin Assignment Diagram & Block Diagram
●Pin Assignment and Pin Function
Pin
Pin
Function
No. name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PGND2
SW2
SW2
BOOT2
PVCC2
SS2
COMP2
FB2
SCP
GND
FAULT
FB3
SS3
IG
GSOUT
Vo2GS
Vo2
C1L
C2L
CPGND
Ground pin
Switching pin 2
Switching pin 2
Capacitance connection pin for booting 2
Power supply input pin
Soft start capacitance connection pin 2
Error amp output 2
Feedback input 2
Capacitance connection pin for short protection delay
Ground pin
Protection detection output pin
Feedback input 3
Delay start capacitance connection pin 3
Gate shading input pin
Gate shading sink output pin
Gate shading source output pin
Power supply input pin
Charge pump clock output 1
Charge pump clock output 2
Ground pin
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Pin
No.
Pin
name
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
CPGND
VGH
Vo1
C3
FB4
VCOM
VV+
VCC
SS4
VREF29
FB1
COMP1
SS1
VREG
PVCC1
BOOT1
SW1
SW1
PGND1
Function
Ground pin
Positive charge pump diode connection pin
Power supply input pin
Charge pump clock output 3
Feedback input 3
VCOM output
VCOM negative input pin
VCOM positive input pin
Power supply input pin
Delay start capacitance connection pin 4
Standard voltage output pin
Feedback input 1
Error amp output 1
Soft start capacitance connection pin 1
Regulator output pin for booting
Power supply input pin
Capacitance connection pin for booting 1
Switching pin 1
Switching pin 1
Ground pin
2009.07 - Rev.B
Technical Note
BD81666EFV
●Block Operation
VREG
A block to generate constant-voltage for DC/DC boosting.
VREF
A block that generates internal reference voltage of 2.9 V (Typ.).
TSD/UVLO
TSD (Thermal shutdown)/UVLO (Under Voltage Lockout) protection block. The TSD circuit shuts down IC at 175°C (Typ.)
and recovers at 160°C (Typ.). The UVLO circuit shuts down the IC when the Vcc is 5.1 V (Typ.) or below.
Error amp block (ERR)
This is the circuit to compare the reference voltage of 1.25 V (Typ.) and the feedback voltage of output voltage. The COMP
pin voltage resulting from this comparison determines the switching duty. At the time of startup, since the soft start is
operated by the SS pin voltage, the COMP pin voltage is limited to the SS pin voltage.
Oscillator block (OSC)
This block generates the oscillating frequency.
SLOPE block
This block generates the triangular waveform from the clock created by OSC. Generated triangular waveform is sent to the
PWM comparator.
PWM block
The COMP pin voltage output by the error amp is compared to the SLOPE block's triangular waveform to determine the
switching duty. Since the switching duty is limited by the maximum duty ratio which is determined internally, it does not
become 100%.
DRV block
A DC/DC driver block. A signal from the PWM is input to drive the power FETs.
CURRENT SENSE
Current flowing to the power FET is detected by voltage at the CURRENT SENSE and the overcurrent protection operates
at 3A (Typ.). When the overcurrent protection operates, switching is turned OFF and the SS pin capacitance is discharged.
DELAY START
A start delay circuit for positive/negative charge pump.
Soft start circuit
Since the output voltage rises gradually while restricting the current at the time of startup, it is possible to prevent the
output voltage overshoot or the rush current.
Positive charge pump
A controller circuit for the positive-side charge pump. The switching amplitude is controlled so that the feedback voltage
FB2 will be set to 1.25 V (Typ.).
The start delay time can be set in the DLS pin at the time of startup. When the DLS voltage reaches 0.65 V (Typ.),
switching waves will be output from the CL1 and CL2 pins.
Negative charge pump
A controller circuit for the negative-side charge pump. The switching amplitude is controlled so that the feedback voltage
FB3 will be set to 1.25 V (Typ.).
Gate shading controller
A controller circuit of gate shading. The Vo2GS and GSOUT are turned on and off according to IG pin input.
VCOM
A common amplifier to set output voltage in a range of 0.3 V to Vo1-0.3 V.
Timer latch
An output short protection circuit. If at least one output is down after the DC/DC2 and positive/negative charge pump
outputs all rise, all the outputs will be shut down.
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7/17
2009.07 - Rev.B
Technical Note
BD81666EFV
●Start-up Sequence
The DC/DC converter of this IC incorporates a soft start function, and the charge pump incorporates a delay function, for
which independent time settings are possible through external capacitors. As the capacitance, 0.001 µF to 0.1 µF is
recommended. If the capacitance is set lower than 0.001 µF, the overshooting may occur on the output voltage. If the
capacitance is set larger than 0.1 µF, the excessive back current flow may occur in the internal parasitic elements when the
power is turned OFF and it may damage IC. When the capacitor more than 0.1 µF is used, be sure to insert a diode to VCC in
series, or a bypass diode between the SS and VCC pins.
Bypass diode
Back current prevention diode
VCC
Fig.26 Example of Bypass Diode Use
When there is the activation relation (sequences) with other power supplies, be sure to use the high-precision product (such as X5R).
Soft start time may vary according to the input voltage, output loads, coils, voltage, and output capacitance. Be sure to verify
the operation using the actual product.
A delay of the charge pump starts from a point where Vo1 reaches 80% (Typ.).
Soft start time of DC/DC converter block: tss
Tss = (Css 0.7 V) / 10 μA [s]
Where, Css is an external capacitor.
Delay time of charge pump block: t DELAY
t DELAY = (Css 0.65) / 5 μA [s]
Where, Css is an external capacitor.
Startup example
VCC
(Input)
IG
(Input)
Vo1
DC/DC (output)
VDD
DC/DC (output 2)
Vo2GS
(Gate shooting
output)
80%
DL1
DL2
DL3
VGL
(Negative charge
pump output)
DL1 = SS1 capacitance delay time
DL2 = SS2 capaciance delay time
DL3 = SS3 capacitance delay time
DL4 = SS4 capacitance delay time
DL4
Fig. 27
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8/17
2009.07 - Rev.B
Technical Note
BD81666EFV
●Selecting Application Components
(1) Output LC constant
The inductance L to use for output is decided by the rated current ILR and input current maximum value IOMAX of the
inductance.
Vin
IL
M1 ON
M1 OFF
IL + IL/2 should not reach
the rated value level
M1
IL
ILR
II
ΔIL
Vo
L
IL
M2
ton
D1
M0
D2
Co
T
t
Fig. 28
Fig.29
Adjust so that IL+ΔIL/2 does not reach the rated current value ILR. At this time, IL and ∆IL can be obtained by the
following equation.
IL= (1 +
Vo
Vin
) Io×
1
η
[A]
(η:efficiency)
ΔIL= 1 {Vin×Vo / (Vin + Vo)} × 1 [A]
L
f
Set with sufficient margin because the inductance L value may have the dispersion of ± 30%.
For the capacitor C to use for the output, select the capacitor which has the larger value in the ripple voltage VPP
permissible value and the drop voltage permissible value at the time of sudden load change.
Output ripple voltage is decided by the following equation.
―
ΔIL
Io
)RESR +
( Vin / (Vin + Vo)) ×
ΔVPP =
(IL
2
Co
1
f
Perform setting so that the voltage is within the permissible ripple voltage range.
For the drop voltage VDR during sudden load change, please perform the rough calculation by the following equation.
VDR =
ΔI
Co
× 10µ sec
[V]
However, 10 µs is the rough calculation value of the DC/DC response speed.
Make Co settings so that these two values will be within the limit values.
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9/17
2009.07 - Rev.B
Technical Note
BD81666EFV
(2) Output LC constant
The inductance L to use for output is decided by the rated current ILR and input current maximum value IOMAX of the
inductance.
IOMAX + I L should not
reach the rated value level
IL
VCC
IL
ILR
IOMAX mean current
Vo
L
Co
t
Fig. 28
Fig. 29
Adjust so that IOMAX + ∆IL does not reach the rated current value ILR. At this time, ∆IL can be obtained by the following
equation.
1
Vo
1
∆IL =
(Vcc - Vo)
[A]
L
Vcc
f
Set with sufficient margin because the inductance L value may have the dispersion of ± 30%.
For the capacitor C to use for the output, select the capacitor which has the larger value in the ripple voltage VPP
permissible value and the drop voltage permissible value at the time of sudden load change.
Output ripple voltage is decided by the following equation.
∆IL
Vo
1
∆IL RESR +
∆VPP =
2Co
Vcc
f
[V]
Perform setting so that the voltage is within the permissible ripple voltage range.
For the drop voltage VDR during sudden load change, please perform the rough calculation by the following equation.
∆I
VDR =
10 µs
[V]
Co
However, 10 µs is the rough calculation value of the DC/DC response speed.
Make Co settings so that these two values will be within the limit values.
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10/17
2009.07 - Rev.B
Technical Note
BD81666EFV
(3) Phase compensation
Phase Setting Method
The following conditions are required in order to ensure the stability of the negative feedback circuit.
Phase lag should be 150° or lower during gain 1 (0 dB) (phase margin of 30° or higher).
Because DC/DC converter applications are sampled using the switching frequency, the overall GBW should be set to
1/10 the switching frequency or lower. The target application characteristics can be summarized as follows:
Phase lag should be 150° or lower during gain 1 (0 dB) (phase margin of 30° or higher).
The GBW at that time (i.e., the frequency of a 0-dB gain) is 1/10 of the switching frequency or below.
In other words, because the response is determined by the GBW limitation, it is necessary to use higher switching
frequencies to raise response.
One way to maintain stability through phase compensation involves canceling the secondary phase lag (-180°) caused
by LC resonance with a secondary phase advance (by inserting 2 phase advances).
The GBW (i.e., the frequency with the gain set to 1) is determined by the phase compensation capacitance connected to
the error amp. Increase the capacitance if a GBW reduction is required.
(a) Standard integrator (low-pass filter)
(b) Open loop characteristics of integrator
A
＋
COMP
A
Feedback R
(a)
-20 dB/decade
Gain
[dB]
GBW(b)
0
－
FB
F
0
C
-90°
Phase
-90
[°]
Phase margin
-180°
-180
F
Fig. 30
Point (a)
fa =
1
2πRCA
Fig. 31
[Hz]
Point (b)
fb = GBW =
1
2πRC
[Hz]
The error amp performs phase compensation of types (a) and (b), making it act as a low-pass filter.
For DC/DC converter applications, R refers to feedback resistors connected in parallel.
From the LC resonance of output, the number of phase advances to be inserted is two.
LC resonant frequency fp =
Vo
R1
C1
R2
－
[Hz]
C2
R3
＋
1
2π√LC
A
CO MP
Phase advance
fz1 =
1
2πC1R1
[Hz]
Phase advance
fz2 =
1
2πC2R3
[Hz]
Fig. 32
Set a phase advancing frequency close to the LC resonant frequency for the purpose of canceling the LC resonance.
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11/17
2009.07 - Rev.B
Technical Note
BD81666EFV
(4) Short protection of timer latch type
If the overcurrent protection function operates after all the outputs are stable, all the outputs will be shut down by the
latch function.
The latch timing is determined by the capacitance connected to the SCP pin. As the capacitance, 0.001 µF to 0.1 µF is
recommended. A startup failure may result if the capacitance is 0.001 µF or below. The internal elements may be
damaged because an overcurrent state will continue if the capacitance is 1 µF or above.
・t scp = (Cscp 0.6 V) / 5 µA [s]
・Where, Css is an external capacitor.
(5) Fault function
This IC incorporates a fault function to tell the operating situation of the protection circuit.
If the protection circuit turns on, the fault pin will be pulled up by external pull-up resistance, and high-level voltage will
be output.
In a stable operation state, the output will be low-level voltage. As the resistance value, 10 kΩ to 220 kΩ is
recommended. Offset voltage due to the internal on resistance will be generated if the resistance is set to 10 Ω or below.
In that case, no low-level voltage may be output correctly. No high-level voltage may be output correctly if the resistance
is 220 kΩ or over by leak current.
The following conditions will set the fault pin to high level.
・If UVLO operates
・If TSD operates
・If OCP operates
・If SCP operates
(6) Common amp
VCOM operates in a range between 0.3 V and V01-0.3 V. Usually, use the buffer type shown in (a).
To improve the current drive capability, use PNP and NPN transistors as shown in (b).
Use the buffer type specified in (a) if the VCOM is not used, and ground the V+ pin. A resistance setting range of 10 kΩ
to 100 kΩ is recommended for R3 and R4. If the resistance is set to 10 kΩ or below, the current consumption will
increase and the efficiency of power will be degraded. If the resistance is 100 kΩ or above, the input bias current will be
0.1 µA (Typ.) and the offset voltage may become great.
(a)
(b)
Vo1
V01
R3
+
VCOM
V+
+
VCOM
-
30kΩ
V+
30kΩ
V-
R3
R4
-
V-
-
VCOM
R4
Vo1
1000uF
VCOM
R5
1kΩ
VCOM =
R4
R3 + R4
Vo1 [V] The recommended R5 value is approximately 1 kΩ.
Fig. 33
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Fig. 34
12/17
2009.07 - Rev.B
Technical Note
BD81666EFV
(7) Design of Feedback Resistance constant
Set the feedback resistance as shown below.
Reference voltage
1.25 V
Vo1
VDD
R1
Vo1, VDD =
＋
R1 + R2
R2
1.25
[V]
ERR
FB1
FB2
R2
－
Fig. 35
(8) Positive-side Charge Pump Settings
The IC incorporates a charge pump controller, thus making it possible to generate stable gate voltage.
The output voltage is determined by the following equation. As the setting range, 10 kΩ to 330 kΩ is recommended. If
the resistor is set lower than 10 kΩ, it causes reduction of power efficiency. If it is set more than 330 kΩ, the offset
voltage becomes larger by the input bias current of 0.4 µA (Typ.) in the internal error amp.
Reference voltage
1.25 V
Vo2
C6
1000 pF to
4700 pF
R6
＋
ERR
2
R7
FB3
R6 + R7
R7
Vo2 =
－
1.25
[V]
Fig. 36
In order to prevent output voltage overshooting, insert capacitor C6 in parallel with R6.
As the capacitance, 1,000 pF to 4,700 pF is recommended. If the capacitance is not within the range, output voltage
oscillation may result. By connecting capacitance to the SS3 pin, the rising delay time can be set for the positive-side
charge pump output. The delay time is determined by the following equation. If a capacitance outside this range is
inserted, output voltage oscillation may result.
・Delay time of charge pump block t DELAY
t DELAY = (CDLS 0.65) / 5 µA [s]
Where, CDLS is an external capacitor.
(9) Negative-side Charge Pump Settings
BD8166EFV incorporates a charge pump controller for negative voltage, thus making it possible to generate stable gate voltage.
The output voltage is determined by the following equation. As the setting range, 10 kΩ to 330 kΩ is recommended.
If the resistor is set lower than 10 kΩ, it causes reduction of power efficiency. If it is set more than 330kΩ, the offset
voltage becomes larger by the input bias current of 0.4 µA (Typ.) in the internal error amp.
Vo3
C8
1000 pF to
4700 pF
1.25 V
R8
－
ERR
＋
R9
Vo3 =
-
R8
R9
1.65 + 1.25 V
[V]
FB4
VREF29
2.9 V
Fig.37
Like the positive-side charge pump, the rise delay time can be set by connecting capacitance to the SS4 pin.
In order to prevent output voltage overshooting, insert capacitor C6 in parallel with R6. As the capacitance, 1,000 pF to
4,700 pF is recommended. If a capacitor outside this range is inserted, the output voltage may oscillate.
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13/17
2009.07 - Rev.B
Technical Note
BD81666EFV
●Gate Shading Setting Method
The IG input signal allows the high-level and low-level control of the positive-side gate voltage. The slope of output can be
set by the external RC. The recommended resistance set value is 200 Ω to 5.1 kΩ and the recommended capacitor set
value is 0.001 µF to 0.1 µF. The aggravation of efficiency may be caused if settings outside this range are made.
Determine ∆V by referring to the following value. The following calculation equation is used for ∆V.
tW
∆V = Vo2GS (1 - exp ()) [V]
CR
TIMING STANDARD VALUE
tWL
LIMIT
H
tWH
PARAMETER
L
UNIT
SYMBOL
IG “ L ” Time
tWL
IG “ H ”
tWH
MIN
TYP
MAX
1
2
—
μs
1
18
—
μs
CONDITION
tLH
H
Time
Vo2GS“H” to “L”
10
∆V
Voltage difference
Vo2GS
Vo2GS“L” to “H”
tLH
R = 500 *
μs
0.1
Time
tWL = 2 us
V
V = 10 V*
From positive-side charge
ΔV
pump
Vo2
L
Gate
Vo2GS
Gate driver
Shading
Fig.38 Gate Shading Timing Chart
R
Control
C
GSOUT
IC
●I/O Equivalent Circuit Diagram
2. SW2 3. SW2 38. SW1 39. SW1
Vcc
4. BOOT2 37. BOOT1
Fig. 39
6. SS2 9. SCP 34. SS1
PVcc
REG
10k
50Ω
SW
7. COMP2 33. COMP1
8. FB2 12. FB3 25. FB4
Vcc
VR
32. FB1
11. FOULT
VREF29
1kΩ
20Ω
10kΩ
13. SS3 30. SS4
14. IG
15. GSOUT
Vo2
VREF29
20Ω
16. Vo2GS
18. C1L 19. C2L 24. C3
Vo2
26. COM
27. VVcc
22. VGH
Vo1
Vo2
28. V+
35. VREG
Vcc
Vcc
PVcc
BOOT
Fig. 40
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14/17
2009.07 - Rev.B
Technical Note
BD81666EFV
●Notes for use
1) Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may
result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such
damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special
mode where the absolute maximum ratings may be exceeded is anticipated.
2) GND potential
Ensure a minimum GND pin potential in all operating conditions.
3) Setting of heat
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
4) Pin short and mistake fitting
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in
damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by the
presence of a foreign object may result in damage to the IC.
5) Actions in strong magnetic field
Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction.
6) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure,
and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process.
7) Ground wiring patterns
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,
placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage
variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the
GND wiring patterns of any external components.
8) Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of
parasitic elements.
For example, when the resistors and transistors are connected to the pins as shown in Fig. 41, a parasitic diode or a
transistor operates by inverting the pin voltage and GND voltage.
The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result
of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC
malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will
trigger the operation of parasitic elements such as by the application of voltages lower than the GND (P substrate) voltage
to input and output pins.
Resistor
Transistor (NPN)
B
～
～
(Pin B)
E
B
～
～
C
(Pin B)
～
～
(Pin A)
GND
N
N
N
N
Parasitic
elements
P+
N
(Pin A)
P substrate
Parasitic elements
GND
P
P+
～
～
P+
N
P
GND
N
P
P+
Parasitic elements
C
E
Parasitic
elements
GND
GND
Fig. 41 Example of a Simple Monolithic IC Architecture
9) Overcurrent protection circuits
An overcurrent protection circuit designed according to the output current is incorporated for the prevention of IC damage
that may result in the event of load shorting. This protection circuit is effective in preventing damage due to sudden and
unexpected accidents. However, the IC should not be used in applications characterized by the continuous operation or
transitioning of the protection circuits. At the time of thermal designing, keep in mind that the current capacity has negative
characteristics to temperatures.
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15/17
2009.07 - Rev.B
Technical Note
BD81666EFV
10) Thermal shutdown circuit (TSD)
This IC incorporates a built-in TSD circuit for the protection from thermal destruction. The IC should be used within the
specified power dissipation range. However, in the event that the IC continues to be operated in excess of its power
dissipation limits, the attendant rise in the chip's junction temperature Tj will trigger the TSD circuit to turn off all output
power elements. The circuit automatically resets once the junction temperature Tj drops.
Operation of the TSD circuit presumes that the IC's absolute maximum ratings have been exceeded. Application designs
should never make use of the TSD circuit.
11) Testing on application boards
At the time of inspection of the installation boards, when the capacitor is connected to the pin with low impedance, be sure
to discharge electricity per process because it may load stresses to the IC. Always turn the IC's power supply off before
connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as
an antistatic measure, and use similar caution when transporting or storing the IC.
POWER DISSIPATION: PD [mW]
●Power Dissipation
On 70 70 1.6 mm glass epoxy PCB
5000
4000
300
200
(1) 1-layer board (Backside copper foil area 0 mm 0 mm)
(2) 2-layer board (Backside copper foil area 15 mm 15 mm)
(3) 2-layer board (Backside copper foil area 70 mm 70 mm)
(4) 4-layer board (Backside copper foil area 70 mm 70 mm)
(4)
(3)
(2)
(1)
100
0
2
5
75 85
100
125
150
AMBIENT TEMPERATURE: Ta [°C]
Fig. 42
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16/17
2009.07 - Rev.B
Technical Note
BD81666EFV
●Ordering part number
B
D
8
Part No.
1
6
6
Part No.
E
F
V
-
Package
HTSSOP-B40
E
2
Packaging and forming specification
E2: Embossed tape and reel
HTSSOP-B40
<Tape and Reel information>
13.6±0.1
(MAX 13.95 include BURR)
4 +6
−4
(8.4)
1
Embossed carrier tape (with dry pack)
Quantity
2000pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
20
1PIN MARK
1.0Max.
0.625
1.2 ± 0.2
(3.2)
0.5 ± 0.15
21
5.4±0.1
7.8±0.2
40
Tape
+0.05
0.17 −0.03
0.85±0.05
0.08±0.05
S
+0.05
0.24 −0.04
0.65
0.08
M
0.08 S
1pin
(Unit : mm)
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Reel
17/17
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2009.07 - Rev.B
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller,
fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of
any of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
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More detail product informations and catalogs are available, please contact us.
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