Internally Trimmed Integrated Circuit Multiplier AD532 FEATURES FUNCTIONAL BLOCK DIAGRAM Pretrimmed to ±1.0% (AD532K) No external components required Guaranteed ±1.0% maximum 4-quadrant error (AD532K) Differential Inputs for (X1 − X2) (Y1 − Y2)/10 V transfer function Monolithic construction, low cost VX R VY FLEXIBILITY OF OPERATION The AD532 multiplies in four quadrants with a transfer function of (X1 − X2)(Y1 − Y2)/10 V, divides in two quadrants with a 10 V Z/(X1 − X2) transfer function, and square roots in one quadrant with a transfer function of ±√10 V Z. In addition to these basic functions, the differential X and Y inputs provide significant operating flexibility both for algebraic computation and transducer instrumentation applications. Transfer functions, such as XY/10 V, (X2 − Y2)/10 V, ±X2/10 V, and 10 V Z/(X1 − X2), are easily attained and are extremely useful in many modulation and function generation applications, as well as in trigonometric calculations for airborne navigation and guidance applications, where the monolithic construction and small size of the AD532 offer considerable system advantages. In addition, the high CMRR (75 dB) of the differential inputs makes the AD532 especially R Z Y1 OUTPUT Y2 10R R (WITH Z TIED TO OUTPUT) 00502-003 VOS (X1 – X2) (Y1 – Y2) VOUT = 10V Multiplication, division, squaring, square rooting Algebraic computation Power measurements Instrumentation applications Available in chip form The AD532 is the first pretrimmed single chip monolithic multiplier/divider. It guarantees a maximum multiplying error of ±1.0% and a ±10 V output voltage without the need for any external trimming resistors or output op amp. Because the AD532 is internally trimmed, its simplicity of use provides design engineers with an attractive alternative to modular multipliers, and its monolithic construction provides significant advantages in size, reliability and economy. Further, the AD532 can be used as a direct replacement for other IC multipliers that require external trim networks. X2 X APPLICATIONS GENERAL DESCRIPTION X1 Figure 1. well qualified for instrumentation applications, as it can provide an output signal that is the product of two transducer generated input signals. GUARANTEED PERFORMANCE OVER TEMPERATURE The AD532J and AD532K are specified for maximum multiplying errors of ±2% and ±1% of full scale, respectively at 25°C, and are rated for operation from 0°C to 70°C. The AD532S has a maximum multiplying error of ±1% of full scale at 25°C; it is also 100% tested to guarantee a maximum error of ±4% at the extended operating temperature limits of −55°C and +125°C. All devices are available in either the hermetically-sealed TO100 metal can, TO-116 ceramic DIP or LCC packages. The J, K, and S grade chips are also available. ADVANTAGES OF ON-THE-CHIP TRIMMING OF THE MONOLITHIC AD532 1. 2. 3. 4. 5. True ratiometric trim for improved power supply rejection. Reduced power requirements since no networks across supplies are required. More reliable because standard monolithic assembly techniques can be used rather than more complex hybrid approaches. High impedance X and Y inputs with negligible circuit loading. Differential X and Y inputs for noise rejection and additional computational flexibility. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 ©2001–2011 Analog Devices, Inc. All rights reserved. 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AD532 TABLE OF CONTENTS Features .............................................................................................. 1 Functional Description .................................................................. 10 Applications ....................................................................................... 1 AD532 Performance Characteristics ........................................... 11 Functional Block Diagram .............................................................. 1 Nonlinearity ................................................................................ 11 General Description ......................................................................... 1 AC Feedthrough ......................................................................... 11 Flexibility of Operation................................................................ 1 Common-Mode Rejection ........................................................ 11 Guaranteed Performance Over Temperature ........................... 1 Dynamic Characteristics ........................................................... 11 Advantages of On-The-Chip Trimming of The Monolithic AD532 ............................................................................................ 1 Power Supply Considerations ................................................... 11 Revision History ............................................................................... 2 Applications..................................................................................... 12 Specifications..................................................................................... 3 Replacing Other IC Multipliers ................................................ 12 Thermal Resistance .......................................................................... 5 Square Root ................................................................................. 13 Chip Dimensions And Bonding Diagram ................................ 5 Difference of Squares ................................................................. 13 ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 14 Pin Configuration and Function Descriptions ............................. 6 Ordering Guide .......................................................................... 15 Noise Characteristics ................................................................. 11 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 2/11—Rev. C to Rev. D Updated Format .................................................................. Universal Added Pin Configuration and Function Descriptions Section ................................................................................................ 6 Added Typical Performance Characteristics Section .................. 8 Changes to Figure 11 ........................................................................ 8 Changes to Figure 12 and Figure 13............................................... 9 Changes to Ordering Guide .......................................................... 15 Rev. D | Page 2 of 16 AD532 SPECIFICATIONS At 25°C, VS = ±15 V, R ≥ 2 kΩ VOS grounded, unless otherwise noted. Table 1. Model MULTIPLIER PERFORMANCE Transfer Function Total Error TA = Minimum to Maximum Total Error vs. Temperature Supply Rejection Nonlinearity, X Nonlinearity, Y Feedthrough, X Feedthrough, Y (X Nulled, Y = 20 V p-p 50 Hz) Feedthrough vs. Temperature Feedthrough vs. Power Supply DYNAMICS Small Signal BW 1% Amplitude Error Slew Rate Settling Time NOISE Conditions Min CMRR Input Bias Current X, Y Inputs X, Y Inputs TMIN to TMAX Z Input Z Input TMIN to TMAX Offset Current Differential Resistance DIVIDER PERFORMANCE Transfer Function Total Error ( X1 − X 2 ) (Y1 − Y2 ) 10V ±15 V ±10% X = 20 V p-p, Y = 10 V Y = 20 V p-p, X = 10 V Y nulled, X = 20 V p-p 50 Hz VOUT = 0.1 rms VOUT 20 p-p to 2%, ΔVOUT = 20 V ±10 f ≤ 1 kHz Differential or CM operating differential ±1.5 ±2.5 ±0.04 ±0.05 ± 0.8 ±0.3 50 ±2.0 30 Min AD532S Typ Max Unit ( X1 − X 2 ) (Y1 − Y2 ) 10V ±1.0 ±0.5 200 ±0.7 ±1.5 ±0.03 ±0.05 ±0.5 ±0.2 30 100 ±0.01 ±0.05 ±0.5 ±0.2 30 150 25 80 25 ±1.0 ±4.0 ±0.04 100 % % %/°C %/% % % mV 80 mV 2.0 ±0.25 1.0 ±0.25 1.0 ±0.25 mV p-p/°C mV/% 1 75 45 1 1 75 45 1 1 75 45 1 MHz kHz V/μs μs 0.6 0.6 0.6 mV (rms) 3.0 3.0 3.0 mV (rms) ±13 1 ±13 1 ±40 0.7 ±2.5 ±10 ±13 1 ±10 0.7 ±2.5 ±2.5 V Ω mV mV/°C mV/% ±10 ±10 V ±30 ±10 40 50 3 10 ±10 ±30 ±0.3 10 VX = −10 V, −10 V ≤ VZ ≤ +10 V VX = −1 V, −10 V ≤ VZ ≤ +10 V AD532K Typ Max 10V –10 V ≤ X, Y ≤ +10 V Xl > X2 Min ( X1 − X 2 ) (Y1 − Y2 ) Wideband Noise f = 5 Hz to 10 kHz f = 5 Hz to 5 MHz OUTPUT Voltage Swing Impedance Offset Voltage Offset Voltage vs. Temperature Offset Voltage vs. Supply INPUT AMPLIFIERS (X, Y, and Z) Signal Voltage Range AD532J Typ Max 10 V Z/(X1 − X2) ±30 2.0 50 1.5 8 ±5 ±25 ±0.1 10 4 ±15 10 V Z/(X1 − X2) dB 1.5 8 ±5 ±25 ±0.1 10 4 ±15 μA μA μA μA μA MΩ 10 V Z/(X1 − X2) ±2 ±1 ±1 % ±4 ±3 ±3 % Rev. D | Page 3 of 16 AD532 Model SQUARE PERFORMANCE Conditions Min Min Min AD532S Typ Max ( X1 − X 2 ) ( X1 − X 2 ) 10V 10V 10V ±0.8 ±0.4 2 −√10 V Z ±1.5 0 V ≤ VZ ≤ 10 V AD532K Typ Max ( X1 − X 2 ) 2 Transfer Function Total Error SQUARE ROOTER PERFORMANCE Transfer Function Total Error POWER SUPPLY SPECIFICATIONS Supply Voltage Rated Performance Operating Supply Current Quiescent AD532J Typ Max 6 Rev. D | Page 4 of 16 ±10 % ±15 ±18 4 % −√10 V Z ±1.0 ±15 ±18 4 ±0.4 −√10 V Z ±1.0 ±15 ±10 Unit 2 6 ±10 4 ±22 V V 6 mA AD532 THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. CHIP DIMENSIONS AND BONDING DIAGRAM Table 2. Thermal Resistance Dimensions are shown in inches and (mm). θJA 150 85 85 θJC 25 22 22 Unit °C/W °C/W °C/W 0.107 (2.718) –VS OUTPUT Z X1 0.062 (1.575) +VS Y1 X2 GND Figure 2. ESD CAUTION Rev. D | Page 5 of 16 VOS Y2 00502-002 Package Type H-10A E-20A D-14 Contact factory for latest dimensions. AD532 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Y2 VOS Y1 +VS GND AD532 TOP VIEW (Not to Scale) X2 X1 OUT 00502-103 Z –VS Z NC +VS 3 2 1 20 19 Y1 OUT Figure 3. 10-Lead Header Pin Configuration (H-10) –VS 4 18 Y2 NC 5 NC 7 17 NC AD532 16 VOS TOP VIEW (Not to Scale) 15 NC NC 8 X2 X1 NC 10 11 12 13 NC 9 NC 14 GND 00502-104 NC 6 NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Figure 4. 20-Lead Leadless Chip Carrier Pin Configuration (E-20A) Z 1 14 +VS OUT 2 NC 4 NC 5 13 Y1 AD532 12 Y2 TOP VIEW 11 VOS (Not to Scale) 10 GND NC 6 9 X2 X1 7 8 NC NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 00502-105 –VS 3 Figure 5. 14-Lead Side Braize DIP (D-14) Table 3. 10 Lead Header Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic Y1 +VS Z OUT −VS X1 X2 GND VOS Y2 Description Y Multiplicand Input 1 Positive Supply Voltage Dual Purpose Input Product Output Negative Supply Voltage X Multiplicand Input 1 X Multiplicand Input 2 Common Output Offset Adjust Y Multiplicand Input 2 Rev. D | Page 6 of 16 AD532 Table 4. 20 Lead Leadless Chip Carrier Pin Function Descriptions Pin No. 2 3 4 1, 5, 6, 7, 8, 9, 11, 12, 15, 17 10 13 14 16 18 19 20 Mnemonic Z OUT −VS NC Description Dual Purpose Input Product Output Negative Supply Voltage No Connection X1 X2 GND VOS Y2 Y1 +VS X Multiplicand Input 1 X Multiplicand Input 2 Common Output Offset Adjust Y Multiplicand Input 2 Y Multiplicand Input 1 Positive Supply Voltage Table 5. 14 Lead Side Braize DIP Pin Function Descriptions Pin No. 1 2 3 4, 5, 6 7 9 10 11 12 13 14 Mnemonic Z OUT −VS NC X1 X2 GND VOS Y2 Y1 +VS Description Dual Purpose Input Product Output Negative Supply Voltage No Connection X Multiplicand Input 1 X Multiplicand Input 2 Common Output Offset Adjust Y Multiplicand Input 2 Y Multiplicand Input 1 Positive Supply Voltage Rev. D | Page 7 of 16 AD532 TYPICAL PERFORMANCE CHARACTERISTICS 70 1 60 Y COMMON-MODE REJ (X1 – X2) = +10V CMRR (dB) XIN YIN 0.1 40 X COMMON-MODE REJ (Y1 – Y2) = +10V 30 20 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PEAK SIGNAL AMPLITUDE (V) 00502-005 0 100 0.01 100k 1M 10M Figure 9. CMRR vs. Frequency 1 20V p-p SIGNAL AMPLITUDE (V) RL = 2kΩ, CL = 1000pF 10 DISTORTION (%) 10k FREQUENCY (Hz) Figure 6. Distortion vs. Peak Signal Amplitude 100 1k 00502-008 10 0.1 RL = 2kΩ, CL = 0pF 1 XIN 0.01 10k 100 1k 10k 100k 1M FREQUENCY (Hz) 00502-006 0.1 10 100k 1M Figure 10. Frequency Response, Multiplying Figure 7. Distortion vs. Frequency 10 VZ = 0.1 × VX sin ωT 1k AMPLITUDE (V) Y FEEDTHROUGH 100 X FEEDTHROUGH 10 10M FREQUENCY (Hz) 00502-009 YIN 1 VX = 10V VX = 1V 1k 10k 100k 1M FREQUENCY (Hz) 10M 0.1 10k 100k 1M FREQUENCY (Hz) Figure 11. Frequency Response, Dividing Figure 8. Feedthrough vs. Frequency Rev. D | Page 8 of 16 10M 00502-010 VX = 5V 1 100 00502-007 FEEDTHROUGH (mV) DISTORTION (%) 50 14 5 12 4 SPOT NOISE (µV/ Hz) SATURATED OUTPUT SWING 10 MAX X OR Y INPUT FOR 1% LINEARITY 8 2 12 14 16 18 POWER SUPPLY VOLTAGE (V) 20 22 0 10 100 1k 10k FREQUENCY (Hz) Figure 13. Spot Noise vs. Frequency Figure 12. Signal Swing vs. Supply Rev. D | Page 9 of 16 100k 00502-012 4 10 3 1 6 00502-011 PEAK SIGNAL VOLTAGE (±V) AD532 AD532 FUNCTIONAL DESCRIPTION zero during production. The product of the two inputs is resolved in the multiplier cell using Gilbert’s linearized transconductance technique. The cell is laser trimmed to obtain VOUT = (X1 − X2)(Y1 − Y2)/10 volts. The built-in op amp is used to obtain low output impedance and make possible self-contained operation. The residual output voltage offset can be zeroed at VOS in critical applications. Otherwise, the VOS pin should be grounded. The functional block diagram for the AD532 is shown in Figure 1and the complete schematic in Figure 14. In the multiplying and squaring modes, Z is connected to the output to close the feedback around the output op amp. In the divide mode, it is used as an input terminal. The X and Y inputs are fed to high impedance differential amplifiers featuring low distortion and good common-mode rejection. The amplifier voltage offsets are actively laser trimmed to X2 +VS R6 R2 R8 R16 R23 R27 Z C1 Q2 Q1 Q7 Q8 Q14 Q15 X1 Q25 R22 R9 R1 R33 Q21 R20 R34 Y1 Q16 Q17 Q3 VOS Q10 Q9 R13 Q4 R21 Q22 Q26 R3 R31 R30 R28 COM Q6 R29 Q12 Q11 Q24 R32 R19 R11 R14 R4 Y2 R5 Q28 R12 Q27 Q20 Q19 Q13 R15 R24 R25 R26 –VS CAN R18 Figure 14. Schematic Diagram Rev. D | Page 10 of 16 00502-004 Q5 OUTPUT Q23 Q18 R10 AD532 AD532 PERFORMANCE CHARACTERISTICS Multiplication accuracy is defined in terms of total error at 25°C with the rated power supply. The value specified is in percent of full scale and includes XIN and YIN nonlinearities, feedback and scale factor error. To this must be added such applicationdependent error terms as power supply rejection, commonmode rejection and temperature coefficients (although worst case error over temperature is specified for the AD532S). Total expected error is the rms sum of the individual components because they are uncorrelated. Accuracy in the divide mode is only a little more complex. To achieve division, the multiplier cell must be connected in the feedback of the output op amp as shown in Figure 17. In this configuration, the multiplier cell varies the closed loop gain of the op amp in an inverse relationship to the denominator voltage. Therefore, as the denominator is reduced, output offset, bandwidth, and other multiplier cell errors are adversely affected. The divide error and drift are then εm × 10 V/X1 − X2) where εm represents multiplier full-scale error and drift, and (X1 − X2) is the absolute value of the denominator. NONLINEARITY Nonlinearity is easily measured in percent harmonic distortion. The curves of Figure 6 and Figure 7 characterize output distortion as a function of input signal level and frequency respectively, with one input held at plus or minus 10 V dc. In Figure 7, the sine wave amplitude is 20 V (p-p). AC FEEDTHROUGH AC feedthrough is a measure of the multiplier’s zero suppression. With one input at zero, the multiplier output should be zero regardless of the signal applied to the other input. Feedthrough as a function of frequency for the AD532 is shown in Figure 8. It is measured for the condition VX = 0, VY = 20 V (p-p) and VY = 0, VX = 20 V (p-p) over the given frequency range. It consists primarily of the second harmonic and is measured in millivolts peak-to-peak. COMMON-MODE REJECTION The AD532 features differential X and Y inputs to enhance its flexibility as a computational multiplier/divider. Common-mode rejection for both inputs as a function of frequency is shown in Figure 9. It is measured with X1 = X2 = 20 V (p-p), (Y1 − Y2) = 10 V dc and Y1 = Y2 = 20 V (p-p), (X1 − X2) = 10 V dc. DYNAMIC CHARACTERISTICS The closed loop frequency response of the AD532 in the multiplier mode typically exhibits a 3 dB bandwidth of 1 MHz and rolls off at 6 dB/octave, thereafter. Response through all inputs is essentially the same as shown in Figure 10. In the divide mode, the closed loop frequency response is a function of the absolute value of the denominator voltage as shown in Figure 11. Stable operation is maintained with capacitive loads to 1000 pF in all modes, except the square root for which 50 pF is a safe upper limit. Higher capacitive loads can be driven if a 100 Ω resistor is connected in series with the output for isolation. POWER SUPPLY CONSIDERATIONS Although the AD532 is tested and specified with ±15 V dc supplies, it may be operated at any supply voltage from ±10 V to ±18 V for the J and K versions, and ±10 V to ±22 V for the S version. The input and output signals must be reduced proportionately to prevent saturation; however, with supply voltages below ±15 V, as shown in Figure 12. Because power supply sensitivity is not dependent on external null networks as in other conventionally nulled multipliers, the power supply rejection ratios are improved from 3 to 40 times in the AD532. NOISE CHARACTERISTICS All AD532s are screened on a sampling basis to assure that output noise will have no appreciable effect on accuracy. Typical spot noise vs. frequency is shown in Figure 13. Rev. D | Page 11 of 16 AD532 APPLICATIONS X1 X2 Z AD532 VIN X1 X2 Z VOUT OUT VOS VOUT = (OPTIONAL) (X1 – X2) (Y1 – Y2) 10V 20kΩ +VS –VS 00502-013 AD532 Y1 Y2 Figure 15. Multiplier Connection For operation as a multiplier, the AD532 should be connected as shown in Figure 15. The inputs can be fed differentially to the X and Y inputs, or single-ended by simply grounding the unused input. Connect the inputs according to the desired polarity in the output. The Z terminal is tied to the output to close the feedback loop around the op amp (see Figure 1). The offset adjust VOS is optional and is adjusted when both inputs are zero volts to obtain zero out, or to buck out other system offsets. VIN2 10V –VS Figure 16. Squarer Connection The squaring circuit in Figure 16 is a simple variation of the multiplier. The differential input capability of the AD532, however, can be used to obtain a positive or negative output response to the input, a useful feature for control applications, as it might eliminate the need for an additional inverter somewhere else. Division Z X1 X2 X Z AD532 Y1 Y2 +VS VOUT = 10VZ X OUT VOUT –VS 1kΩ (SF) 2.2kΩ 47kΩ 10kΩ 20kΩ (X0) REPLACING OTHER IC MULTIPLIERS Multiplication VOUT = (OPTIONAL) 20kΩ +VS Finally, provision for fine trimming the output voltage offset has been included. This connection is optional, however, as the AD532 has been factory-trimmed for total performance as described in the listed specifications. Existing designs using IC multipliers that require external trimming networks can be simplified using the pin-for-pin replaceability of the AD532 by merely grounding the X2, Y2 and VOS terminals. The VOS terminal should always be grounded when unused. VOUT OUT Y1 Y2 +VS VOS –VS 00502-014 First and foremost, trimming on the chip eliminates the need for a hybrid substrate and the additional bonding wires that are required between the resistors and the multiplier chip. By trimming more appropriate resistors on the AD532 chip itself, the second input terminals that were once committed to external trimming networks have been freed to allow fully differential operation at both the X and Y inputs. Further, the requirement for an input attenuator to adjust the gain at the Y input has been eliminated, letting the user take full advantage of the high input impedance properties of the input differential amplifiers. Therefore, the AD532 offers greater flexibility for both algebraic computation and transducer instrumentation applications. Squaring +VS –VS 00502-015 The performance and ease of use of the AD532 is achieved through the laser trimming of thin-film resistors deposited directly on the monolithic chip. This trimming-on-the-chip technique provides a number of significant advantages in terms of cost, reliability and flexibility over conventional in-package trimming of off-the-chip resistors mounted or deposited on a hybrid substrate. Figure 17. Divider Connection The AD532 can be configured as a two-quadrant divider by connecting the multiplier cell in the feedback loop of the op amp and using the Z terminal as a signal input, as shown in Figure 17. It should be noted, however, that the output error is given approximately by 10 V εm/(X1 − X2), where εm is the total error specification for the multiply mode; and bandwidth by fm × (X1 − X2)/10 V, where fm is the bandwidth of the multiplier. Further, to avoid positive feedback, the X input is restricted to negative values. Thus, for single-ended negative inputs (0 V to −10 V), connect the input to X and the offset null to X2; for single-ended positive inputs (0 V to +10 V), connect the input to X2 and the offset null to X1. For optimum performance, gain (S.F.) and offset (X0) adjustments are recommended as shown and explained in Table 6. For practical reasons, the useful range in denominator input is approximately 500 mV ≤ |(X1 − X2)| ≤ 10 V. The voltage offset adjust (VOS), if used, is trimmed with Z at zero and (X1 − X2) at full scale. Rev. D | Page 12 of 16 AD532 Adjust Scale Factor X0 (Offset) With: X −10 V −1 V Divider Adjust for: Z VOUT +10 V −10 V +0.1 V −1 V Square Rooter With: Adjust: for: Z VOUT +10 V −10 V +0.1 V −1 V obtain −1.0 V dc in the output, VOUT = −√10 V Z. For optimum performance, gain (S.F.) and offset (X0) adjustments are recommended as shown and explained in Table 6. DIFFERENCE OF SQUARES Repeat if required. SQUARE ROOT Y Z 20kΩ 20kΩ Z AD532 Z AD532 Y1 Y2 +VS VOUT = 10VZ +VS OUT VOUT 1kΩ (SF) +VS –VS 00502-016 10kΩ 20kΩ (X0) VOUT = X2 – Y2 10V (OPTIONAL) –VS Figure 19. Differential of Squares Connection –VS 47kΩ 20kΩ AD741KH VOUT OUT Y1 Y2 +VS VOS –VS –Y 10kΩ X1 X2 2.2kΩ X1 X2 X 00502-017 Table 6. Adjustment Procedure (Divider or Square Rooter) Figure 18. Square Rooter Connection The connections for square root mode are shown in Figure 18. Similar to the divide mode, the multiplier cell is connected in the feedback of the op amp by connecting the output back to both the X and Y inputs. The diode D1 is connected as shown to prevent latch-up as ZIN approaches 0 volts. In this case, the VOS adjustment is made with ZIN = +0.1 V dc, adjusting VOS to The differential input capability of the AD532 allows for the algebraic solution of several interesting functions, such as the difference of squares, X2 − Y2/10 V. As shown in Figure 19, the AD532 is configured in the square mode, with a simple unity gain inverter connected between one of the signal inputs (Y) and one of the inverting input terminals (−YIN) of the multiplier. The inverter should use precision (0.1%) resistors or be otherwise trimmed for unity gain for best accuracy. Rev. D | Page 13 of 16 AD532 OUTLINE DIMENSIONS 0.005 (0.13) MIN 0.080 (2.03) MAX 8 14 1 PIN 1 0.200 (5.08) MAX 7 0.310 (7.87) 0.220 (5.59) 0.100 (2.54) BSC 0.765 (19.43) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.320 (8.13) 0.290 (7.37) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING PLANE 0.070 (1.78) 0.030 (0.76) 0.015 (0.38) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 20. 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] (D-14) Dimensions shown in inches and (millimeters) 0.200 (5.08) REF 0.100 (2.54) REF 0.015 (0.38) MIN 0.075 (1.91) REF 0.095 (2.41) 0.075 (1.90) 19 18 0.358 (9.09) 0.342 (8.69) SQ 0.358 (9.09) MAX SQ 0.088 (2.24) 0.054 (1.37) 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 3 20 4 0.028 (0.71) 0.022 (0.56) 1 BOTTOM VIEW 0.050 (1.27) BSC 8 14 13 9 45° TYP 0.055 (1.40) 0.045 (1.14) 0.150 (3.81) BSC CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 022106-A 0.100 (2.54) 0.064 (1.63) Figure 21. 20-Terminal Ceramic Leadless Chip Carrier [LCC] (E-20-1) Dimensions shown in inches and (millimeters) REFERENCE PLANE 0.500 (12.70) MIN 0.185 (4.70) 0.165 (4.19) 0.160 (4.06) 0.110 (2.79) 0.335 (8.51) 0.305 (7.75) 0.370 (9.40) 0.335 (8.51) 6 7 5 0.021 (0.53) 0.016 (0.40) 0.115 (2.92) BSC 8 4 9 0.045 (1.14) 0.025 (0.65) 3 2 0.040 (1.02) MAX BASE & SEATING PLANE 10 1 0.034 (0.86) 0.025 (0.64) 0.230 (5.84) BSC 36° BSC DIMENSIONS PER JEDEC STANDARDS MO-006-AF CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 22. 10-Pin Metal Header Package [TO-100] (H-10) Dimensions shown in inches and (millimeters) Rev. D | Page 14 of 16 022306-A 0.050 (1.27) MAX AD532 ORDERING GUIDE Model 1 AD532JCHIPS AD532JD AD532JDZ AD532JH AD532JHZ AD532KD AD532KDZ AD532KH AD532KHZ AD532SCHIPS AD532SD AD532SD/883B AD532SE/883B AD532SH AD532SH/883B 1 Temperature Range 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C Package Description Chip 14-Lead SBDIP 14-Lead SBDIP 10-Pin Metal Header Package [TO-100] 10-Pin Metal Header Package [TO-100] 14-Lead SBDIP 14-Lead SBDIP 10-Pin Metal Header Package [TO-100] 10-Pin Metal Header Package [TO-100] Chip 14-Lead SBDIP 14-Lead SBDIP 20-Terminal LCC 10-Pin Metal Header Package [TO-100] 10-Pin Metal Header Package [TO-100] Z = RoHS Compliant Part. Rev. D | Page 15 of 16 Package Option D-14 D-14 H-10 H-10 D-14 D-14 H-10 H-10 D-14 D-14 E-20-1 H-10 H-10 AD532 NOTES ©2001–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00502-0-2/11(D) Rev. D | Page 16 of 16

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