Revised May 2005 MM74HCT540 • MM74HCT541 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer General Description The MM74HCT540 and MM74HCT541 3-STATE buffers utilize advanced silicon-gate CMOS technology and are general purpose high speed inverting and non-inverting buffers. They possess high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits achieve speeds comparable to low power Schottky devices, while retaining the low power consumption of CMOS. Both devices are TTL input compatible and have a fanout of 15 LS-TTL equivalent inputs. MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug-in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs. The MM74HCT540 is an inverting buffer and the MM74HCT541 is a non-inverting buffer. The 3-STATE control gate operates as a two-input NOR such that if either G1 or G2 are HIGH, all eight outputs are in the high-impedance state. In order to enhance PC board layout, the MM74HCT540 and MM74HCT541 offers a pinout having inputs and outputs on opposite sides of the package. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Features ■ TTL input compatible ■ Typical propagation delay: 12 ns ■ 3-STATE outputs for connection to system buses ■ Low quiescent current: 80 PA ■ Output current: 6 mA (min.) Ordering Code: Order Number Package Number Package Description MM74HCT540WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide MM74HCT540SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HCT540MTC MM74HCT540N MTC20 N20A 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide MM74HCT541WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide MM74HCT541SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HCT541MTC MM74HCT541N MTC20 N20A 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP, SOIC, SOP and TSSOP Top View MM74HCT540 © 2005 Fairchild Semiconductor Corporation Top View MM74HCT541 DS006040 www.fairchildsemi.com MM74HCT540 • MM74HCT541 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer February 1984 MM74HCT540 • MM74HCT541 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) 0.5 to 7.0V 1.5 to VCC 1.5V DC Output Voltage (VOUT) 0.5 to VCC 0.5V Clamp Diode Current (IIK, IOK) r20 mA r35 mA DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC ) r70 mA Storage Temperature Range (TSTG) 65qC to 150qC Supply Voltage (VCC) DC Input Voltage (VIN) Supply Voltage (VCC) 600 mW S.O. Package only 500 mW Max Units 4.5 5.5 V 0 VCC V 40 85 qC 500 ns DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) Power Dissipation (PD) (Note 3) Min Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: 12 mW/qC from 65qC to 85qC. Lead Temperature (TL) 260qC (Soldering 10 seconds) DC Electrical Characteristics VCC 5V r 10% (unless otherwise specified) Symbol VIH Parameter TA Conditions 25qC Typ Minimum HIGH Level TA 40 to 85qC TA 55 to 125qC Guaranteed Limits Units 2.0 2.0 2.0 V 0.8 0.8 0.8 V Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level VIN Output Voltage |IOUT| VIH or VIL 20 PA VCC VCC 0.1 VCC 0.1 VCC 0.1 V |IOUT| 6.0 mA, VCC 4.5V 4.2 3.98 3.84 3.7 V 7.2 mA, VCC 5.5V 5.2 4.98 4.84 4.7 V |IOUT| VOL Maximum LOW Level VIN VIH or VIL Voltage |IOUT| 20 PA 0 0.1 0.1 0.1 V |IOUT| 6.0 mA, VCC 4.5V 0.2 0.26 0.33 0.4 V 7.2 mA, VCC 5.5V 0.2 0.26 0.33 0.4 V r0.1 r1.0 r1.0 PA r0.5 r5.0 r10 PA 8.0 80 160 PA 1.0 1.3 1.5 mA |IOUT| IIN Maximum Input VIN VCC or GND Current IOZ Maximum 3-STATE VOUT Output Leakage G VCC or GND VIH Current ICC Maximum Quiescent VIN Supply Current IOUT VIN VCC or GND 0 PA 2.4V or 0.5V (Note 4) 0.6 Note 4: Measured per input. All other inputs at VCC or GND. www.fairchildsemi.com 2 MM74HCT540: VCC 5.0V, tr Symbol tPHL, tPLH tf 25qC, (unless otherwise specified) 6 ns, TA Parameter Conditions Maximum Output Typ Guaranteed Limits Units CL 45 pF 12 18 ns Maximum Output CL 45 pF 14 28 ns Enable Time RL 1 k: Maximum Output CL 5 pF 13 25 ns Disable Time RL 1 k: Propagation Delay tPZL, tPZH tPLZ, tPHZ AC Electrical Characteristics MM74HCT540: VCC Symbol 5.0V r 10%, tr tf Parameter 6 ns (unless otherwise specified) TA Conditions 25qC Typ tPHL, tPLH Maximum Output Propagation Delay tPZH, tPZL Maximum Output Disable Time tTHL, tTLH Maximum Output 40 to 85qC TA 55 to 125qC Units Guaranteed Limits CL 50 pF 12 20 25 30 CL 150 pF 22 30 38 45 ns RL 1 k: RL 1 k: CL 50 pF CL 50 pF Enable Time tPHZ, tPLZ Maximum Output TA ns CL 50 pF 15 30 38 45 ns CL 150 pF 20 40 50 60 ns 15 30 38 45 ns 6 12 15 18 ns 5 10 10 10 pF 15 20 20 20 pF Rise and Fall Time CIN Maximum Input Capacitance COUT Maximum Output Capacitance CPD Power Dissipation Capacitance (Note 5) (per output) G VCC 12 pF G GND 50 pF Note 5: CPD determines the no load dynamic power consumption, PD IS CPD VCC f ICC. CPD VCC2 f ICC VCC,and the no load dynamic current consumption, 3 www.fairchildsemi.com MM74HCT540 • MM74HCT541 AC Electrical Characteristics MM74HCT540 • MM74HCT541 AC Electrical Characteristics MM74HCT541: VCC 5.0V, tr Symbol tPHL, tPLH tf 6 ns, TA 25qC, (unless otherwise specified) Parameter Conditions Maximum Output Typ Guaranteed Limits Units CL 45 pF 13 20 ns Maximum Output CL 45 pF 17 28 ns Enable Time RL 1 k: Maximum Output CL 5 pF 15 25 ns Disable Time RL 1 k: Propagation Delay tPZL, tPZH tPLZ, tPHZ AC Electrical Characteristics MM74HCT541: VCC Symbol 5.0V r 10%, tr Parameter tf 6 ns (unless otherwise specified) TA Conditions 25qC Typ tPHL, tPLH Maximum Output Propagation Delay tPZH, tPZL Maximum Output Disable Time tTHL, tTLH Maximum Output 40 to 85qC TA 55 to 125qC Units Guaranteed Limits CL 50 pF 14 23 29 34 CL 150 pF 17 33 42 49 ns RL 1 k: RL 1 k: CL 50 pF Enable Time tPHZ, tPLZ Maximum Output TA ns CL 50 pF 17 30 38 45 ns CL 150 pF 22 40 50 60 ns 17 30 38 45 ns 6 12 15 18 ns 5 10 10 10 pF 15 20 20 20 pF CL 5 0 pF Rise and Fall Time CIN Maximum Input Capacitance COUT Maximum Output Capacitance CPD Power Dissipation Capacitance (Note 6) (per output) G VCC 12 pF G GND 45 pF Note 6: CPD determines the no load dynamic power consumption, PD IS CPD V CC f ICC. www.fairchildsemi.com C PD VCC2 f ICC VCC,and the no load dynamic current consumption, 4 MM74HCT540 • MM74HCT541 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com MM74HCT540 • MM74HCT541 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 MM74HCT540 • MM74HCT541 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com MM74HCT540 • MM74HCT541 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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