CYPRESS CY62167E

CY62167E MoBL®
16-Mbit (1 M × 16 / 2 M × 8) Static RAM
16-Mbit (1M × 16 / 2M × 8) Static RAM
Features
■
Configurable as 1 M × 16 or as 2 M × 8 SRAM
■
Very high speed: 45 ns
■
Wide voltage range: 4.5 V to 5.5 V
■
Ultra low standby power
❐ Typical standby current: 1.5 µA
❐ Maximum standby current: 12 µA
reduces power consumption by 99% when addresses are not
toggling. Place the device into standby mode when deselected
(CE1 HIGH, or CE2 LOW, or both BHE and BLE are HIGH). The
input and output pins (I/O0 through I/O15) are placed in a high
impedance state when:
■
Ultra low active power
❐ Typical active current: 2.2 mA at f = 1 MHz
■
Easy memory expansion with CE1, CE2, and OE features
■
Automatic power-down when deselected
■
CMOS for optimum speed and power
■
Offered in 48-pin TSOP I package
Functional Description[1]
The CY62167E is a high performance CMOS static RAM
organized as 1 M words by 16-bits/2 M words by 8-bits. This
device features advanced circuit design to provide an ultra low
active current. This is ideal for providing More Battery Life™
(MoBL®) in portable applications such as cellular telephones.
The device also has an automatic power down feature that
Logic Block Diagram
■
The device is deselected (CE1 HIGH or CE2 LOW)
■
Outputs are disabled (OE HIGH)
■
Both byte high enable and byte low enable are disabled (BHE,
BLE HIGH) or
■
A write operation is in progress (CE1 LOW, CE2 HIGH, and WE
LOW)
To write to the device, take chip enables (CE1 LOW and CE2
HIGH) and write enable (WE) input LOW. If byte low enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
A19). If byte high enable (BHE) is LOW, then data from the I/O
pins (I/O8 through I/O15) is written into the location specified on
the address pins (A0 through A19).
To read from the device, take chip enables (CE1 LOW and CE2
HIGH) and output enable (OE) LOW while forcing the write
enable (WE) HIGH. If byte low enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O0 to I/O7. If byte high enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See the “Truth Table” on
page 11 for a complete description of read and write modes.
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
1 M × 16 / 2 M × 8
RAM ARRAY
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
BYTE
BHE
WE
CE2
BHE
OE
CE1
BLE
BLE
POWER DOWN
CIRCUIT
CE1
A11
A12
A13
A14
A15
A16
A17
A18
A19
CE2
Note
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document Number: 001-15607 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 16, 2010
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CY62167E MoBL®
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings............................................................. 4
Operating Range............................................................... 4
Electrical Characteristics................................................. 4
Capacitance ...................................................................... 4
Thermal Resistance.......................................................... 4
AC Test Loads and Waveforms....................................... 5
Data Retention Characteristics ....................................... 5
Data Retention Waveform................................................ 5
Switching Characteristics................................................ 6
Switching Waveforms ...................................................... 7
Truth Table ...................................................................... 11
Document Number: 001-15607 Rev. *B
Ordering Information......................................................
Ordering Code Definitions .........................................
Package Diagram............................................................
Acronyms ........................................................................
Document Conventions .................................................
Units of Measure .......................................................
Document History Page .................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC Solutions .........................................................
12
12
13
14
14
14
15
15
15
15
15
Page 2 of 15
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CY62167E MoBL®
Pin Configuration[2, 3]
48-Pin TSOP I Top View
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
CE2
NC
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
I/O15/A20
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
Product Portfolio
Power Dissipation
Product
Speed
(ns)
VCC Range (V)
Operating ICC (mA)
f = 1 MHz
CY62167ELL
Min
Typ[4]
Max
4.5
5.0
5.5
45
Standby ISB2 (µA)
f = fmax
Typ[4]
Max
Typ[4]
Max
Typ[4]
Max
2.2
4.0
25
30
1.5
12
Notes
2. NC pins are not connected on the die.
3. The BYTE pin in the 48-TSOPI package must be tied to VCC to use the device as a 1 M × 16 SRAM. The 48-TSOPI package can also be used as a
2 M × 8 SRAM by tying the BYTE signal to VSS. In the 2 M × 8 configuration, pin 45 is A20, while BHE, BLE and I/O8 to I/O14 pins are not used.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 001-15607 Rev. *B
Page 3 of 15
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CY62167E MoBL®
DC input voltage[5, 6].......................................–0.5 V to 6.0 V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Supply voltage to ground
potential ..........................................................–0.5 V to 6.0 V
DC voltage applied to outputs
in high Z state[5, 6] ...........................................–0.5 V to 6.0 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage........................................... >2001 V
(MIL-STD-883, method 3015)
Latch-up current ...................................................... >200 mA
Operating Range
Device
CY62167ELL
Ambient
Temperature
Range
VCC[7]
Industrial –40 °C to +85 °C 4.5 V to 5.5 V
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH voltage
IOH = –1.0 mA
VOL
Output LOW voltage
IOL = 2.1 mA
VIH
Input HIGH voltage
VCC = 4.5 V to 5.5 V
45 ns
Unit
Min
Typ[9]
Max
2.4
–
–
V
–
–
0.4
V
2.2
–
VCC + 0.5 V
V
–0.5
–
0.7[8]
V
VIL
Input LOW voltage
VCC = 4.5 V to 5.5 V
IIX
Input leakage current
GND < VI < VCC
–1
–
+1
µA
IOZ
Output leakage current
GND < VO < VCC, output disabled
–1
–
+1
µA
ICC
VCC operating supply
current
f = fMAX = 1/tRC
–
25
30
mA
–
2.2
4.0
mA
–
1.5
12
µA
ISB2[10]
Automatic power down
current—CMOS inputs
f = 1 MHz
VCC = VCC(max)
IOUT = 0 mA
CMOS levels
CE1 > VCC – 0.2 V or CE2 < 0.2 V, or BHE
and BLE > VCC – 0.2 V, VIN > VCC – 0.2 V or
VIN < 0.2 V, f = 0, VCC = VCC(max)
Capacitance
Parameter[11]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz,
VCC = VCC(typ)
Max
Unit
10
pF
10
pF
TSOP I
Unit
60
°C/W
4.3
°C/W
Thermal Resistance
Parameter[11]
Description
ΘJA
Thermal resistance
(junction to ambient)
ΘJC
Thermal resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit
board
Notes
5. VIL(min) = –2.0 V for pulse durations less than 20 ns.
6. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
7. Full Device AC operation is based on a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.
8. Under DC conditions the device meets a VIL of 0.8 V. However, in dynamic conditions input LOW voltage applied to the device must not be higher than 0.7 V.
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C
10. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
11. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-15607 Rev. *B
Page 4 of 15
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CY62167E MoBL®
AC Test Loads and Waveforms
R1
VCC
OUTPUT
VCC
GND
30 pF
R2
10%
ALL INPUT PULSES
90%
90%
10%
FALL TIME= 1 V/ns
RISE TIME= 1 V/ns
INCLUDING
JIG AND
SCOPE
EQUIVALENT TO: THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
Values
Unit
R1
1800
Ω
R2
990
Ω
RTH
639
Ω
VTH
1.77
V
Data Retention Characteristics
Over the operating range
Parameter
Description
Conditions
Min
Typ[12]
Max
Unit
2.0
–
–
V
VDR
VCC for data retention
–
ICCDR[13]
Data retention current
VCC = VDR, CE1 > VCC – 0.2 V or CE2 <
0.2 V, or BHE and BLE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
–
–
12
µA
tCDR[14]
Chip deselect to data
retention time
–
0
–
–
ns
tR[15]
Operation recovery time –
45
–
–
ns
Data Retention Waveform[16]
VCC
VCC(min)
tCDR
DATA RETENTION MODE
VDR > 2.0 V
VCC(min)
tR
CE1 or
BHE. BLE
or
CE2
Notes
12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
13. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
14. Tested initially and after any design or process changes that may affect these parameters.
15. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
16. BHE. BLE is the AND of BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling BHE and BLE.
Document Number: 001-15607 Rev. *B
Page 5 of 15
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CY62167E MoBL®
Switching Characteristics
Over the Operating Range
Parameter[17, 18]
Description
45 ns
Min
Max
Unit
READ CYCLE
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid
–
45
ns
tDOE
OE LOW to data valid
tLZOE
–
22
ns
[19]
5
–
ns
Z[19, 20]
–
18
ns
10
–
ns
–
18
ns
OE LOW to low Z
tHZOE
OE HIGH to high
tLZCE
CE1 LOW and CE2 HIGH to low Z[19]
Z[19, 20]
tHZCE
CE1 HIGH and CE2 LOW to high
tPU
CE1 LOW and CE2 HIGH to power-up
0
–
ns
tPD
CE1 HIGH and CE2 LOW to power-down
–
45
ns
tDBE
BLE/BHE LOW to data valid
–
45
ns
10
–
ns
–
18
ns
tLZBE
tHZBE
WRITE
BLE/BHE LOW to low
Z[19]
BLE/BHE HIGH to high
Z[19, 20]
CYCLE[21]
tWC
Write cycle time
45
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
35
–
ns
tAW
Address setup to write end
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
35
–
ns
tBW
BLE/BHE LOW to write end
35
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
WE LOW to high
Z[19, 20]
–
18
ns
WE HIGH to low
Z[19]
10
–
ns
tHZWE
tLZWE
Notes
17. Test conditions for all parameters other than tristate parameters assume signal transition time of 1 V/ns, timing reference levels of VCC(typ)/2, input pulse levels
of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 5.
18. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
19. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
20. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
21. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate
a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing should be referenced to the edge of the signal that
terminates the write.
Document Number: 001-15607 Rev. *B
Page 6 of 15
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CY62167E MoBL®
Switching Waveforms
Figure 1. Read Cycle No. 1 (address transition controlled [22, 23])
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 2. Read Cycle No. 2 (OE controlled [23, 24])
ADDRESS
tRC
CE1
tPD
tHZCE
CE2
tACE
BHE/BLE
tDBE
tHZBE
tLZBE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
50%
50%
ICC
ISB
Notes
22. The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH.
23. WE is HIGH for read cycle.
24. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document Number: 001-15607 Rev. *B
Page 7 of 15
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CY62167E MoBL®
Switching Waveforms (continued)
Figure 3. Write Cycle No. 1 (WE controlled [25, 26, 27])
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
tHD
tSD
DATA I/O
NOTE 28
VALID DATA
tHZOE
Notes
25. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate
a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing should be referenced to the edge of the signal that
terminates the write.
26. Data I/O is high impedance if OE = VIH.
27. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
28. During this period the I/Os are in output state and input signals must not be applied.
Document Number: 001-15607 Rev. *B
Page 8 of 15
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CY62167E MoBL®
Switching Waveforms (continued)
Figure 4. Write Cycle No. 2 (CE1 or CE2 controlled.[29, 30, 31])
()
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
DATA I/O
tHD
tSD
NOTE 32
VALID DATA
tHZOE
Figure 5. Write Cycle No. 3 (WE controlled, OE LOW [31])
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
tSA
WE
tHA
tPWE
tSD
DATA I/O
NOTE
32
tHD
VALID DATA
t
LZWE
tHZWE
Notes
29. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate
a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing should be referenced to the edge of the signal that
terminates the write.
30. Data I/O is high impedance if OE = VIH.
31. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
32. During this period the I/Os are in output state and input signals must not be applied.
Document Number: 001-15607 Rev. *B
Page 9 of 15
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CY62167E MoBL®
Switching Waveforms (continued)
Figure 6. Write Cycle No. 4 (BHE/BLE controlled, OE LOW [33])
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
NOTE
34
tHD
VALID DATA
Notes
33. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
34. During this period the I/Os are in output state and input signals must not be applied.
Document Number: 001-15607 Rev. *B
Page 10 of 15
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CY62167E MoBL®
Truth Table
CE1
H
CE2
WE
OE
BHE
BLE
[35]
X
X
X
X
X
X[35]
Inputs Outputs
Mode
Power
High Z
Deselect/power-down
Standby (ISB)
L
X
X
X
X
High Z
Deselect/power-down
Standby (ISB)
[35]
X
X
H
H
High Z
Deselect/power-down
Standby (ISB)
L
H
H
L
L
L
Data out (I/O0–I/O15)
Read
Active (ICC)
L
H
H
L
H
L
Data out (I/O0–I/O7);
High Z (I/O8–I/O15)
Read
Active (ICC)
L
H
H
L
L
H
High Z (I/O0–I/O7);
Data out (I/O8–I/O15)
Read
Active (ICC)
L
H
H
H
L
H
High Z
Output disabled
Active (ICC)
L
H
H
H
H
L
High Z
Output disabled
Active (ICC)
L
H
H
H
L
L
High Z
Output disabled
Active (ICC)
L
H
L
X
L
L
Data in (I/O0–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
Data in (I/O0–I/O7);
High Z (I/O8–I/O15)
Write
Active (ICC)
L
H
L
X
L
H
High Z (I/O0–I/O7);
Data in (I/O8–I/O15)
Write
Active (ICC)
[35]
X
X
Note
35. The ‘X’ (Do not care) state for the chip enables in the truth table refers to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted
Document Number: 001-15607 Rev. *B
Page 11 of 15
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CY62167E MoBL®
Ordering Information
Table 1 lists the CY62167ELL key package features and ordering codes. The table contains only the parts that are currently available.
If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at
www.cypress.com and refer to the product summary page at http://www.cypress.com/products.
Table 1. Key Features and Ordering Information
Speed
(ns)
45
Package
Diagram
Ordering Code
CY62167ELL-45ZXI
51-85183
Package Type
48-pin TSOP I (Pb-free)
Operating
Range
Industrial
Ordering Code Definitions
CY 621 6
7
E LL - 45
ZX
I
Temperature Grade: I = Industrial
Package Type: (ZX = 48-pin TSOP I (Pb-free))
45 = Speed Grade
LL = Low Power
E = Process Technology 90 nm
Buswidth = × 16
Density = 16-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-15607 Rev. *B
Page 12 of 15
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CY62167E MoBL®
Package Diagram
Figure 7. 48-Pin TSOP I (12 mm × 18.4 mm × 1.0 mm), 51-85183
51-85183 *B
Document Number: 001-15607 Rev. *B
Page 13 of 15
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CY62167E MoBL®
Acronyms
Acronym
Description
BHE
byte high enable
BLE
byte low enable
CMOS
complementary metal oxide semiconductor
CE
chip enable
I/O
input/output
OE
output enable
SRAM
static random access memory
TSOP
thin small outline package
VFBGA
very fine ball grid array
WE
write enable
Document Conventions
Units of Measure
Table 2. Units of Measure
Symbol
Unit of Measure
ns
nano seconds
V
volts
µA
micro amperes
mA
milli amperes
pF
pico Farad
°C
degree Celsius
W
watts
Document Number: 001-15607 Rev. *B
Page 14 of 15
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CY62167E MoBL®
Document History Page
Document Title: CY62167E MoBL® 16-Mbit (1 M × 16 / 2 M × 8) Static RAM
Document Number: 001-15607
Rev.
ECN No.
Issue Date
Orig. of
Change
**
1103145
See ECN
VKN
New Data Sheet
*A
1138903
See ECN
VKN
Converted from preliminary to final
Changed ICC(max) spec from 2.8 mA to 4.0 mA for f=1 MHz
Changed ICC(typ) spec from 22 mA to 25 mA for f=fmax
Changed ICC(max) spec from 25 mA to 30 mA for f=fmax
Added footnote# 8 related to VIL
Changed ICCDR spec from 10 μA to 12 μA
Added footnote# 14 related to AC timing parameters
*B
2934385
06/03/10
VKN
Included BHE, BLE in ISB2, ICCDR test conditions to reflect byte power down
feature
Added footnote #35 related to chip enable
Updated package diagram
Updated template
Description of Change
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© Cypress Semiconductor Corporation, 2007-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-15607 Rev. *B
Revised August 16, 2010
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All products and company names mentioned in this document may be the trademarks of their respective holders.
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