ONSEMI NTMD4840NR2G

NTMD4840N
Power MOSFET
30 V, 7.5 A, Dual N−Channel, SOIC−8
Features
•
•
•
•
•
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
Dual SOIC−8 Surface Mount Package Saves Board Space
This is a Pb−Free Device
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RDS(on) Max
V(BR)DSS
24 mW @ 10 V
30 V
Applications
7.5 A
36 mW @ 4.5 V
• Disk Drives
• DC−DC Converters
• Printers
N−Channel
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
±20
V
ID
5.5
A
Rating
Continuous Drain
Current RqJA (Note 1)
TA = 25°C
Power Dissipation
RqJA (Note 1)
TA = 25°C
PD
1.14
W
Continuous Drain
Current RqJA (Note 2)
TA = 25°C
ID
4.5
A
TA = 25°C
PD
0.68
W
Continuous Drain
Current RqJA t < 10 s
(Note 1)
TA = 25°C
ID
7.5
A
Power Dissipation
RqJA t < 10 s (Note 1)
TA = 25°C
PD
1.95
W
IDM
30
A
TJ, TSTG
−55 to
+150
°C
Power Dissipation
RqJA (Note 2)
ID Max
TA = 70°C
Steady
State
Pulsed Drain Current
TA = 70°C
Operating Junction and Storage Temperature
Source Current (Body Diode)
S
3.5
TA = 70°C
TA = 25°C,
tp = 10 ms
6.0
IS
2.0
A
Single Pulse Drain−to−Source Avalanche
Energy TJ = 25°C, VDD = 30 V, VGS = 10 V,
IL = 7.5 Apk, L = 1.0 mH, RG = 25 W
EAS
28
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Rating
Symbol
Max
Junction−to−Ambient – Steady State (Note 1)
RqJA
110
Junction−to−Ambient – t≤10 s (Note 1)
RqJA
64
Junction−to−FOOT (Drain)
RqJF
40
Junction−to−Ambient – Steady State (Note 2)
RqJA
183.5
1
D1 D1 D2 D2
8
SOIC−8
CASE 751
STYLE 11
8
1
4840N
AYWW
G
1
S1 G1 S2 G2
4840N
A
Y
WW
G
= Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Package
Shipping†
Unit
NTMD4840NR2G
SOIC−8
(Pb−Free)
2500/Tape & Reel
°C/W
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 inch sq pad size, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
September, 2009 − Rev. 1
MARKING DIAGRAM
& PIN ASSIGNMENT
Device
THERMAL RESISTANCE RATINGS
© Semiconductor Components Industries, LLC, 2009
G
4.4
Publication Order Number:
NTMD4840N/D
NTMD4840N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)jk
Characteristic
Symbol
Test Condition
Min
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Drain−to−Source Breakdown Voltage Temperature Coefficient
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
V(BR)DSS/TJ
IDSS
V
18
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25°C
1.0
TJ = 100°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
3.0
V
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
Forward Transconductance
VGS(TH)/TJ
1.5
6.0
RDS(on)
gFS
mV/°C
VGS = 10 V
ID = 6.9 A
16
24
VGS = 4.5 V
ID = 5.0 A
26
36
VDS = 1.5 V, ID = 6.9 A
15
mW
S
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
70
Total Gate Charge
QG(TOT)
4.8
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
QG(TOT)
520
VGS = 0 V, f = 1.0 MHz, VDS = 15 V
VGS = 4.5 V, VDS = 15 V, ID = 6.9 A
140
pF
1.1
nC
2.1
1.9
VGS = 10 V, VDS = 15 V, ID = 6.9 A
9.5
nC
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
7.6
VGS = 10 V, VDD = 15 V,
ID = 1.0 A, RG = 3.0 W
tf
5.0
ns
17
3.0
DRAIN−TO−SOURCE CHARACTERISTICS
Forward Diode Voltage
VSD
Reverse Recovery Time
tRR
Charge Time
Ta
Discharge Time
Reverse Recovery Time
Tb
VGS = 0 V
ID = 2.0 A
TJ = 25°C
0.76
TJ = 125°C
0.58
1.0
12.5
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 2.0 A
V
ns
7.3
5.2
QRR
6.0
nC
LS
0.66
nH
0.20
nH
PACKAGE PARASITIC VALUES
Source Inductance
Drain Inductance
LD
Gate Inductance
LG
Gate Resistance
RG
TA = 25°C
1.50
2.0
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
nH
3.0
W
NTMD4840N
TYPICAL PERFORMANCE CURVES
8
TJ = 25°C
ID, DRAIN CURRENT (AMPS)
10
3.4 V
6
3.2 V
4
3.0 V
2
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
32
10V
4.5 V
4.2 V
4V
3.8 V
2.8 V
2.6 V
0
1.0
2.0
4.0
3.0
5.0
24
20
16
12
4
0.045
0.040
0.035
0.030
0.025
0.020
2.5
2
3.5
3
4
5
4
7
6
8
9
TJ = 25°C
0.028
0.026
VGS = 4.5 V
0.024
0.022
0.020
0.018
VGS = 10 V
0.016
0.014
2
10
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
4.5
0.030
3.5
5
6.5
8
9.5
12.5
11
14
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
100000
1.65
VGS = 0 V
ID = 7.5 A
VGS = 10 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
TJ = −55°C
Figure 2. Transfer Characteristics
0.050
1.45
TJ = 25°C
Figure 1. On−Region Characteristics
0.055
1.55
TJ = 125°C
8
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TJ = 25°C
ID = 6.9 A
3
VDS ≥ 10 V
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.060
0.015
28
0
1.5
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (AMPS)
12
1.35
10000
1.25
1.15
1.05
0.95
TJ = 150°C
1000
TJ = 125°C
0.85
0.75
0.65
−50
−25
0
25
50
75
100
125
150
100
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
30
NTMD4840N
TYPICAL PERFORMANCE CURVES
TJ = 25°C
600
C, CAPACITANCE (pF)
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
700
VGS = 0 V
Ciss
500
400
300
200
Coss
100
0
Crss
0
5
10
15
20
25
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
30
10
QT
9
VDS
8
7
VGS
6
5
3
2
VGS = 10 V
ID = 6.9 A
TJ = 25°C
1
0
1
0
Figure 7. Capacitance Variation
IS, SOURCE CURRENT (AMPS)
td(off)
tf
t, TIME (ns)
8
3
5
6
7
4
QG, TOTAL GATE CHARGE (nC)
9
10
2.5
VDD = 15 V
ID = 1 A
VGS = 10 V
10
td(on)
tr
1
10
1.5
1
0.5
0
0.4
0.5
0.6
0.7
0.8
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100 ms
1 ms
1
10 ms
VGS = 20 V
SINGLE PULSE
TC = 25°C
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
1
10
100
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
10
0.01
0.01
VGS = 0 V
TJ = 25°C
RG, GATE RESISTANCE (OHMS)
10 ms
0.1
2
100
100
ID, DRAIN CURRENT (AMPS)
2
Figure 8. Gate−To−Source and
Drain−To−Source Voltage vs. Total Charge
100
1
QGD
QGS
4
30
25
ID = 7.5 A
20
15
10
5
0
25
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
125
50
75
100
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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4
150
NTMD4840N
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AJ
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTMD4840N/D