APW7066 Dual Synchronous Buck PWM Controllers and One Linear Controller Features • General Description The APW7066 has two synchronous buck PWM controllers and one linear controller with high precision internal Two Synchronous Buck Converters and A Linear Regulator • • references voltage to offer accurate outputs. The PWM controllers are designed to drive two N-channel MOSFETs VIN Range up to 12V Input Power Supplies Require 12V and 5V or in synchronous buck topology, and the linear controller drives an external N-channel MOSFET. The device re- Use 12V to Generate a Shunt Regulator 5.8V • 0.6V Reference for VOUT1 and VOUT3 quires 12V and 5V power supplies, if the 5V supply is not available, VCC12 can offer an optional shunt regulator with 0.8% Accurate • • • 3.3V Reference for VOUT2 with 0.8% Accurate 5.8V for 5V supply. All outputs have independent soft-start and enable func- Buffered VTT Reference Output tions by SS/EN pins to control. Connect a capacitor from each SS/EN pin to the ground for setting the soft-start Three Outputs have Independent Soft-Start and Enable • time, and pulling the SS/EN pin below 1V to disable regulator. Pull the SS2/EN2 to VCC, enter the DDR mode, Internal 300kHz Oscillator and Programmable Frequency Range from 70 kHz to 800kHz • • • • • • the SS1/EN1 controls both VOUT1 and VOUT2, and allows VOUT2 to track VOUT1. It also offers the phase shift Synchronous Switching Frequency DDR Mode or Independent Mode Selection function by REFOUT pin to select the phase shift between VOUT1 and VOUT2 in DDR mode or Independent mode. Phase Shift Selection Power Good Function When all SS/EN pins exceed 3.3V and no faults are detected, the PGOOD pin goes high to indicate the regu- Short-Circuit Protection for VOUT1 and VOUT2 lators are ready. If any of the SS/EN pins goes below 3.2V or any of the outputs has a fault condition, the PGOOD pin Thermally Enhanced TSSOP-24P and QFN5x5-32 Packages • will be pulled low. The internal oscillator is nominally 300kHz (keep the FS/ Lead Free and Green Devices Available (RoHS Compliant) SYNC pin open or short to GND), and it offers the programmable frequency function from 70kHz to 800kHz; con- Applications necting a resistor from FS/SYNC to VCC12 to decrease the frequency, conversely, connect a resistor from FS/ • • • SYNC to GND to increase the frequency.The IC also provides the synchronous frequency function. Connect the Graphic Cards DDR memory Power Supplies LGATE signal of another converter to FS/SYNC pin; forcing the switching frequency to follow the external clock. Low-Voltage Distributed Power Supplies The possible synchronous frequency is from 150kHz to 800kHz. There is no Rds(on) sensing or under-voltage sensing on APW7066. However, it provides a simple shortcircuit protection by monitoring the COMP1 and COMP2 for over-voltage. When any of two pins exceeds their trip point and the condition persists for 1-2 internal clock cycle (3-6µs at 300kHz), then it will shut down all regulators. ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 1 www.anpec.com.tw APW7066 BOOT1 NC NC VCC FB1 COMP1 25 1 REFIN 24 UGATE1 NC PGND_1 VCC12_1 REFOUT GND BOTTOM SIDE PAD SS1/EN1 SS2/EN2 LGATE1 LGATE2 SS3/EN3 VCC12_2 VREF PGND_2 DRIVE3 8 BOOT2 NC UGATE2 GND 9 TSSOP-24P (TOP VIEW) PGOOD NC 17 FS/SYNC GND BOTTOM SIDE PAD VCC BOOT1 UGATE1 VCC12 LGATE1 LGATE2 PGND UGATE2 BOOT2 GND PGOOD FS/SYNC NC 24 23 22 21 20 19 18 17 16 15 14 13 FB3 FB1 1 COMP1 2 COMP2 3 FB2 4 REFIN 5 REFOUT 6 SS1/EN1 7 SS2/EN2 8 SS3/EN3 9 VREF 10 DRIVE3 11 FB3 12 FB2 32 COMP2 Pin Configuration 16 QFN5x5-32 (Top View) Ordering and Marking Information Package Code R : TSSOP-24P QA : QFN5x5-32 Operating Ambient Temperature Range C : 0 to 70 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW7066 Assembly Material Handling Code Temperature Range Package Code APW7066 R : APW7066 QA : APW7066 XXXXX XXXXX - Date Code XXXXX - Date Code APW7066 XXXXX Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 2 www.anpec.com.tw APW7066 Absolute Maximum Ratings Symbol VCC12 VCC VUGATE1, VUGATE2 VBOOT1, VBOOT2 Rating Unit VCC12 to GND Parameter -0.3 to 15 V Separate Supply -0.3 to 5.5 V -0.3 to 6 V -0.3 to 30 V -0.3 to 15 V -0.3 to 15 V -0.3 to VCC V -0.3 to VCC V -0.3 to VCC V -0.3 to +0.3 V 0 to +70 °C Shunt Regulator to GND UGATE1, UGATE2 to GND BOOT1, BOOT2 to GND LGATE1, LGATE2 LGATE1, LGATE2 to GND DRIVE3 FS/SYNC DRIVE3 to GND FS/SYNC to GND REFIN, REFOUT, REFIN, REFOUT, PGOOD, VREF to GND PGOOD, VREF FB1, COMP1, FB2, FB1, COMP1, FB2, COMP2, FB3 to GND COMP2, FB3 SS1/EN1, SS1/EN, SS2/EN2, SS3/EN3 to GND SS2/EN2, SS3/EN3 PGND PGND to GND TA Operating Temperature Range TJ Maximum Junction Temperature TSTG Storage Temperature Range TSDR Maximum Lead Temperature Soldering, 10 Seconds +150 °C -65 to +150 °C 260 °C Typical Value Unit TSSOP-24P QFN5x5-32 39 30 °C/W TSSOP-24P QFN5x5-32 5 °C/W Thermal Characteristics Symbol Parameter Thermal Resistance − Junction to Ambient R θJA Thermal Resistance − Junction to Case R θJC Electrical Characteristics Operating Conditions: VCC = 5V, VCC12 = 12V, TA = 0 to 70°C, Unless Otherwise Specified. Symbol Parameter Test Conditions APW7066 Unit Min. Typ. Max. - 4 - mA - 6 - mA - 50 - mA - 7 - mA 5.6 5.8 6.0 V - 20 60 mA INPUT SUPPLY POWER VCC VCC12 VCC12 VCC Input Supply Current (Quiescent) outputs disabled Input Supply Current (Dynamic) UGATEs, LGATEs CL = 1nF, 300kHz Shunt Regulator Output Voltage 20mA current; ~Equivalent to 300Ω resistor VCC to 12V Shunt Regulator Current 300Ω resistor VCC to 12V Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 3 www.anpec.com.tw APW7066 Electrical Characteristics (Cont.) Operating Conditions: VCC = 5V, VCC12 = 12V, TA = 0 to 70°C, unless Otherwise Specified. Symbol Parameter Test Conditions APW7066 Unit Min. Typ. VCC Rising 4.15 4.23 4.4 V VCC Falling 3.9 4.0 4.15 V VCC12 Rising 7.55 7.8 8 V VCC12 Falling 7.1 7.3 7.55 V - 0.6 - V Max. INPUT SUPPLY POWER (CONT.) Power-On Reset Threshold SYSTEM ACCURACY Outputs 1 and 3 Reference Voltage Output 2 Reference Voltage - 3.3V - Outputs 1 and 2 System Accuracy -0.8 - 0.8 % Output 3 System Accuracy -0.8 - 0.8 % -20 - 20 % OSCILLATOR Accuracy Frequency FS/SYNC pin open 240 300 360 kHz Adjustment Range FS/SYNC pin: resistor to GND; resistor to VCC12 70 - 800 kHz Sawtooth Amplitude - 2.1 - V Duty-Cycle Range 0 - 85 % ERROR AMPLIFIER (OUT1 AND OUT2) Open-Loop Gain RL = 10kΩ to ground - 85 - dB Open-Loop Bandwidth CL = 100pF, RL = 10kΩ to ground - 15 - MHz Slew Rate CL = 100pF, RL = 10kΩ to ground - 4 - V/µs EA Offset COMP1/2 to FB1/2; compare to internal VREF/REFIN - 2 - mV Maximum Output Voltage RL = 10kΩ to ground; (may trip short-circuit) - VCC - V Output High Source Current COMP1/2, VCOMP=2V - -50 - mA Output Low Sink Current COMP1/2, VCOMP=2V - 45 - mA - 3.3 - V PROTECTION AND MONITOR Causes PGOOD to go low; if there for a Under-Voltage Threshold (COMP1 and filter time, implies the COMP pin(s) is COMP2) out-of-range, and shuts down IC UV Filter Time Based on internal oscillator clock frequency (nominal 300kHz = 3.3µs clock period) 1 - 2 Clock pulses PGOOD Low Voltage IPGOOD = 2mA - 0.1 0.3 V DRIVE3 to FB3; compare to internal VREF - 2 - mV DRIVE3 High Output Voltage - VCC12 - DRIVE3 High Output Source Current - 1.5 - mA DRIVE3 Low Output Sink Current - 2.5 - mA LINEAR REGULATOR (OUT3) EA Offset Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 4 www.anpec.com.tw APW7066 Electrical Characteristics (Cont.) Operating Conditions: VCC = 5V, VCC12 = 12V, TA = 0 to 70°C, unless Otherwise Specified. Symbol Parameter Test Conditions APW7066 Min. Typ. Max. Unit VREF Output Voltage 1.1µF max capacitance Output Accuracy Source Current - 3.3 - V -0.8 - +0.8 % - - 2.0 mA REFOUT (VTTREF) Output Voltage 0.6 - 3.3 V Offset Voltage Determined by REFIN voltage -10 - +10 mV Source Current 0.2 - 20 mA Sink Current - - 0.48 mA Output Capacitance - 0.1 - µF - 3.8 VCC V V Output High Voltage Minimum To select 0 degree phase; see Table 1 ENABLE/SOFTSTART (SS/EN 1,2,3) Enable Threshold EN Rising - 1.05 - EN falling - 0.95 - - -30 - µA Soft-Start High Voltage End of ramp - 3.5 - V Output High Voltage To select DDR mod; see Table 1 - 3.8 VCC V 150 - 800 kHz - - 12 V Soft-Start Current FS/SYNC PLL Frequency range of Lock-in High Voltage From LG pin of another IC, for example GATE DRIVERS Output1 GATE Driver Source UGATE1, LGATE1=3V, BOOT=12V - 1.8 - A Output2 GATE Driver Source UGATE2, LGATE2=3V, BOOT=12V - 1 - A Output1 GATE Driver Sink UGATE1, LGATE1=3V, BOOT=12V - 2.5 - Ω Output2 GATE Driver Sink UGATE2, UGATE2=3V, BOOT=12V - 4 - Ω Output Voltage UGATE1, UGATE2 - - 30 V Output Voltage LGATE1, LGATE2 - 12 - V Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 5 www.anpec.com.tw APW7066 Typical Operating Characteristics VOUT2 Power Up VOUT1 Power Up VCC12(5V/div) VCC12(5V/div) VCC(2V/div) VCC(2V/div) VOUT2(2V/div) VOUT1(1V/div) SS2(2V/div) SS1(2V/div) Time(5ms/div) Time(5ms/div) VOUT3 Power Up VREF Power Up VCC12(5V/div) VCC12(5V/div) VCC(2V/div) VCC(2V/div) VOUT3(1V/div) VREF(2V/div) SS3(2V/div) SS2(2V/div) Time(5ms/div) Time(5ms/div) Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 6 www.anpec.com.tw APW7066 Typical Operating Characteristics (Cont.) VOUT2 Power Up VOUT1 Power Up UGATE1(20V/div) UGATE2(20V/div) LGATE2(10V/div) LGATE1(10V/div) VOUT1(1V/div) VOUT2(5V/div) SS1(2V/div) SS2(2V/div) Time(2ms/div) Time(2ms/div) DDR Mode Power Up Phase Shift 0 Degrees SS2=VCC VOUT1=REFIN VREF(2V/div) LG1(10V/div) VOUT2(2V/div) LG2(10V/div) VOUT1(1V/div) SS1(2V/div) Time(1µs/div) Time(2ms/div) Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 7 www.anpec.com.tw APW7066 Typical Operating Characteristics (Cont.) Phase Shift 180 Degrees Phase Shift 90 Degrees LG1(10V/div) LG1(10V/div) LG2(10V/div) LG2(10V/div) Time(1µs/div) Time(1µs/div) PGOOD High PGOOD Low SS1(2V/div) SS1(2V/div) SS2(2V/div) SS2(2V/div) SS3(2V/div) SS3(2V/div) PGOOD(5V/div) PGOOD(5V/div) Time(5ms/div) Time(5ms/div) Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 8 www.anpec.com.tw APW7066 Typical Operating Characteristics (Cont.) VOUT1 Short Circuit Protection VOUT2 Short Circuit Protection Comp1 (2V/div) Comp2 (2V/div) SS1 (2V/div) SS2 (2V/div) UG1 (20V/div) UG2 (20V/div) PGOOD (5V/div) PGOOD (5V/div) Time(5µs/div) Time(5µs/div) VOUT1 Load Transient VOUT2 Load Transient VOUT1=VIN3 VOUT1 (0.1V/div) VOUT1=VIN3 VOUT1 (0.2V/div) VOUT2 (0.1V/div) VOUT2 (0.1V/div) VOUT3 (0.1V/div) VOUT3 (0.05V/div) IOUT2 (5A/div) IOUT1 (10A/div) Time(20µs/div) Time(20µs/div) Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 9 www.anpec.com.tw APW7066 Typical Operating Characteristics (Cont.) VOUT3 Load Transient UG1 Rising VOUT1=VIN3 VOUT1 (0.1V/div) UG1 (10V/div) VOUT2 (0.1V/div) Phase1 (10V/div) VOUT3 (0.1V/div) LG1 (10V/div) IOUT3 (2A/div) Time(20µs/div) Time(50ns/div) UG1 Falling UG2 Rising UG1 (10V/div) UG2 (10V/div) Phase1 (10V/div) Phase2 (10V/ LG1 (10V/div) LG2 (10V/div) Time(50ns/div) Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 Time(50ns/div) 10 www.anpec.com.tw APW7066 Typical Operating Characteristics (Cont.) UG2 Falling PGOOD Sink Current vs. PGOOD Voltage 3 2.5 Sink Current (mA) UG2 (10V/div) Phase2 (10V/div) 2 1.5 1 0.5 LG2 (10V/div) 0 0 10 Time(50ns/div) 20 30 40 PGOOD Voltage (mV) REFOUT Voltage vs. Source Current VREF Voltage vs. Source Current 3.32 3.35 3.34 3.31 3.32 VREF Voltage (V) REFOUT Voltage (V) 3.33 3.31 3.3 3.29 3.28 3.27 3.3 3.29 3.26 3.28 3.25 0 5 10 15 0 20 Source Current (mA) Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 0.5 1 1.5 2 Source Current (mA) 11 www.anpec.com.tw APW7066 Typical Operating Characteristics (Cont.) UG1 Source Current vs. Voltage 2.4 2.2 2.4 2.2 2 1.8 2 1.8 Source Current (A) Sink Current (A) UG1 Sink Current vs. Voltage 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 0 2 4 6 8 10 12 0 2 UG1 Voltage (V) 6 8 10 12 UG1 Voltage (V) LG1 Sink Current vs. Voltage LG1 Source Current vs. Voltage 2.4 2.4 2.2 2.2 2 2 1.8 1.8 1.6 1.4 Source Current (A) Sink Current (A) 4 1.2 1 0.8 0.6 0.4 0.2 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 0 2 4 6 8 10 12 0 LG1 Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 2 4 6 8 10 12 LG1 Voltage (V) 12 www.anpec.com.tw APW7066 Typical Operating Characteristics (Cont.) UG2 Sink Current vs. Voltage UG2 Source Current vs. Voltage 1.4 1.6 BOOT=12V BOOT=12V 1.4 1.2 Source Current (A) Sink Current (A) 1.2 1 0.8 0.6 0.4 1 0.8 0.6 0.4 0.2 0.2 0 0 0 2 4 6 8 10 0 12 2 4 8 10 12 UG2 Voltage UG2 Voltage (V) LG2 Source Current vs. Voltage LG2 Sink Current vs. Voltage 1.6 1.4 1.4 1.2 1.2 1 1 Source Current (A) Sink Current (A) 6 0.8 0.6 0.4 0.8 0.6 0.4 0.2 0.2 0 0 0 2 4 6 8 10 0 12 LG2 Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 2 4 6 8 10 12 LG2 Voltage (V) 13 www.anpec.com.tw APW7066 Typical Operating Characteristics (Cont.) DRIVE3 Sink Current vs. Voltage DRIVE3 Source Current vs. Voltage 3.5 2 3 1.5 Source Current (mA) Sink Current (mA) 2.5 2 1.5 1 1 0.5 0.5 0 0 0 2 4 6 8 10 0 12 2 4 DRIVE3 Voltage (V) 8 10 12 DRIVE3 Voltage (V) FS Resistance vs. Switching Frequency Shunt Regulator Sink Current vs. Voltage 60 1000 FS to VCC12 900 50 800 Sink Current (mA) 700 FS Resistance (kΩ) 6 600 500 400 300 200 40 30 20 10 FS to GND 100 0 0 0 3 100 200 300 400 500 600 700 800 Switching Frequency (kHz) Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 3.5 4 4.5 5 5.5 6 6.5 7 Shunt Regulator Voltage (V) 14 www.anpec.com.tw APW7066 Typical Operating Characteristics (Cont.) Comp Source Current vs. Voltage 70 50 60 50 40 Source Current (mA) Sink Current (mA) Comp Sink Current vs. Voltage 60 30 20 10 40 30 20 10 0 0 0 0.5 1 1.5 2 2.5 3 0 1 3 4 VREF Voltage vs. Temperature FB Voltage vs. Temperature 610 3.35 608 3.34 606 3.33 604 3.32 VREF Voltage (V) FB Voltage (mV) 2 Comp Voltage (V) Comp Voltage (V) 602 600 598 596 3.31 3.3 3.29 3.28 594 3.27 592 3.26 3.25 590 0 25 50 75 100 125 0 150 50 75 100 125 150 Temperature (°C) Temperature (°C) Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 25 15 www.anpec.com.tw APW7066 Pin Description PIN FUNCTION NO. NAME TSSOP-24P DFN5x5-32 1 29 2 30 3 31 4 32 FB2 These pins are the inverting inputs of the error amplifiers of their respective regulators. They are used to set the output voltage and the compensation components. 5 1 REFIN This pin is the reference input voltage of error amplifier of the VOUT2. It also provides the voltage into a buffer, which is out on the REFOUT pin. FB1 These pins are the inverting inputs of the error amplifiers of their respective regulators. They are used to set the output voltage and the compensation components. COMP1 These pins are the outputs of error amplifiers of their respective regulators. They are COMP2 used to set the compensation components. 6 3 This pin provides a buffed voltage, which is from REFIN pin. In Independent mode, it can be used by other ICs. In DDR mode, it is from the VOUT1, and can be used as REFOUT the VTT buffer. This pin also uses to select the phase shift (see table1). When this pin pulls to VCC, the buffer is disabled and the REFOUT is not available for use. It is recommended that a 0.1µF capacitor is connected to the ground for stability. 7 4 SS1/EN1 8 5 9 6 10 7 11 8 12 10 These pins provide two functions. Connect a capacitor to the GND for setting the SS2/EN2 soft-start time. Use an open drain logic signal to pull the SS/EN pin low to disable the respective output, leave open to enable the respective output. SS3/EN3 VREF This pin provides a 3.3V reference voltage, which can be used by the REFIN pin or other ICs as a voltage reference. It is recommended that a 1µF capacitor is connected to ground for stability. DRIVE3 This pin drives the gate of an external N-channel MOSFET for linear regulator. FB3 These pins are the inverting inputs of the error amplifiers of their respective regulators. They are used to set the output voltage and the compensation components. This pin is used to adjust the switching frequency. Connecting a resistor from FS/SYNC pin to the ground increases the switching frequency. Conversely, FS/SYNC connecting a resistor from this pin to the VCC12 reduces the switching frequency. In addition, this pin also provides synchronous frequency function. An external clock can be fed into this pin, and force the switching frequency to follow the external clock. 13 11 14 12 PGOOD This pin is an open drain device; connect a pull up resistor to the VCC for PGOOD function. 15 13 GND This pin is the signal ground pin. The metal thermal pad under the package is the IC substrate; connects the GND pin and metal thermal pad together on the board, and ties to the good GND plane for electrical and thermal conduction. 16 16 BOOT2 These pins provide the bootstrap voltage to the gate driver for driving the upper MOSFETs. It can be connected to a power voltage directly, but the difference voltage between the BOOT and VIN must be high enough to drive the upper MOSFETs. 17 14 UGATE2 These pins provide the gate driver for the upper MOSFETs of VOUT1 and VOUT2. 18 18,23 19 20 LGATE2 These pins provide the gate driver for the lower MOSFETs of VOUT1 and VOUT2. 20 21 LGATE1 These pins provide the gate driver for the lower MOSFETs of VOUT1 and VOUT2. 21 19, 22 PGND VCC12 Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 This pin is the power ground pin for the gate driver and linear driver circuit. It should be tied to the GND. Power supply input pin. Connect a nominal 12V power supply to this pin for the gate driver. It is recommended that a decoupling capacitor (1 to 10µF) is connected to the GND for noise decoupling. 16 www.anpec.com.tw APW7066 Pin Description (Cont.) PIN FUNCTION NO. NAME TSSOP-24P DFN5x5-32 22 24 UGATE1 These pins provide the gate driver for the upper MOSFETs of VOUT1 and VOUT2. 23 25 BOOT1 These pins provide the bootstrap voltage to the gate driver for driving the upper MOSFETs. It can be connected to a power voltage directly, but the difference voltage between the BOOT and VIN must be high enough to drive the upper MOSFETs. Power supply input pin. Connect a nominal 5V power supply to this pin for the control circuit, or connect a resistor (nominally 300Ω) to VCC12 for a shunt regulator function (typical 5.8V). It is recommended that a decoupling capacitor (1 to 10µF) is connected to the GND for noise decoupling. 24 28 VCC - 2,9,15,17,26,27 NC Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 17 www.anpec.com.tw APW7066 Block Diagram VCC VREF VCC12 5.8V 30µA Power On Reset and Control SS1/EN1 BOOT1 30µA 3.3V Bias Current SS2/ EN2 0.6V 3.3V Gate Control Logic 1 UGATE1 30µA LGATE1 SS3/EN3 3.3V BOOT2 Oscillator Gate Control Logic 2 UGATE2 LGATE2 PGOOD Monitor COMP Pins for Short Protection FS/SYNC COMP1 0.6V 3.3V 1-2 Clock Cycle Filter FB1 REFOUT If short, Filter shut down all outputs REFIN VCC12 FB3 FB2 0.6V COMP2 DRIVE3 GND Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 PGND 18 www.anpec.com.tw APW7066 Typical Application Circuit APW7066 DDR MODE VCC VCC12 Optional for Shunt Regulator COMP1 VOUT1 VIN1 BOOT1 FB1 UGATE1 COMP2 VOUT2 VOUT1 LGATE1 VCC12 FB2 BOOT2 VOUT1(DDR) VIN2=VOUT1(DDR) REFIN PHASE SHIFT 0o APW7066 VCC12 PHASE SHIFT 90o VTTREF VCC UGATE2 VOUT2 LGATE2 REFOUT VREF PGOOD VIN3 FS/SYNC SYNCHRONOUS FREQUENCY SS1/EN1 DRIVE3 SS2/EN2 VOUT3 FB3 SS3/EN3 GND Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 19 PGND www.anpec.com.tw APW7066 Typical Application Circuit (Cont.) APW7066 INDEPENDENTMODE VCC Optional for shunt VCC12 regulator COMP1 VOUT1 VIN1 BOOT1 FB1 UGATE1 COMP2 VOUT2 PHASE SHIFT 0o LGATE1 VCC12 FB2 BOOT2 VREF VOUT1 VIN2 REFIN APW7066 VCC12 VCC UGATE2 PHASE SHIFT 180o VTTREF VOUT2 LGATE2 REFOUT VREF PGOOD VIN3 FS/SYNC SYNCHRONOUS FREQUENCY SS1/EN1 DRIVE3 SS2/EN2 VOUT3 FB3 SS3/EN3 GND Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 20 PGND www.anpec.com.tw APW7066 Function Description Operational Modes Phase Shift The APW7066 has two independent synchronous buck converters, and it also has DDR mode operation to allow The APW7066 has phase shift function, use the REFOUT pin to select the phase shift between Independent mode VOUT2 to track VOUT1. In independent mode operation, connect a capacitor from and DDR mode. Connect the REFOUT to VCC to get the 0 degre in either mode. In this case, the buffer of the each SS/EN pin to the ground to set each regulator’s softstart time. The 3.3V reference VREF can be used directly, REFOUT is disabled. Leave the REFOUT open shifts the phase 90 degrees in DDR mode, or 180 degrees in Inde- or divided by two resistors for REFIN, since the VREF is controlled by the SS2/EN2. pendent mode, REFOUT can be used in this case (see Table 1.). DDR mode is chosen by connecting the SS2/EN2 pin to VCC(5V). In this mode, SS2/EN2 function will be disabled, Table1. Mode and Phase Selection MODE SS1/EN1 is used to control soft start and enable both VOUT1 and VOUT2. The VOUT1 is used as the REFIN for the VOUT2, that makes VOUT2 to track VOUT1. VREF SS2/EN2 REFOUT REFIN PHASE SHIFT DDR VCC VCC VOUT1 0 deg DDR VCC Open VOUT1 90 deg Independent SS2 cap VCC VREF 0 deg Independent SS2 cap Open VREF 180 deg CH1/CH2 SS1/EN1 for CH1 and CH2 SS1/EN1 for CH1 SS2/EN2 for CH2 REFIN The advantage of Phase shift is to avoid overlapping the switching current spikes of the two channels, or interaction between the channels; it also reduces the RMS current of the input capacitors, allowing fewer caps to be SS1/EN1 employed. However, the phase shift between the rising edge of LGATE1 and LGATE2 (See figure 3.), depending SS2/EN2 SS3/EN3 on the duty cycles, the falling edges of the two channels might overlap; so the user should check it. GND Figure 1. Independent Mode Circuit LG1 LG2 (0deg) VOUT1 REFIN LG2 (90deg) VCC LG2 (180deg) SS1/EN1 SS2/EN2 SS3/EN3 0 GND 90 180 0 Figure 3. Phase of LG2 with respect to rising edge of LG1 Figure 2.DDR Mode Circuit Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 21 www.anpec.com.tw APW7066 Function Description (Cont.) Soft-Start/Enable PGOOD The three SS/EN pins control the soft-start and enable or disable the controller. In Independent mode, the three The PGOOD output is an open-drain device, when the VCC is present; the gate of open-drain device will be regulators all have independent soft-start and enable functions. Connect a soft-start capacitor from each SS/EN high, forcing the PGOOD pin to go low. The three SS/EN pins and the SCP signals control the PGOOD signal (see pin to the GND to set the soft-start interval, and an open drain logic signal for each SS/EN pin will enable or dis- block diagram), after the three SS/EN signals are over threshold high 3.3V and three outputs have no short- able the respective output. Figure 4. Shows the soft-start interval. When both VCC circuit, the PGOOD goes high to indicate all regulators are ready. If any of the SS/EN pins goes below threshold and VCC12 reach their Power-On-Reset threshold 4.23V and 7.8V, a 30µA current source starts to charge the low 3.2V, the PGOOD will go low. Also, if any of the outputs has a short, the PGOOD pull low and if short-circuit condi- capacitor. When the SS reaches the enabled threshold about 1V, the internal 0.6V reference starts to rise and tion continues for 1-2 clock pulses, all regulators will shut down. If the short-circuit is not long enough to shut down, follows the SS; the error amplifier output (COMP) suddenly raises to 1.1V, which is the valley of the oscillator’s it may still cause PGOOD to go low momentarily. Because the PGOOD is an open-drain device, the typical triangle wave, leads the VOUT to start up. Until the SS reaches about 3.0V, the internal reference completes the range of the value to connect a pull high resistor to VCC will be 1kΩ to 10kΩ; if PGOOD is not used, leave it open. soft-start interval and reaches to 0.6V; then VOUT1 is in regulation. The SS1 still rises to 3.5V and then stops. Shunt Regulator The APW7066 must have two power supplies VCC (5V) and VCC12 (12V) to drive the IC; VCC (5V) is for the con- VOLTAGE trol circuit and VCC12 (12V) is for the drivers of outputs. But it can also operate only VCC12, because the shunt regulator 5.8V was designed for VCC (5V); the range of VSS the shunt regulator was designed over the usual range 4.5V to 5.5V of typical 5V power supplies. 3V Connect a resistor from VCC12 to VCC for shunt regulator and for the supply current. The input supply current of VCC is 7mA; minimum shunt regulator current is about 7mA, and therefore the 20mA shunt regulator current is VOUT 1V enough; thus, the typical value, 300Ω of the resistor is recommended. The relation among minimun shunt regut0 t1 t2 lator current, required shunt regulator current and supply current is: TIME ISHUNT = ICC + ISHUNT(MIN) Where: Figure 4. Soft-Start Interval ISHUNT = Required Shunt Regulator Current ICC = Supply Current TSoft - Start = t2 − t1 = CSS ⋅ 2V ISS ISHUNT(MIN) = Minimum Shunt Regulator Current Where: CSS = external Soft-Start capacitor ISS = Soft-Start current = 30µA Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 22 www.anpec.com.tw APW7066 Function Description (Cont.) Shunt Regulator (Cont.) Figure 8 shows the switching timing of the synchronization function. The rising edge of external signal OPTIONAL R VCC (5.8V) FOR SHUNT REGULATOR and the falling edge of UGATE of APW7066 are fixed; there is a delay time between the rising edge of external sig- VCC12 nal and the falling edge of UGATE, the delay time is about 500ns. Figure 9 shows the timing chart of the synchronization function. An external signal is connected to the FS/SYNC pin and the switching frequency of APW7066 will track the frequency of external signal after an additional 300µs delay time to avoid false triggering. If Figure 5. another converter’s signal is lost, the APW7066 will return to internal oscillator. This allows the two switch- Oscillator ing converters operating at the same frequency to avoid the interference from the independent frequencies between The APW7066 provides the oscillator switching frequency adjustment. Connect a resistor from FS/SYNC pin to the them. The acceptable frequency is a range of 150kHz to 800kHz. ground, the nominally 300kHz oscillator switching frequency is increased according to the value of the resistor. The adjustment range of the switching frequency is 300kHz to 800kHz. APW7066 VIN Other Regulator UGATE Conversely, connecting a resistor from FS/SYNC pin to the VCC12 reduces the switching frequency.The adjust- FS/ SYNC ment range of the switching frequency is 70kHz to 300kHz. VOUT LGATE 1000 FS to VCC12 900 Figure 7. Connecting the LGATE signal from other regulator to FS/SYNC pin FS Resistance (kΩ) 800 700 600 External Clock (10V/div) 500 400 300 LGATE1 (10V/div) FS to GND 200 100 0 0 100 200 300 400 500 600 700 800 Switching Frequency UGATE1 (10V/div) Figure 6. FS/SYNC Resistance vs. Frequency LGATE2 (10V/div) SYNC The switching frequency also can be synchronized to an external frequency. If there are two switching convert- Time (0.5µ/div) Figure 8. The switching timing of synchronization func- ers on the same board, taking the LGATE signal from another switching converter, go through a 10kΩ resistor, tion and connecting to the FS/SYNC pin (see Figure 7). Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 23 www.anpec.com.tw APW7066 Function Description (Cont.) SYNC (Cont.) R1 ) x REFIN R2 R1 VOUT3 = (1 + ) x 0.6V R2 R3 REFIN = (1 + ) x VOUT1(DDR Mode) R4 R3 REFIN = (1 + ) x VREF (Independe nt Mode) R4 VOUT2 = (1 + 300µs External Clock (LGATE) LGATE1/2 Where: R1 = resistor from VOUT to FB UGATE1/2 R2 = resistor from FB to GND R3 = resistor from VREF or VOUT1 to REFIN Figure 9. The timing chart of synchronization function R4 = resistor from REFIN to GND Short-Circuit Protection Note that the R1 is part of the compensation. It should be conformed to the feedback compensation. The APW7066 has a simple short-circuit protection to monitor COMP1 and COMP2 for VOUT1/2. When output voltage has a short, the FB pin should start to follow output, since it is a resistor divider from the output. The FB is the inverting input of Error-Amp, when FB pin is lower than the Error-Amp reference, then the COMP will rise to increase the duty-cycle of the upper MOSFET gate driver, this allows output to get higher voltage. If the short-circuit condition is long enough, the COMP pin will exceed the trip point 3.3V,and the duty circle will hit the maximum. This means that either Over-Current or Under-Voltage condition is detected. If any of the COMP1 and COMP2 exceeds their trip points, and holds over a filter time (1-2 clock cycle of switching frequency), then all regulators will shut down, and require a POR on either of VCC or VCC12 to restart. Note that the linear regulator has no short-circuit protection. Output Voltage Setting The output voltage can be adjusted with a resistive divider, from output voltage to FB pin to the ground. Use 1% or better resistors for these resistor dividers is recommended. The reference voltages of VOUT1 and VOUT3 are 0.6V, the reference voltage of VOUT2 is REFIN voltage. The VREF voltage is for REFIN in independent mode. The following equations can be used to calculate the output voltage: VOUT1 = (1 + R1 ) x 0.6V R2 Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 24 www.anpec.com.tw APW7066 Application Information Linear Regulator Input/Output Capacitor Selection GAINLC = The input capacitor is chosen based on its voltage rating. Under load transient condition, the input capacitor will 1+ s × ESR × COUT s2 × L × COUT + s × ESR × COUT + 1 The poles and zero of this transfer function are: momentarily supply the required transient current. The output capacitor for the linear regulator is chosen to minimize any droop during load transient condition. In addition, the capacitor is chosen based on its voltage rating. FLC = 1 2 × π × L × COUT FESR 1 2 × π × ESR× COUT Linear Regulator Input/Output MOSFET Selection The FLC is the double poles of the LC filter, and FESR is the zero introduced by the ESR of the output capacitor. The maximum DRIVE3 voltage is determined by the VCC12. Since this pin drives an external N-channel MOSFET, therefore the maximum output voltage of the L Output PHASE linear regulator is dependent upon the VGS. VOUT3MAX = VCC12 - VGS COUT Another criteria is its efficiency of heat removal. The power ESR dissipated by the MOSFET is given by: Pdiss = IOUTx (VIN - VOUT3) where IOUT is the maximum load current VOUT3 is the nominal output voltage. In some applications, heatsink might be required to help Figure 10. The Output LC Filter maintain the junction temperature of the MOSFET below its maximum rating. FLC -40dB/dec Linear Regulator Compensation Selection FESR The linear regulator is stable over all load current. However, the transient response can be further enhanced by connecting a RC network between the FB3 and DRIVE3 -20dB/dec pin. Depending on the output capacitance and load current of the application, the value of this RC network is then varied. A good starting point for the resistor value is 6.8kΩ and 470pF for the capacitor. Frequency PWM Compensation Figure 11. The LC Filter Gain & Frequency The output LC filter of a step down converter introduces a double pole, which contributes with -40dB/decade gain The PWM modulator is shown in Figure 12. The input is the output of the error amplifier and the output is the PHASE node. The transfer function of the PWM modulator is given slope and 180 degrees phase shift in the control loop. A compensation network between COMP, FB and VOUT by: should be added. The compensation network is shown in Figure 13. GAINPWM = The output LC filter consists of the output inductor and output capacitors. The transfer function of the LC filter is VIN ∆VOSC given by: Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 25 www.anpec.com.tw APW7066 Application Information (Cont.) C1 PWM Compensation (Cont.) VIN R3 Driver C3 R2 C2 VOUT PWM Comparator R1 - VOSC VCOMP FB + Output of Error Amplifier VREF PHASE Figure 13. Compensation Network The closed loop gain of the converter can be written as: Driver GAINLC x GAINPWM x GAINAMP Figure 14. shows the asymptotic plot of the closed loop Figure 12. The PWM Modulator The compensation circuit is shown in Figure 13. It pro- converter gain and the following guidelines will help to design the compensation network. Using the below vide a close loop transfer function with the highest zero crossover frequency and sufficient phase margin. The guidelines should give a compensation similar to the curve plotted. A stable closed loop has a -20dB/decade transfer function of error amplifier is given by: slope and a phase margin greater than 45 degree. 1. Choose a value for R1, usually between 1K and 5K. 1 // R2 + 1 sC2 VCOMP sC1 GAINAMP = = VOUT 1 R1 // R3 + sC3 1 1 × s + s + ( ) R1 R3 C3 + × R1 + R3 R2 × C2 × = 1 R1× R3 × C1 s s + C1 + C2 × s + R2 × C1× C2 R3 × C3 2. Select the desired zero crossover frequency FO: (1/5 ~ 1/10) x FS > FO > FESR Use the following equation to calculate R2: R2 = ∆VOSC VIN × FO × R1 FLC 3. Place the first zero FZ1 before the output LC filter double pole frequency FLC. FZ1 = 0.75 x FLC The poles and zeros of the transfer function are: Calculate the C2 by the equation: 1 FZ1 = 2 × π × R2 × C2 1 FZ2 = 2 × π × (R1+ R3)× C3 1 FP1 = C1× C2 2 × π × R2 × C1 + C2 1 FP2 = 2 × π × R3 × C3 C2 = 1 2 × π × R2 × FLC × 0.75 4. Set the pole at the ESR zero frequency FESR: FP1 = FESR Calculate the C1 by the equation: C1 = C2 2 × π × R2 × C2 × FESR − 1 5. Set the second pole FP2 at half the switching frequency and also set the second zero FZ2 at the output LC filter double pole FLC. The compensation gain should not exceed the error amplifier open loop gain, check the compensation gain at FP2 with the capabilities of the error amplifier. Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 26 www.anpec.com.tw APW7066 Application Information (Cont.) PWM Compensation (Cont.) A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. FP2 = 0.5xFO FZ2 = FLC Increasing the switching frequency (FS) also reduces the ripple current and voltage, but it will increase the switch- Combine the two equations will get the following component calculations: R1 R3 = FS 2xFLC C3 = −1 ing loss of the MOSFET and the power dissipation of the converter. The maximum ripple current occurs at the 1 maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maxi- π × R3 × FS mum output current. Once the inductance value has been chosen, select an inductor that is capable of carrying the required peak current without going into saturation. In some types of Open Loop Error Amp Gain Gain FZ1=0.75FLC FP1=FESR FZ2=FLC 20log (R2/R1) inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. This will FP2=0.5FS result in a larger output ripple voltage. Output Capacitor Selection 20log (VIN/ VOSC) Compensation Gain 0 FLC Higher Capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore select high performance low ESR capacitors that are intended for switching regulator applications. In some applications, FO FESR PWM & Filter Gain multiple capacitors have to be parallel to achieve the desired ESR value. A small decoupling capacitor in parallel Converter Gain for bypassing the noise is also recommended, and the voltage rating of the output capacitors are also must be Frequency considered. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, Figure 14. Converter Gain & Frequency Output Inductor Selection consult the capacitors manufacturer. The inductor value determines the inductor ripple current and affects the load transient response. Higher inductor Input Capacitor Selection value reduces the inductor’s ripple current and induces lower output ripple voltage. The ripple current and ripple The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select voltage can be approximated by: the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMS VIN − VOUT VOUT IRIPPLE = × FS × L VIN current rating requirement is approximately IOUT/2, where IOUT is the load current. During power up, the input capaci- ∆VOUT = IRIPPLE x ESR tors have to handle large amount of surge current. If tantalum capacitors are used, make sure they are surge tested where Fs is the switching frequency of the regulator. Although increase the inductor value and frequency reduce by the manufactures. If in doubt, consult the capacitors manufacturer. For high frequency decoupling, a ceramic the ripple current and voltage, but there is a tradeoff exists between the inductor’s ripple current and the regula- capacitor 1µF can be connected between the drain of upper MOSFET and the source of lower MOSFET. tor load transient response time. Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 27 www.anpec.com.tw APW7066 Application Information (Cont.) MOSFET Selection MOSFETs. If the circuit still works, remove the short can cause an inductive kick on the phase pin, and it may dam- The selection of the N-channel power MOSFETs are determined by the RDS(ON), reverse transfer capacitance (CRSS) age the IC and MOSFETs. • If the resistance of the short is not low enough to cause and maximum output current requirement. The losses in the MOSFETs have two components: conduction loss and protection, the regulator will work as the load has transition loss. For the upper and lower MOSFET, the losses are approximately given by the following : increased, and continue to regulate up until the MOSFETs is damaged. The resistance of the short should include wiring, PCB traces, contact resistances, and all of the return paths. PUPPER = Iout 2(1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS PLOWER = Iout 2(1+ TC)(RDS(ON))(1-D) • The higher duty cycle will give a higher COMP voltage where IOUT is the load current level, and it is easy to touch the trip point. The compensation components also affect the response TC is the temperature dependency of RDS(ON) FS is the switching frequency of COMP voltage; smaller caps may give a faster response. tsw is the switching interval D is the duty cycle • The output current has faster rising time during short; the COMP pin will have a sharp rise. However, if the cur- Note that both MOSFETs have conduction losses while the upper MOSFET include an additional transition loss. rent rises too fast, it may cause a false trip. The output capacitance and its ESR can affect the rising time of the The switching internal, tsw, is a function of the reverse transfer capacitance CRSS. current during short. The (1+TC) term is to factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) Layout Consideration vs. Temperature” curve of the power MOSFET. In high power switching regulator, a correct layout is important to ensure proper operation of the regulator. In general, interconnecting impedances should be mini- Connecting One Input from Another Output It can be connected one of the 3 outputs as the input voltage to the 2nd. In these cases the output current of the mized by using short, wide printed circuit traces. Signal and power grounds are to be kept separate and finally first output includes its own load current and the 2nd output’s load current. Therefore, the components of the combined using ground plane construction or single point grounding. Figure 15 illustrates the layout, with bold lines first output must be designed and sized for the both outputs. The soft-start of first output must be faster than indicating high current paths; these traces must be short and wide. Components along the bold lines should be the 2nd output. If the first output is not present when the 2nd output tries to start up, the 2nd output cannot get placed lose together. Below is a checklist for your layout: • The metal plate of the bottom of the packages (TSSOP- smooth and controlled output voltage rise, even cause short-circuit protection. 24 and QFN5x5-32) must be soldered to the PCB and connected to the GND plane on the backside through several thermal vias. • Keep the switching nodes (UGATE, LGATE and PHASE) Short Circuit Protection The APW7066 provides a simple short circuit protection away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces to function, and it is not easy to predict its performance, since many factors can affect how well it works. Therefore, the these nodes as short as possible. • The traces from the gate drivers to the MOSFETs (UG1, limitations and suggestions of this method must be provided for users to understand how to work it well. LG1, UG2, LG2, DRIVE3) should be short and wide. • Decoupling capacitor, compensation component, the • The short circuit protection was not designed to work for the output in initial short condition. In this case, the resistor dividers, boot capacitors, and SS capacitors should be close their pins. short circuit protection may not work, and damage the Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 28 www.anpec.com.tw APW7066 Application Information (Cont.) Layout Consideration • The input capacitor should be near the drain of the upper MOSFET; the output capacitor should be near the loads. The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND. • The drain of the MOSFETs (VIN and phase nodes) should be a large plane for heat sinking. VIN APW7066 UG FB CREFOUT CVREF VOUT CBOOT Q1 BOOT REFOUT Q2 LG VREF PGND VCC SS VCC12 CSS L1 CIN COUT L O A D CVCC12 CVCC GND Figure 15. Layout Guidelines Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 29 www.anpec.com.tw APW7066 Package Information TSSOP-24P D SEE VIEW A b A VIEW A L 0 GAUGE PLANE SEATING PLANE A1 S Y M B O L 0.25 c A2 e E E2 EXPOSED PAD E1 D1 TSSOP-24P MILLIMETERS MIN. INCHES MAX. A MIN. MAX. 1.20 0.047 A1 0.05 0.15 0.002 0.006 A2 0.80 1.05 0.031 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 D 7.70 7.90 0.303 0.311 D1 3.50 5.00 0.138 0.197 E 6.20 6.60 0.244 0.260 E1 4.30 4.50 0.169 0.177 E2 2.50 3.50 0.098 0.138 0.75 0.018 8o 0o e L 0 0.65 BSC 0.45 0o 0.026 BSC 0.030 8o Note : 1. Followed from JEDEC MO-153 ADT. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E1" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 30 www.anpec.com.tw APW7066 Package Information QFN5x5-32 D b E A A1 D2 A3 L K E2 Pin 1 Corner e S Y M B O L QFN5x5-32 MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.80 1.00 0.031 0.039 A1 0.00 0.05 0.000 A3 0.20 REF 0.002 0.008 REF b 0.18 0.30 0.007 0.012 D 4.90 5.10 0.193 0.201 D2 3.50 3.80 0.138 0.150 0.201 0.150 E 4.90 5.10 0.193 E2 3.50 3.80 0.138 0.45 0.014 e 0.50 BSC L 0.35 K 0.20 0.020 BSC 0.018 0.008 Note : 1. Followed from JEDEC MO-220 VHHD-4. Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 31 www.anpec.com.tw APW7066 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application QFN 5x5-32 Application TSSOP-24P A H 330.0±2.00 50 MIN. P0 P1 4.0±0.10 8.0±0.10 A H 330.0±2.00 50 MIN. P0 P1 4.00±0.10 8.00±0.10 T1 C 12.4+2.00 13.0+0.50 -0.00 -0.20 d D 1.5 MIN. 20.2 MIN. W E1 12.0±0.30 1.75±0.10 F 5.5±0.10 P2 D0 D1 T A0 B0 K0 2.0±0.10 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 5.35±0.20 5.35±0.20 1.30±0.20 T1 C d D W E1 F 1.5 MIN. 20.2 MIN. 16.4+2.00 13.0+0.50 -0.00 -0.20 P2 D0 2.00±0.10 1.5+0.10 -0.00 16.0±0.30 1.75±0.10 7.50±0.10 D1 T A0 B0 K0 1.5 MIN. 0.6+0.00 -0.40 6.9±0.20 8.30.±0.20 1.50±0.20 (mm) Devices Per Unit Package Type QFN5x5-32 TSSOP-24P Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 Unit Tape & Reel Tape & Reel Quantity 2500 2000 32 www.anpec.com.tw APW7066 Taping Direction Information TSSOP-24P USER DIRECTION OF FEED QFN5x5-32 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 33 www.anpec.com.tw APW7066 Classification Profile Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 34 www.anpec.com.tw APW7066 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 35 www.anpec.com.tw