2N/PN/SST 4117, 4118, 4119 ULTRA-HIGH INPUT IMPEDANCE N-CHANNEL JFET AMPLIFIER FEATURES LOW POWER IDSS<600 µA (2N4117A) MINIMUM CIRCUIT LOADING IGSS<1 pA (2N4117A Series) ABSOLUTE MAXIMUM RATINGS (NOTE 3) @ 25°C (unless otherwise noted) Gate-Source or Gate-Drain Voltage -40V Gate-Current 50mA 2N SERIES PN SERIES TO-72 TOP VIEW TO-92 TOP VIEW Total Device Dissipation SST SERIES SOT-23 TOP VIEW SOT-23 TOP VIEW D 1 S 2 G 3 (Derate 2mW/ºC above 25ºC) 300mW Storage Temperature Range -55ºC to+150ºC Lead Temperature (1/16” from case for 10 seconds) 300ºC ELECTRICAL CHARACTERISTICS @ 25ºC (unless otherwise noted) 4117 SYMBOL CHARACTERISTIC 4118 4119 MIN MAX MIN MAX MIN MAX UNITS CONDITIONS BVGSS Gate-Source Breakdown Voltage -40 -- -40 -- -40 -- VGS(off) Gate-Source Cutoff Voltage -0.6 -1.8 -1 -3 -2 -6 IDSS Saturation Drain Current (NOTE 2) 0.03 0.60 0.08 0.60 0.20 0.80 mA -- -1 -- -1 -- -1 pA -- -2.5 -- -2.5 -- -2.5 nA -- -10 -- -10 -- -10 pA -- -25 -- -25 -- -25 nA 150ºC 70 450 80 650 100 700 µS f=1kHz -- 3 -- 5 -- 10 -- 3 -- 3 -- 3 -- 1.5 -- 1.5 -- 1.5 Gate Reverse Current 2N4117A, 2N4118A, 2N4119A V IG =-1µA VDS=0 VDS =10V ID=1nA VDS =10V VGS=0 VGS =-20V VDS=0 150ºC IGSS PN4117, PN4118, PN4119 SST4117, SST4118, SST4119 gfs gos Ciss Crss Common-Source Forward Transconductance Common-Source Output Conductance Common-Source Input Capacitance (NOTE 4) Common-Source Reverse Transfer Capacitance (NOTE 4) Linear Integrated Systems VGS =-10V VDS=0 VDS =10V VGS=0 pF f=1MHz • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201135 05/20/2014 Rev#A7 ECN# 2N & SST 4117 4118 4119 STANDARD PACKAGE DIMENSIONS: 2N4117A, 2N4118A, 2N4119A PN4117, PN4118, PN4119 SST4117, SST4118, SST4119 TO-72 TO-92 SOT-23 SOT-23 Four Lead 0.89 1.03 0.37 0.51 1 1.78 2.05 2.80 3.04 3 2 1.20 1.40 2.10 2.64 0.89 1.12 0.085 0.180 0.013 0.100 0.55 DIMENSIONS IN MILLIMETERS *Dimensions in inches NOTES: 1. Due to symmetrical geometry, these units may be operated with source and drain leads interchanged. 2. This parameter is measured during a 2 ms interval 100 ms after power is applied. (Not a JEDEC condition.) 3. Absolute maximum ratings are limiting values above which serviceability may be impaired. 4. Not production tested, guaranteed by design. Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Linear Integrated Systems. 5. Linear Integrated Systems (LIS) is a 25-year-old, third-generation precision semiconductor company providing high-quality discrete components. Expertise brought to LIS is based on processes and products developed at Amelco, Union Carbide, Intersil and Micro Power Systems by company President John H. Hall. Hall, a protégé of Silicon Valley legend Dr. Jean Hoerni, was the director of IC Development at Union Carbide, Co-Founder and Vice President of R&D at Intersil, and Founder/President of Micro Power Systems. Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201135 05/20/2014 Rev#A7 ECN# 2N & SST 4117 4118 4119