P3C1041 high speed 256k X 16 (4 MEG) static cmos ram FEATURES Fast Access Times - 10/12/15/20 ns Advanced CMOS Technology Low Power Operation Fast tOE Single 3.3V ± 0.3V Power Supply Automatic Power Down when deselected Packages – 44-Pin TSOP II 2.0V Data Retention Easy Memory Expansion Using CE and OE Inputs Fully TTL Compatible Inputs and Outputs DESCRIPTION The P3C1041 is a 262,144 words by 16 bits high-speed CMOS static RAM. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 3.3V ± 0.3V tolerance power supply. Access times as fast as 10 nanoseconds permit greatly enhanced system operating speeds. CMOS is utilized to reduce power consumption to a low level. The P3C1041 device provides asynchronous operation Functional Block Diagram with matching access and cycle times. Memory locations are specified on address pins A0 to A17. Reading is accomplished by device selection (CE) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE or OE os HIGH or WE is LOW. The P3C1041 is packaged in a 44-pin 400-mil wide TSOP II package. Pin Configuration TSOP II Document # SRAM130 REV B Revised May 2011 P3C1041 - HIGH SPEED 256K x 16 STATIC CMOS RAM Maximum Ratings(1) Sym RECOMMENDED OPERATING CONDITIONS Parameter Value Unit V Grade(2) Ambient Temp GND VCC 0°C to 70°C 0V 3.3V ± 10% -40°C to +85°C 0V 3.3V ± 10% VCC Power Supply Pin with Respect to GND -0.5 to +4.6 VTERM Terminal Voltage with Respect to GND (up to 7.0V) -0.5 to VCC + 0.5 V TA Operating Temperature -55 to +125 °C TBIAS Temperature Under Bias -55 to +125 °C TSTG Storage Temperature -65 to +150 °C Sym Parameter IOUT DC Output Current 20 mA CIN Input Capacitance COUT Output Capacitance Commercial Industrial CAPACITANCES(4) (VCC = 3.3V, TA = 25°C, f = 1.0MHz) Conditions Typ Unit VIN=0V 8 pF VOUT=0V 8 pF DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) Sym Parameter Test Conditions Min Max Unit VIH Input High Voltage 2.0 VCC + 0.3 V VIL Input Low Voltage -0.3(3) 0.8 V VOL Output Low Voltage (TTL Load) IOL = +8 mA, VCC = Min 0.4 V VOH Output High Voltage (TTL Load) IOH = -4 mA, VCC = Min ILI Input Leakage Current VCC = Max. VIN=GND to VCC 2.4 V -1 +1 µA -1 +1 µA — 20 mA — 10 mA VCC = Max. ILO Output Leakage Current CE = VIH, VOUT = GND to VCC CE ≥ VIH ISB Standby Power Supply Current (TTL Input Levels) VCC = Max. f = Max., Outputs Open VIN ≥ VIH or VIN ≤ VIL CE ≥ VCC - 0.2V ISB1 Standby Power Supply Current (CMOS Input Levels) VCC = Max. f = 0, Outputs Open VIN ≥ VCC - 0.3V or VIN ≤ 0.3V Document # SRAM130 REV B Page 2 P3C1041 - HIGH SPEED 256K x 16 STATIC CMOS RAM POWER DISSIPATION CHARACTERISTICS VS. SPEED Sym ICC Parameter Dynamic Operating Current* Temperature Range -10 -12 -15 -20 Unit Commercial 90 80 70 60 mA Industrial N/A 95 85 75 mA * VCC = 3.6V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH. AC ELECTRICAL CHARACTERISTICS—READ CYCLE (VCC = 3.3V ± 0.3V, All Temperature Ranges)(2) Sym Parameter -10 Min -12 Max Max Max Max Address Access Time 10 12 15 20 ns tAC Chip Enable Access Time 10 12 15 20 ns tOH Output Hold from Address Change 3 3 3 3 ns tLZ Chip Enable to Output in Low Z 3 3 3 3 ns tHZ Chip Disable to Output in High Z 5 6 7 8 ns tOE Output Enable Low to Data Valid 5 7 7 8 ns tOLZ Output Enable Low to Low Z tOHZ Output Enable High to High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time 10 12 15 20 ns tBE Byte Enable to Data Valid 5 7 7 8 ns tHZBE Byte Disable to High Z Document # SRAM130 REV B 0 5 0 0 6 0 0 7 ns 8 0 0 6 ns 0 0 0 6 20 Unit tAA 0 15 Min Read Cycle Time Byte Enable to Low Z 12 Min -20 tRC tLZBE 10 Min -15 ns 0 7 ns 8 ns Page 3 P3C1041 - HIGH SPEED 256K x 16 STATIC CMOS RAM TIMING WAVEFORM OF READ CYCLE NO. 1 TIMING WAVEFORM OF READ CYCLE NO. 2 (OE CONTROLLED)(5,6) Notes: 1.Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Maximum rating conditions for extended periods may affect reliability. 2.Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3.Transient inputs with VIL not more negative than –2.0V and VIH ≤ VCC + 0.5V, are permissible for pulse widths up to 20 ns. Document # SRAM130 REV B 4.This parameter is sampled and not 100% tested. 5.WE is HIGH for READ cycle. 6.CE is LOW and OE is LOW for READ cycle. 7.ADDRESS must be valid prior to, or coincident with CE transition LOW. 8.Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9.Read Cycle Time is measured from the last valid address to the first transitioning address. Page 4 P3C1041 - HIGH SPEED 256K x 16 STATIC CMOS RAM AC CHARACTERISTICS—WRITE CYCLE (VCC = 3.3V ± 0.3V, All Temperature Ranges)(2) Sym Parameter -10 Min -12 Max Min -15 Max Min -20 Max Min Max Unit tWC Write Cycle Time 10 12 15 20 ns tCW Chip Enable Time to End of Write 7 8 10 10 ns tAW Address Valid to End of Write 7 8 10 10 ns tAS Address Setup Time to Write Start 0 0 0 0 ns tWP Write Pulse Width 7 8 10 10 ns tAH Address Hold Time 0 0 0 0 ns tDW Data Valid to End of Write 5 6 7 8 ns tDH Data Hold Time 0 0 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write 5 5 0 0 ns tLZWE WE High to Low Z 3 3 3 3 ns tBW Byte Enable to End of Write 7 8 10 10 ns 5 6 7 8 ns TIMING WAVEFORM OF WRITE Cycle No. 1 (CE Controlled) Document # SRAM130 REV B Page 5 P3C1041 - HIGH SPEED 256K x 16 STATIC CMOS RAM Timing Waveform of Write Cycle No. 2 (BLE OR BHE Controlled) Timing Waveform of Write Cycle No. 3 (WE Controlled, OE LOW) Document # SRAM130 REV B Page 6 P3C1041 - HIGH SPEED 256K x 16 STATIC CMOS RAM data retention characteristics Symbol Parameter Test Condition VDR VCC for Data Retention ICCDR Data Retention Current CE ≥ VCC - 0.2V, tCDR Chip Deselect to Data Retention Time VIN ≥ VCC - 0.2V or tR† Operation Recovery Time VIN ≤ 0.2V Min Max 2.0 Unit V 10 mA 0 ns tRC§ ns data retention WAVEFORM Document # SRAM130 REV B Page 7 P3C1041 - HIGH SPEED 256K x 16 STATIC CMOS RAM AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Output Load See Figures 1, 2, 3 Figure 1. AC Output Load Figure 2. High-Z Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the ultra-high speed of the P4C116/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used. TRUTH TABLE Mode CE OE WE BLE BHE I/O0-I/O7 I/O8-I/O15 Power Power-down H X X X X High Z High Z Standby Read All Bits L L H L L DOUT DOUT Active Read Lower Bits Only L L H L H DOUT High Z Active Read Upper Bits Only L L H H L High Z DOUT Active Write All Bits L X L L L DIN DIN Active Write Lower Bits Only L X L L H DIN High Z Active Write Upper Bits Only L X L H L High Z DIN Active Selected, Outputs Disabled L H H X X High Z High Z Active Document # SRAM130 REV B Page 8 P3C1041 - HIGH SPEED 256K x 16 STATIC CMOS RAM ORDERING INFORMATION Document # SRAM130 REV B Page 9 P3C1041 - HIGH SPEED 256K x 16 STATIC CMOS RAM Pkg # T2 # Pins 44 TSOP II THIN SMALL OUTLINE PACKAGE Symbol Min Max A 0.039 0.047 A2 0.033 0.045 b 0.012 0.017 D 0.717 0.733 e 0.0315 BSC E 0.453 0.473 E1 0.392 0.408 Document # SRAM130 REV B Page 10 P3C1041 - HIGH SPEED 256K x 16 STATIC CMOS RAM REVISIONS DOCUMENT NUMBER SRAM 130 DOCUMENT TITLE P3C1041 - HIGH SPEED 256K x 16 STATIC SMOS RAM REV ISSUE DATE ORIGINATOR OR Oct-2005 JDB New Data Sheet A Sep-2008 JDB Updated TSOP II package drawing B Sep-2011 JDB Removed SOJ package Document # SRAM130 REV B DESCRIPTION OF CHANGE Page 11