PYRAMID P4C116

P4C116/P4C116L
ULTRA HIGH SPEED 2K x 8
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
Fully TTL Compatible Inputs and Outputs
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25/35 ns (Commercial)
– 15/20/25/35 ns (Military)
Produced with PACE II TechnologyTM
Standard Pinout (JEDEC Approved)
– 24-Pin 300 mil DIP, SOIC, SOJ
– 24-Pin Solder Seal Flat Pack
– 24-Pin Rectangular LCC (300 x 400 mils)
– 28-Pin Square LCC (450 x 450 mils)
– 32-Pin Rectangular LCC (450 x 550 mils)
– 40-Pin Square LCC (480 x 480 mils)
Low Power Operation
Output Enable Control Function
Single 5V±10% Power Supply
Common Data I/O
DESCRIPTION
The P4C116/P4C116L are 16,384-bit ultra high-speed
static RAMs organized as 2K x 8. The CMOS memories
require no clocks or refreshing and have equal access
and cycle times. Inputs are fully TTL-compatible. The
RAMs operate from a single 5V±10% tolerance power
supply. Current drain is typically 10 µA from a 2.0V
supply.
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
The P4C116 is available in 24-pin 300 mil DIP, SOJ and
SOIC packages, a solder seal flatpack and 4 different
LCC packages (24, 28, 32, and 40 pin).
DIP (P4, C4), SOJ (J4), SOIC (S4)
SOLDER SEAL FLAT PACK (FS-1) SIMILAR
LCC configurations at end of datasheet
Document # SRAM110 REV A
1
Revised October 2005
P4C116/P4C116L
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
VCC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
VTERM
Terminal Voltage with
Respect to GND
(up to 7.0V)
–0.5 to
VCC +0.5
V
TA
Operating Temperature
–55 to +125
°C
Symbol
Ambient Temp
Commercial
Military
Gnd
0V
5.0V ±10%
-55°C to +125°C
0V
5.0V ±10%
Unit
TBIAS
Temperature Under
Bias
–55 to +125
°C
TSTG
Storage Temperature
–65 to +150
°C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
50
mA
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
Vcc
0°C to 70°C
Value
CAPACITANCES(4)
RECOMMENDED OPERATING CONDITIONS
Grade(2)
Parameter
Symbol
Parameter
Conditions Typ. Unit
CIN
Input Capacitance
VIN = 0V
5
pF
COUT
Output Capacitance VOUT= 0V
7
pF
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
Symbol
Parameter
P4C116
Min
Max
Test Conditions
P4C116L
Min
Max
Unit
VIH
Input High Voltage
2.2
VCC +0.5
2.2
VCC +0.5
V
VIL
Input Low Voltage
–0.5(3)
0.8
–0.5(3)
0.8
V
VHC
CMOS Input High Voltage
VLC
CMOS Input Low Voltage
VCD
Input Clamp Diode Voltage VCC = Min., IIN = –18 mA
Output Low Voltage
IOL = +8 mA, VCC = Min.
(TTL Load)
VOL
VOH
Output High Voltage
(TTL Load)
ILI
Input Leakage Current
ILO
Output Leakage Current
ISB
Standby Power Supply
Current (TTL Input Levels)
ISB1
Standby Power Supply
Current
(CMOS Input Levels)
VCC –0.2 VCC +0.5 VCC –0.2 VCC +0.5
–0.5
(3)
IOH = –4 mA, VCC = Min.
VCC = Max.
–0.5
V
0.2
V
–1.2
–1.2
V
0.4
0.4
V
2.4
Mil.
V
2.4
–10
–5
+10
+5
–5
n/a
+5
n/a
µA
–10
–5
+10
+5
–5
n/a
+5
n/a
µA
Mil.
___
30
___
20
20
___
mA
Ind./Com’l.
___
n/a
Mil.
___
15
___
Ind./Com’l.
___
10
___
VIN = GND to VCC
Com’l.
VCC = Max., CE = VIH,
VOUT = GND to VCC
Mil.
Com’l.
CE ≥ VIH,
VCC= Max,
0.2
(3)
f = Max., Outputs Open
CE ≥ VHC,
VCC= Max,
1
mA
n/a
f = 0, Outputs Open
VIN ≤ VLC or VIN ≥ VHC
n/a = Not Applicable
Document # SRAM110 REV A
Page 2 of 14
P4C116/P4C116L
DATA RETENTION CHARACTERISTICS (P4C116L Military Temperature Only)
Symbol
Parameter
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR
Chip Deselect to
Data Retention Time
tR†
Operation Recovery Time
Test Conditons
Min
Typ.*
VCC =
2.0V
3.0V
Max
VCC =
2.0V
3.0V
V
2.0
10
CE ≥ VCC –0.2V,
15
600
900
µA
0
ns
tRC§
ns
VIN ≥ VCC –0.2V
or VIN ≤ 0.2V
Unit
*TA = +25°C
§tRC = Read Cycle Time
†
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
Parameter
ICC
Dynamic Operating Current*
Temperature
Range
Commercial
Military
–10
–12
180
170
–15
160
N/A
N/A
170
–20
155
160
–35
–25
150
155
140
150
Unit
mA
mA
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym.
Parameter
–12
–10
–20
–15
–25
–35
Min Max Min Max Min Max Min Max Min Max Min Max
Unit
tRC
Read Cycle Time
tAA
tAC
Address Access Time
10
12
15
20
25
35
ns
Chip Enable Access Time
10
12
15
20
25
35
ns
tOH
Output Hold from Address Change
2
2
2
2
2
2
ns
tLZ
Chip Enable to Output in Low Z
2
2
2
2
3
3
ns
tHZ
Chip Disable to Output in High Z
5
6
7
8
10
15
ns
tOE
Output Enable Low to Data Valid
6
8
10
10
15
20
ns
tOLZ Output Enable Low to Low Z
0
tOHZ Output Enable High to High Z
tPU
Chip Enable to Power Up Time
tPD
Chip Disable to Power Down
Document # SRAM110 REV A
15
12
10
0
6
0
0
7
12
25
0
8
0
0
10
20
0
0
20
ns
0
12
9
0
15
35
ns
15
0
20
ns
ns
25
ns
Page 3 of 14
P4C116/P4C116L
OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
Document # SRAM110 REV A
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE transition
LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Page 4 of 14
P4C116/P4C116L
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym.
Parameter
–10
–20
–15
–12
–35
–25
Min Max Min Max Min Max Min Max Min Max Min Max
Unit
tWC
Write Cycle Time
10
12
15
20
25
35
ns
tCW
Chip Enable Time to End of Write
8
10
12
15
18
25
ns
tAW
Address Valid to End of Write
8
10
12
15
18
25
ns
tAS
Address Set-up Time
0
0
0
0
0
0
ns
tWP
Write Pulse Width
8
10
12
15
18
20
ns
tAH
Address Hold Time
0
0
0
0
0
0
ns
tDW
Data Valid to End of Write
7
8
10
12
15
20
ns
tDH
Data Hold Time
0
0
0
0
0
0
ns
tWZ
Write Enable to Output in High Z
tOW
Output Active from End of Write
6
0
7
0
8
0
10
0
15
0
15
0
ns
ns
WE CONTROLLED)(10,11)
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE
CE CONTROLLED)(10)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE
Notes:
10. CE and WE must be LOW for WRITE cycle.
11. OE is LOW for this WRITE cycle to show tWZ and tOW.
12. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state
Document # SRAM110 REV A
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Page 5 of 14
P4C116/P4C116L
AC TEST CONDITIONS
Input Pulse Levels
TRUTH TABLE
GND to 3.0V
Mode
CE
OE
WE
I/O
Power
Input Rise and Fall Times
3ns
Standby
H
X
X
High Z
Standby
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
DOUT
Disabled
L
H
H
High Z
Active
Read
L
L
H
DOUT
Active
Write
L
X
L
High Z
Active
Output Load
See Figures 1 and 2
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C116/L, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads that
cause supply bounce must be avoided by bringing the VCC and ground
planes directly up to the contactor fingers. A 0.01 µF high frequency
Document # SRAM110 REV A
capacitor is also required between VCC and ground. To avoid signal
reflections, proper termination must be used; for example, a 50Ω test
environment should be terminated into a 50Ω load with 1.73V (Thevenin
Voltage) at the comparator input, and a 116Ω resistor must be used in
series with DOUT to match 166Ω (Thevenin Resistance).
Page 6 of 14
P4C116/P4C116L
LCC PIN CONFIGURATIONS
24-Pin LCC (L8)
28-Pin LCC (L5-1)
32-Pin LCC (L6)
40-Pin LCC (L10)
Document # SRAM110 REV A
Page 7 of 14
P4C116/P4C116L
ORDERING INFORMATION
SELECTION GUIDE
The P4C116 is available in the following temperature, speed and package options.
Temperature
Range
Commercial
Military
Temperature
Military
Processed*
Package
Speed (ns)
10
12
15
20
25
35
Plastic DIP
-10PC
-12PC
-15PC
-20PC
-25PC
-35PC
Plastic SOJ
-10JC
-12JC
-15JC
-20JC
-25JC
-35JC
Plastic SOIC
-10SC
-12SC
-15SC
-20SC
-25SC
-35SC
24-Pin Rect. LCC
N/A
N/A
-15LM
-20LM
-25LM
-35LM
28-Pin Sq. LCC
N/A
N/A
-15L28M
-20L28M
-25L28M
-35L28M
32-Pin Rect. LCC
N/A
N/A
-15L32M
-20L32M
-25L32M
-35L32M
40-Pin Sq. LCC
N/A
N/A
-15L40M
-20L40M
-25L40M
-35L40M
Side Brazed DIP
N/A
N/A
-15CM
-20CM
-25CM
-35CM
CERPACK
N/A
N/A
-15FSM
-20FSM
-25FSM
-35FSM
24-Pin Rect. LCC
N/A
N/A
-15LMB
-20LMB
-25LMB
-35LMB
28-Pin Sq. LCC
N/A
N/A
-15L28MB
-20L28MB
-25L28MB
-35L28MB
32-Pin Rect. LCC
N/A
N/A
-15L32MB
-20L32MB
-25L32MB
-35L32MB
40-Pin Sq. LCC
N/A
N/A
Side Brazed DIP
N/A
N/A
-15L40MB
-15CMB
-20L40MB
-20CMB
-25L40MB
-25CMB
-35L40MB
-35CMB
CERPACK
N/A
N/A
-15FSMB
-20FSMB
-25FSMB
-35FSMB
* Military temperature range with MIL-STD-883, Class B processing.
N/A = Not Available
Document # SRAM110 REV A
Page 8 of 14
P4C116/P4C116L
Pkg #
# Pins
Symbol
A
b
b2
C
D
E
eA
e
L
Q
S1
S2
Pkg #
# Pins
Symbol
A
b
b1
c
c1
D
E
E1
E2
E3
e
k
L
Q
S1
M
N
C4
SIDE BRAZED DUAL IN-LINE PACKAGE
24 (300 mil)
Min
Max
0.200
0.014
0.026
0.045
0.065
0.008
0.018
1.280
0.220
0.310
0.300 BSC
0.100 BSC
0.125
0.200
0.015
0.060
0.005
0.005
-
FS-1
SOLDER SEAL FLATPACK
24
Min
Max
0.045
0.115
0.015
0.022
0.015
0.019
0.004
0.009
0.004
0.006
0.640
0.350
0.420
0.450
0.180
0.030
0.050 BSC
0.008
0.015
0.250
0.370
0.026
0.045
0.000
0.0015
24
Document # SRAM110 REV A
Page 9 of 14
P4C116/P4C116L
Pkg #
# Pins
Symbol
A
A1
b
C
D
e
E
E1
E2
Q
Pkg #
# Pins
Symbol
A
A1
B1
D/E
D1/E1
D2/E2
D3/E3
e
h
j
L
L1
L2
ND
NE
J4
SOJ SMALL OUTLINE IC PACKAGE
24 (300 mil)
Min
Max
0.128
0.148
0.082
0.016
0.020
0.007
0.010
0.620
0.630
0.050 BSC
0.335 BSC
0.292
0.300
0.267 BSC
0.025
-
L5-1
SQUARE LEADLESS CHIP CARRIER
28
Min
Max
0.060
0.075
0.050
0.065
0.022
0.028
0.442
0.460
0.300 BSC
0.150 BSC
0.460
0.050 BSC
0.040 REF
0.020 REF
0.045
0.055
0.045
0.055
0.075
0.095
7
7
Document # SRAM110 REV A
Page 10 of 14
P4C116/P4C116L
Pkg #
# Pins
Symbol
A
A1
B1
D
D1
D2
D3
E
E1
E2
E3
e
h
j
L
L1
L2
ND
NE
Pkg #
# Pins
Symbol
A
A1
B1
D
D1
D2
D3
E
E1
E2
E3
e
h
j
L
L1
L2
ND
NE
L6
RECTANGULAR LEADLESS CHIP CARRIER
32
Min
Max
0.060
0.075
0.050
0.065
0.022
0.028
0.442
0.458
0.300 BSC
0.150 BSC
0.458
0.540
0.560
0.400 BSC
0.200 BSC
0.558
0.050 BSC
0.040 REF
0.020 REF
0.045
0.055
0.045
0.055
0.075
0.095
7
9
L8
RECTANGULAR LEADLESS CHIP CARRIER
24
Min
Max
0.064
0.076
0.054
0.066
0.022
0.028
0.292
0.308
0.200 BSC
0.100 BSC
0.308
0.392
0.408
0.300 BSC
0.150 BSC
0.408
0.050 BSC
0.025 REF
0.015 REF
0.040
0.050
0.040
0.050
0.077
0.093
5
7
Document # SRAM110 REV A
Page 11 of 14
P4C116/P4C116L
Pkg #
# Pins
Symbol
A
A1
B1
D/E
D1/E1
D2/E2
D3/E3
e
h
j
L
L1
L2
ND/NE
Pkg #
# Pins
Symbol
A
A1
b
b2
C
D
E1
E
e
eB
L
α
L10
SQUARE LEADLESS CHIP CARRIER
40
Min
Max
0.060
0.080
0.050
0.075
0.015
0.025
0.475
0.492
0.360 BSC
0.180 BSC
0.492
0.040 BSC
R = .0075
0.026 REF
0.030
0.050
0.030
0.050
0.080
0.090
10
P4
PLASTIC DUAL IN-LINE PACKAGE
24 (300 Mil)
Min
Max
0.210
0.015
0.014
0.022
0.045
0.070
0.008
0.014
1.230
1.280
0.240
0.280
0.300
0.325
0.100 BSC
0.430
0.115
0.150
0°
15°
Document # SRAM110 REV A
Page 12 of 14
P4C116/P4C116L
Pkg #
# Pins
Symbol
A
A1
b2
C
D
e
E
H
h
L
α
S4
SOIC/SOP SMALL OUTLINE IC PACKAGE
24 (300 Mil)
Min
Max
0.093
0.104
0.004
0.012
0.013
0.020
0.009
0.012
0.598
0.614
0.050 BSC
0.291
0.299
0.394
0.419
0.010
0.029
0.016
0.050
0°
8°
Document # SRAM110 REV A
Page 13 of 14
P4C116/P4C116L
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
SRAM110
P4C116 / P4C116L ULTRA HIGH SPEED 2K x 8 STATIC CMOS RAMS
REV.
ISSUE
DATE
ORIG. OF
CHANGE
OR
1997
DAB
New Data Sheet
A
Oct-05
JDB
Change logo to Pyramid
Document # SRAM110 REV A
DESCRIPTION OF CHANGE
Page 14 of 14