SN74S225 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS SDLS207B – SEPTEMBER 1976 – REVISED APRIL 1998 D D D D D Independent Asychronous Inputs and Outputs 16 Words by 5 Bits DC to 10-MHz Data Rate 3-State Outputs Packaged in Standard Plastic 300-mil DIPs description This 80-bit active-element memory is a monolithic Schottky-clamped transistor-transistor logic (STTL) array organized as 16 words by 5 bits. A memory system using the SN74S225 easily can be expanded in multiples of 48 words or of 10 bits as shown in Figure 3. The 3-state outputs controlled by a single output-enable (OE) input make bus connection and multiplexing easy. N PACKAGE (TOP VIEW) CLKA IR UNCK OUT D0 D1 D2 D3 D4 OE GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC CLKB CLR OR UNCK IN Q0 Q1 Q2 Q3 Q4 A first-in, first-out (FIFO) memory is a storage device that allows data to be written into and read from its array at independent data rates. This FIFO is designed to process data at rates from dc to 10 MHz in a bit-parallel format, word by word. Reading or writing is done independently, utilizing separate asynchronous data clocks. Data can be written into the array on the low-to-high transition of either load-clock (CLKA, CLKB) input. Data can be read out of the array on the low-to-high transition of the unload-clock (UNCK IN) input (normally high). Writing data into the FIFO can be accomplished in one of two ways: D D In applications not requiring a gated clock control, best results are achieved by applying the clock input to one of the clocks while tying the other clock input high. In applications needing a gated clock, the load clock (gate control) must be high for the FIFO to load on the next clock pulse. CLKA and CLKB can be used interchangeably for either clock gate control or clock input. Status of the SN74S225 is provided by three outputs. The input-ready (IR) output monitors the status of the last word location and signifies when the memory is full. This output is high whenever the memory is available to accept any data. The unload-clock (UNCK OUT) output also monitors the last word location. This output generates a low-logic-level pulse (synchronized to the internal clock pulse) when the location is vacant. The third status output, output ready (OR), is high when the first word location contains valid data and UNCK IN is high. When UNCK IN goes low, OR will go low and stay low until new valid data is in the first word position. The first word location is defined as the location from which data is provided to the outputs. The data outputs are noninverted with respect to the data inputs and are 3-state, with a common control input (OE). When OE is low, the data outputs are enabled to function as totem-pole outputs. A high logic level forces each data output to a high-impedance state while all other inputs and outputs remain active.The clear (CLR) input invalidates all data stored in the memory array by clearing the control logic and setting OR to a low logic level on the high-to-low transition of a low-active pulse. The SN74S225 is characterized for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74S225 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS SDLS207B – SEPTEMBER 1976 – REVISED APRIL 1998 logic symbol† OE UNCK IN 9 16 FIFO 16 × 5 2 EN6 5, 2 Z1 3– CTR CLR CLKA CLKB D0 D1 D2 D3 D4 18 1 CT = 0 & CT < 16 G2 CT > 0 G3 2 1 5 17 UNCK OUT IR OR 4D C4 Z5 6 15 14 6 13 7 12 8 11 † This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. 2 2 2+ 19 4 1, 3 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q0 Q1 Q2 Q3 Q4 functional block diagram Words 3 – 14 Same as 2 or 15 Word 16 (last word) 4 Word 2 Word 1 (first word) 15 14 13 12 11 C1 17 Q1 Q2 Q3 Q4 OE OR 1D R UNCK 3 OUT IR CLR 2 18 16 UNCK IN 3 SDLS207B – SEPTEMBER 1976 – REVISED APRIL 1998 • DALLAS, TEXAS 75265 D1 5 6 D2 7 D3 8 D4 SN74S225 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS Same as Q0 Same as D10 9 CLKA 1 19 CLKB Q0 Data Outputs POST OFFICE BOX 655303 Data Inputs D0 Word 15 SN74S225 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS SDLS207B – SEPTEMBER 1976 – REVISED APRIL 1998 schematics of inputs and outputs EQUIVALENT OF ALL INPUTS EXCEPT DATA INPUTS VCC Input EQUIVALENT OF DATA INPUTS TYPICAL OF ALL OUTPUTS VCC VCC 58 Ω NOM Input Output absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Off-state output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74S225 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS SDLS207B – SEPTEMBER 1976 – REVISED APRIL 1998 recommended operating conditions VCC VIH Supply voltage VIL Low-level input voltage IOH High level output current High-level IOL Low level output current Low-level TA Operating free-air temperature High-level input voltage MIN NOM MAX UNIT 4.75 5 5.25 V 2 V 0.8 Q outputs –6.5 All other outputs –3.2 Q outputs 16 All other outputs 8 0 70 V mA mA °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL Q outputs All others Q outputs All others IOZH IOZL II IIH IIL Data All others Data All others IOS‡ ICC§ TEST CONDITIONS MIN VCC = 4.75 V, VCC = 4.75 V, II = –18 mA IOL = –6.5 mA VCC = 4.75 V, VCC = 4.75 V, IOL = –3.2 mA IOL = 16 mA VCC = 4.75 V, VCC = 5.25 V, IOL = 8 mA VO = 2.4 V VCC = 5.25 V, VCC = 5.25 V, VO = 0.5 V VI = 5.5 V VCC = 5 5.25 25 V V, VI = 2 2.7 7V 25 V VCC = 5 5.25 V, 5V VI = 0 0.5 VCC = 5.25 V, VCC = 5.25 V VO = 0 TYP† 2.4 2.9 2.4 2.9 MAX UNIT –1.2 V V 0.35 0.5 0.35 0.5 50 µA 1 mA 25 –1 –0.25 80 µA –50 40 –30 V µA mA –100 mA 120 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ Duration of the short circuit should not exceed one second. § ICC is measured with all inputs grounded and the outputs open. timing requirements over recommended operating conditions (unless otherwise noted) (see Figure 1) MIN fclock Clock frequency tw Pulse duration CLKA or CLKB high UNCK IN low CLR low Data (see Note 3) tsu Set p time before CLKA↑ or CLKB↑ Setup CLR inactive th Hold time after CLKA↑ or CLKB↑ NOTE 3: Data must be set up within 20 ns after the load-clock positive transition. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 NOM MAX UNIT 10 MHz 25 7 ns 40 –20 25 70 ns ns 5 SN74S225 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS SDLS207B – SEPTEMBER 1976 – REVISED APRIL 1998 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS CLKA fmax CL = 30 pF CLKB UNCK IN 10 20 10 20 10 20 7 14 MAX UNIT MHz UNCK OUT tdis OE Any Q CL = 5 pF 10 25 ns ten tPLH OE Any Q CL = 30 pF 25 40 ns UNCK IN CL = 30 pF 50 75 Any Q 50 75 CLKA or CLKB OR CL = 30 pF 190 300 UNCK IN OR CL = 30 pF 40 60 30 45 CLR OR 35 60 tPLH tPHL tPHL CLKA or CLKB UNCK IN CLKA or CLKB UNCK OUT CL = 30 pF IR UNCK IN tPLH CLR OR↑ IR CL = 30 pF Any Q † All typical values are at VCC = 5 V, TA = 25°C. 6 TYP† tw tPHL tPLH CL = 30 pF MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns 25 45 270 400 55 75 255 400 16 35 10 20 ns ns ns ns ns SN74S225 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS SDLS207B – SEPTEMBER 1976 – REVISED APRIL 1998 PARAMETER MEASUREMENT INFORMATION 7V PARAMETER Open S1 ten R1 = 500 Ω From Output Under Test tdis Test Point CL (see Note A) tpd R2 = 500 Ω LOAD CIRCUIT FOR 3-STATE OUTPUTS S1 tPZH tPZL tPHZ tPLZ tPLH tPHL 3.5 V High-Level Pulse 1.3 V 1.3 V 0.3 V th tsu tw 1.3 V 3.5 V Low-Level Pulse 1.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS PULSE DURATION 3.5 V Data Input 1.3 V 0.3 V 3.5 V Timing Input Open Closed Open Closed Open Open 1.3 V 0.3 V 3.5 V VOLTAGE WAVEFORMS SET UP AND HOLD TIMES Output Control 1.3 V 1.3 V 0.3 V 3.5 V Input (see Note C) 1.3 V tPZL 1.3 V tPLZ 0.3 V tPLH In-Phase Output 1.3 V tPHL Out-of-Phase Output tPHL VOH 1.3 V VOL tPLH 1.3 V VOH 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 3.5 V Waveform 1 S1 Closed (see Note B) 1.3 V tPHZ VOL 0.3 V tPZH Waveform 2 S1 Open (see Note B) VOH 1.3 V 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74S225 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS SDLS207B – SEPTEMBER 1976 – REVISED APRIL 1998 APPLICATION INFORMATION CLR ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ Inputs CLKA CLKB Word 1 D Word 2 Word 16 Word 3 is Low UNCK IN Outputs IR UNCK OUT OR Q Word 1 Word 1 Load Word 1 Load Word 2 Word 3 Unload Word 1 Load Words 3–15 Clear Word 2 Load Word 16 Unload Words 3–15 Unload Word 2 Figure 2. Typical Waveforms for a 16-Word FIFO 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Word 16 Unload Word 16 SN74S225 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS SDLS207B – SEPTEMBER 1976 – REVISED APRIL 1998 APPLICATION INFORMATION (high) (high) CLKB (high) CLKB CLKB CLK CLKA OR CLKA OR CLKA OR NC UNCK OUTUNCK IN IR D0 Q0 D1 Q1 UNCK OUTUNCK IN IR D0 Q0 D1 Q1 UNCK OUTUNCK IN IR D0 Q0 D1 Q1 5-Bit Data In NC NC D2 Q2 D2 Q2 D2 D3 Q3 D3 Q3 D3 Q3 D4 Q4 D4 Q4 D4 Q4 CLR OE CLR OE CLR Q2 OR UNCK IN 5-Bit Data Out OE CLR OE IR CLR (high) NC 5-Bit Data In OE CLR (high) CLKB OE CLR (high) CLKB OE CLKB CLKA OR CLKA OR CLKA OR UNCK OUTUNCK IN IR D0 Q0 D1 Q1 UNCK OUTUNCK IN IR D0 Q0 D1 Q1 UNCK OUTUNCK IN IR D0 Q0 D1 Q1 NC NC D2 Q2 D2 Q2 D2 Q2 D3 Q3 Q4 D3 Q3 Q4 D3 Q3 Q4 D4 D4 D4 5-Bit Data Out Figure 3. Word-Width Expansion: 48 × 10 Bits POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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