SPN10T10 N-Channel Enhancement Mode MOSFET DESCRIPTION The SPN10T10 is the N-Channel logic enhancement mode power field effect transistor which is produced using super high cell density DMOS trench technology. The SPN10T10 has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low RDS(ON) and fast switching speed. APPLICATIONS Powered System DC/DC Converter Load Switch FEATURES 100V/5A,RDS(ON)= 160mΩ@VGS= 10V High density cell design for extremely low RDS (ON) Exceptional on-resistance and maximum DC current capability TO-220,TO-220F package design PIN CONFIGURATION TO-220 TO-220F PART MARKING 2012/07/23 Preliminary Page 1 SPN10T10 N-Channel Enhancement Mode MOSFET PIN DESCRIPTION Pin Symbol Description 1 G Gate 2 D Drain 3 S Source Package Part Marking ORDERING INFORMATION Part Number SPN10T10T220TGB TO-220 SPN10T10T220FTGB TO-220F ※ SPN10T10T220TGB : Tube ; Pb – Free ; Halogen - Free ※ SPN10T10T220FTGB : Tube ; Pb – Free ; Halogen - Free SPN10T10 SPN10T10 ABSOULTE MAXIMUM RATINGS (TA=25℃ Unless otherwise noted) Parameter Symbol Typical Unit Drain-Source Voltage VDSS 100 V Gate –Source Voltage VGSS ±20 V Continuous Drain Current(TJ=150℃) TC=25℃ TC=100℃ ID 9 5.6 A Pulsed Drain Current IDM 30 A Avalanche Current IAS 9 A Power Dissipation TC = 25℃ TC=100℃ PD 28 10 W TJ 150 ℃ Storage Temperature Range TSTG -55/150 ℃ Thermal Resistance-Junction to Ambient RθJA 65 ℃/W Operating Junction Temperature 2012/07/23 Preliminary Page 2 SPN10T10 N-Channel Enhancement Mode MOSFET ELECTRICAL CHARACTERISTICS (TA=25℃ Unless otherwise noted) Parameter Symbol Conditions Min. V(BR)DSS VGS=0V,ID=250uA 100 Typ Max. Unit Static Drain-Source Breakdown Voltage Gate Threshold Voltage VGS(th) VDS=VGS,ID=250uA Gate Leakage Current IGSS Zero Gate Voltage Drain Current IDSS On-State Drain Current ID(on) Drain-Source On-Resistance 1 3 VDS=0V,VGS=±20V VDS=80V,VGS=0V VDS=80V,VGS=0V TJ=125℃ VDS≥5V,VGS =10V RDS(on) VGS= 10V, ID=5A Forward Transconductance gfs VDS=10V,ID=5A Diode Forward Voltage VSD IS=9A,VGS =0V ±100 25 250 9 V nA uA A 0.110 0.160 5.6 Ω S 1.3 V Dynamic Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Input Capacitance Ciss 10 VDS=80V,VGS=10V ID= 5A 4.5 430 VDS=25,VGS=0V f=1MHz Coss Reverse Transfer Capacitance Crss 35 td(on) 6.5 Turn-Off Time 2012/07/23 Preliminary tr td(off) tf nC 2.5 Output Capacitance Turn-On Time 16 VDD=50V,RL=10Ω ID≡5A,VGEN=10V RG=3.3Ω pF 56 10 nS 13 3.4 Page 3 SPN10T10 N-Channel Enhancement Mode MOSFET TYPICAL CHARACTERISTICS 2012/07/23 Preliminary Page 4 SPN10T10 N-Channel Enhancement Mode MOSFET TYPICAL CHARACTERISTICS 2012/07/23 Preliminary Page 5 SPN10T10 N-Channel Enhancement Mode MOSFET TYPICAL CHARACTERISTICS 2012/07/23 Preliminary Page 6 SPN10T10 N-Channel Enhancement Mode MOSFET TO-220 PACKAGE OUTLINE 2012/07/23 Preliminary Page 7 SPN10T10 N-Channel Enhancement Mode MOSFET TO-220F PACKAGE OUTLINE 2012/07/23 Preliminary Page 8 SPN10T10 N-Channel Enhancement Mode MOSFET Information provided is alleged to be exact and consistent. SYNC Power Corporation presumes no responsibility for the penalties of use of such information or for any violation of patents or other rights of third parties which may result from its use. No license is granted by allegation or otherwise under any patent or patent rights of SYNC Power Corporation. Conditions mentioned in this publication are subject to change without notice. This publication surpasses and replaces all information previously supplied. SYNC Power Corporation products are not authorized for use as critical components in life support devices or systems without express written approval of SYNC Power Corporation. ©The SYNC Power logo is a registered trademark of SYNC Power Corporation ©2012 SYNC Power Corporation – Printed in Taiwan – All Rights Reserved SYNC Power Corporation 7F-2, No.3-1, Park Street NanKang District (NKSP), Taipei, Taiwan 115 Phone: 886-2-2655-8178 Fax: 886-2-2655-8468 ©http://www.syncpower.com 2012/07/23 Preliminary Page 9