CDB4392 Evaluation Board for CS4392 Features Description l Demonstrates The CDB4392 evaluation board is an excellent means for quickly evaluating the CS4392 24-bit, stereo D/A converter. Evaluation requires an analog signal analyzer, a digital signal source, a PC for controlling the CS4392 (for control port mode only) and a power supply. Analog line level outputs are provided via RCA phono jacks. recommended layout and grounding arrangements l CS8414 receives AES/EBU, S/PDIF, & EIAJ340 compatible digital audio l Digital and analog patch areas l Requires only a digital signal source and power supplies for a complete Digital-toAnalog-Converter system The CS8414 digital audio receiver I.C. provides the system timing necessary to operate the Digital-to-Analog converter and will accept AES/EBU, S/PDIF, and EIAJ340 compatible audio data. The evaluation board may also be configured to accept external timing and data signals for operation in a user application during system development. ORDERING INFORMATION CDB4392 Evaluation Board I/O for Clocks and Data Control Port Channel A Output and Mute CS8414 Digital Audio Interface CS4392 Channel B Output and Mute Preliminary Product Information P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2001 (All Rights Reserved) MAY ‘01 DS459DB1 1 CDB4392 TABLE OF CONTENTS 1. CDB4392 SYSTEM OVERVIEW .............................................................................................. 3 2. CS4392 DIGITAL TO ANALOG CONVERTER ........................................................................ 3 3. CS8414 DIGITAL AUDIO RECEIVER ...................................................................................... 3 4. CS8414 DATA FORMAT .......................................................................................................... 3 5. INPUT/OUTPUT FOR CLOCKS AND DATA ........................................................................... 4 6. POWER SUPPLY CIRCUITRY ................................................................................................. 4 7. GROUNDING AND POWER SUPPLY DECOUPLING ............................................................ 4 8. CONTROL PORT SOFTWARE ................................................................................................ 4 9. DSD OPERATION .................................................................................................................... 4 10. ANALOG OUTPUT FILTER .................................................................................................. 5 LIST OF FIGURES Figure 1. System Block Diagram and Signal Flow .......................................................................... 8 Figure 2. CS4392 and Level Shifters .............................................................................................. 9 Figure 3. Channel A Selectable Instrumentation Amplifier............................................................ 10 Figure 4. Channel B Selectable Instrumentation Amplifier............................................................ 11 Figure 5. Channel A Audio Output and Mute Circuit ..................................................................... 12 Figure 6. Channel B Audio Output and Mute Circuit .................................................................... 13 Figure 7. CS8414 Digital Audio Receiver...................................................................................... 14 Figure 8. I/O for Clocks and Data.................................................................................................. 15 Figure 9. Control Port Interface ..................................................................................................... 16 Figure 10. Power Supply and Reset Circuitry ............................................................................... 17 Figure 11. Silkscreen Top ............................................................................................................. 18 Figure 12. Top Side....................................................................................................................... 19 Figure 13. Bottom Side.................................................................................................................. 20 LIST OF TABLES Table 1. CS8414 Supported Formats.............................................................................................. 3 Table 2. System Connections ......................................................................................................... 5 Table 3. CDB4392 Jumper and Switch settings - STAND-ALONE MODE ..................................... 6 Table 4. CDB4392 Jumper and Switch settings - CONTOL PORT MODE..................................... 7 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com. 2 DS459DB1 CDB4392 1. CDB4392 SYSTEM OVERVIEW The CDB4392 evaluation board is an excellent means of quickly evaluating the CS4392. The CS8414 digital audio interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio test equipment. The evaluation board also allows the user to supply clocks and data through a 10-pin header for system development. The CDB4392 schematic has been partitioned into 9 schematics shown in Figures 2 through 10. Each partitioned schematic is represented in the system diagram shown in Figure 1. Notice that the system diagram also includes the interconnections between the partitioned schematics. 2. CS4392 DIGITAL TO ANALOG CONVERTER A description of the CS4392 is included in the CS4392 datasheet. 3. CS8414 DIGITAL AUDIO RECEIVER The system receives and decodes the standard S/PDIF data format using a CS8414 Digital Audio Receiver, Figure 5. The outputs of the CS8414 include a serial bit clock, serial data, left-right clock (FSYNC), de-emphasis control and a 256 Fs master clock. The operation of the CS8414 and a discussion of the digital audio interface are included in the CS8414 datasheet. During normal operation, the CS8414 operates in the Channel Status mode where the LED’s display channel status information for the channel selected by the CSLR/FCK jumper. This allows the CS8414 to decode the de-emphasis bit from the digital audio interface for control of the CS4392 de-emphasis filter, when the CS4392 is in stand-alone mode. When the Error Information Switch is activated, the CS8414 operates in the Error and Frequency information mode. The information displayed by the DS459DB1 LED’s can be decoded by consulting the CS8414 datasheet. It is likely that the de-emphasis control for the CS4392 will be erroneous and produce an incorrect audio output if the Error Information Switch is activated and the CS4392 is in the standalone mode with the de-emphasis jumper selected. Encoded sample frequency information can be displayed provided a proper clock is being applied to the FCK pin of the CS8414. When an LED is lit, this indicates a "1" on the corresponding pin located on the CS8414. When an LED is off, this indicates a "0" on the corresponding pin. Neither the L nor R option of CSLR/FCK should be selected if the FCK pin is being driven by a clock signal. The evaluation board has been designed such that the input can be either optical or coax, see Figure 6. However, both inputs cannot be driven simultaneously. 4. CS8414 DATA FORMAT The CS8414 data format can be set with switches M0, M1, M2, and M3, as described in the CS8414 datasheet. The format selected must be compatible with the data format of the CS4392, as shown in the CS4392 datasheet. Please note that the CS8414 does not support all the possible modes of the CS4392 and the Left-Justified Format for the CS8414 and the CS4392 have incompatible serial clocks, see Table 1. The default settings for M0-M3 on the evaluation board are given in Tables 3-4. CS4392 CP Mode Format 0 1 2 3 4 5 CS4392 SA Mode Format 0 1 2 3 - CS8414 Format Unsupported 2 5 Unsupported Unsupported 6 Table 1. CS8414 Supported Formats 3 CDB4392 5. INPUT/OUTPUT FOR CLOCKS AND DATA 7. GROUNDING AND POWER SUPPLY DECOUPLING The evaluation board has been designed to allow interfacing to external systems via the 10-pin header, J9. This header allows the evaluation board to accept externally generated clocks and data. The schematic for the clock/data I/O is shown in Figure 8. The 74HC243 transceiver functions as an I/O buffer where HRD1 through HRD6 determine if the transceiver operates as a transmitter or receiver. A transmit function is implemented with all jumpers, HRD1 through HDR6 in the 8414 position. LRCK, SDATA, and SCLK from the CS8414 will be outputs on J9. The transceiver operates as a receiver with HRD1 through HDR6 in the EXT_CLK position. MCLK, LRCK, SDATA and SCLK on J9 become inputs. The CS4392 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 10 details the power distribution used on this board. The decoupling capacitors are located as close to the CS4392 as possible. Extensive use of ground plane fill in the evaluation board yields large reductions in radiated noise. 6. POWER SUPPLY CIRCUITRY Power is supplied to the evaluation board by five binding posts (GND, +5V, VL, +12V and -12V), see Figure 10. The +5V input supplies power to the +5 volt digital circuitry (VA+5, VD+5, VDPC+5) and to VA on the CS4392, while the VL input supplies power to the Voltage Level Converters and the CS4392 VL pin. +12V and -12V supply power to the op-amp and can be +/-5 to +/-12 volts. WARNING: Refer to the CS4392 datasheet for maximum allowable voltages levels. Operation outside of this range can cause permanent damage to the device. 4 8. CONTROL PORT SOFTWARE The CDB4392 is shipped with Windows based software for interfacing with the CS4392 control port via the DB25 connector, P1. The software can be used to communicate with the CS4392 in either SPI or Two Wire mode; however, in SPI mode the CS4392 registers are write-only. Note: The Two Wire control port mode is compatible with the I2C protocol. Further documentation for the software is available on the distribution diskette. The documentation is available in the plain text format file, README.TXT. 9. DSD OPERATION The CDB4392 supports Direct Stream Digital (DSD) operation through the header for external clocks and data, J9. The CS4392 must be placed into the DSD mode and the jumpers HDR1 through HDR6 must be placed into the external clock positions. DS459DB1 CDB4392 10. ANALOG OUTPUT FILTER The analog output filter on the CDB4392 has been designed to add flexibility when evaluating the CS4392. The output filter was designed in an optional two stage format, with the first optional stage being an instrumentation amplifier design and the second is a 2-pole butterworth filter. The 2-pole filter is designed to have the in-band impedance matched between the positive and negative legs. It also provides a balanced to single ended conversion for standard un-balanced outputs. HDR17 for channel B, right) to position 2. This instrumentation amplifier incorporates a 3x gain (+9.5dB) which effectively lowers the noise contribution of the 2-pole filter which improves the overall dynamic range of the system. Resistors R16 and R21 can be adjusted to change the gain of the Instrumentation amp, and R2(R23) must equal R3(R22). The gain of this stage is determined from the following equation where R= R16(R21) and R2= R2(R23)=R3(R22): 2(R ) 1 + ----------R2 The instrumentation amplifier is optionally inserted by changing the FILT jumpers (HDR13 and HDR15 for channel A, left, and HDR16 and CONNECTOR INPUT/OUTPUT +5V Input + 5 Volt power SIGNAL PRESENT +3/+5V ** Input + 5 Volt **ONLY** power for the CS4392 VL Input + 1.8 to +5.5 digital interface voltage (Note that VL should not exceed the voltage applied to the+3/+5V terminal) VEE Input -12 to -5V negative supply for the op-amp VCC Input +5 to +12V positive supply for the op-amp GND Input Ground connection from power supply Coax Input Input Digital audio interface input via coax Optical Input Input Digital audio interface input via optical J9 Input/Output I/O for master, serial, left/right clocks and serial data Parallel Port Input/Output Parallel connection to PC for SPI / Two Wire control port signals HDR9 Input/Output I/O for SPI / Two Wire control port signals AOUTA Output Channel A line level analog output AOUTB Output Channel B line level analog output Table 2. System Connections DS459DB1 5 CDB4392 JUMPER / SWITCH PURPOSE POSITION FUNCTION SELECTED SW1 - M0 CS8414 mode selection *LO See CS8414 datasheet for details SW1 - M1 CS8414 mode selection *HI See CS8414 datasheet for details SW1 - M2 CS8414 mode selection *LO See CS8414 datasheet for details SW1 - M3 CS8414 mode selection *LO See CS8414 datasheet for details SW1 CSLR/FCK Selects channel for CS8414 channel status information *LO See CS8414 datasheet for details HDR8 External mute for AOUTA *ON OFF Mute Enabled Mute Disabled HDR7 External mute for AOUTB *ON OFF Mute Enabled Mute Disabled ENCTRL Enables / Disables parallel port ENABLE *DISABLE Invalid for Stand-Alone Mode Disables parallel port M0/AD0/CS CS4392 Mode Selection *HI LO See CS4392 datasheet for details M1/SDA/CDIN CS4392 Mode Selection HI *LO See CS4392 datasheet for details M2/SCL/CCLK CS4392 Mode Selection GND HI *DEM See CS4392 datasheet for details Allows the CS8414 to control de-emphasis M3 CS4392 Mode Selection HI *LO See CS4392 datasheet for details HDR1 to HDR6 Selects source of clocks and audio data *8414 EXT Selects CS8414 as source Digital I/O header becomes source HDR13,15 and HDR16,17 Selects whether the optional instrumentation amplifier is used or bypassed 1 *2 Bypassed Active Table 3. CDB4392 Jumper and Switch settings - STAND-ALONE MODE *Settings for Stand-Alone mode Notes: 6 The CDB4392 evaluation board is shipped from the factory configured for Control Port mode. DS459DB1 CDB4392 JUMPER PURPOSE POSITION FUNCTION SELECTED SW1 - M0 CS8414 mode selection *LO See CS8414 datasheet for details SW1 - M1 CS8414 mode selection *HI See CS8414 datasheet for details SW1 - M2 CS8414 mode selection *LO See CS8414 datasheet for details SW1 - M3 CS8414 mode selection *LO See CS8414 datasheet for details SW1 CSLR/FCK Selects channel for CS8414 channel status information *LO See CS8414 datasheet for details HDR8 External mute for AOUTA *ON OFF Mute Enabled Mute Disabled HDR7 External mute for AOUTB *ON OFF Mute Enabled Mute Disabled ENCTRL Enables / Disables parallel port *ENABLE DISABLE Enables parallel port Invalid for Control Port mode M0/AD0/CS AD0/CS *HI LO “Don’t Care” for Control Port mode M1/SDA/CDIN SDA/CDIN Pull-Up *HI LO SDA/CDIN pulled high Invalid for Control Port mode M2/SCL/CCLK SCL/CCLK Pull-Up GND *HI DEM Invalid for Control Port mode SCL/CCLK pulled high Invalid for Control Port mode M3 Not Functional HI *LO Must be low for Control Port mode HDR1 to HDR6 Selects source of clocks and audio data *8414 EXT Selects CS8414 as source Digital I/O header becomes source HDR13,15 and HDR16,17 Selects whether the optional instrumentation amplifier is used or bypassed 1 *2 Bypassed Active Table 4. CDB4392 Jumper and Switch settings - CONTOL PORT MODE *Settings for Control Port mode Notes: DS459DB1 The CDB4392 evaluation board is shipped from the factory configured for Control Port mode. 7 8 )LJ 'LJLWDO $XGLR ,QSXWV )LJ &6 'LJLWDO $XGLR 5;3 5HFHLYHU &RQQHFWLRQV 5;1 0&/. /5&. 6&/. 6'$7$ 5HVHW &LUFXLW )LJ &6 )LJ Figure 1. System Block Diagram and Signal Flow ,2IRU &ORFNV DQG'DWD )LJ &RQWURO 3RUW ,QWHUIDFH )LJ 6HOHFWDEOH ,QVWUXPHQWDWLRQ $PSOLILHU )LJ 6HOHFWDEOH ,QVWUXPHQWDWLRQ $PSOLILHU )LJ &KDQQHO% 2XWSXWV DQG0XWH &LUFXLW )LJ &KDQQHO$ 2XWSXWV DQG0XWH &LUFXLW )LJ CDB4392 DS459DB1 DS459DB1 .1UF GND RST MCLK M3 LRCK SCLK SDATA 8414_DEM C61 VL GND .1UF C59 VL GND GND 1 2 4 5 13 12 10 9 1 2 4 5 13 12 10 9 GND O3 O2 O1 O0 VCC GND O3 O2 O1 O0 VCC 74VHC125M /A0 B0 /A1 B1 /A2 B2 /A3 B3 U6 LOW ENABLE 74VHC125M /A0 B0 /A1 B1 /A2 B2 /A3 B3 U9 6 3 6 3 7 8 7 11 GND GND 11 14 8 14 DEM VL 49.9 R41 R10 499 R13 499 R14 499 GND M0 M1 M2 M3 MCLK LRCK SCLK SDATA 1 2 3 4 5 6 7 8 9 10 U7 CS4392 \RST VL SDATA/DSD_A SCLK/DSD_B LRCK/DSDMODE MCLK (DSD_CLK)M3 (SCL/CCLK)M2 (SDA/CDIN)M1 (AD0/\CS\)M0 Figure 2. CS4392 and Level Shifters M0/AD0/CS M1/SDA/CDIN M2/SCL/CCLK mclk lrck sclk sdata .1UF X7R C54 AMUTEC AOUTAAOUTA+ VA AGND AOUTB+ AOUTBBMUTEC CMOUT FILT+ 20 19 18 17 16 15 14 13 12 11 C20 10UF .1UF X7R C34 AOUTB+ AOUTBBMUTEC AMUTEC AOUTAAOUTA+ GND 1UF C21 .1UF X7R C17 GND 1UF C40 FERRITE_BEAD L1 VA+5 CDB4392 9 AOUTA+ AOUTA- 2.21K COG R16 3 2 6 5 R3 390PF COG 2.21K U12 7 4 .1UF C41 MC33078P 1 .1UF U12 C42 2.21K 390PF COG 8 VEE V- + - V+ VCC C3 C2 R2 - + MC33078P GND 1 2 HDR13 HDR3X1 HDR15 HDR3X1 Figure 3. Channel A Selectable Instrumentation Amplifier 300 AOUTA+ R39 AOUTA- 300 2200PF C55 10 GND R40 1 2 FILT FILT AOUTA+ AOUTA- CDB4392 DS459DB1 AOUTB+ AOUTB- 2.21K COG 3 4 VEE V- + - 390PF COG 2.21K U13 7 .1UF C43 MC33078P 1 .1UF U13 C44 2.21K 390PF COG 8 VCC V+ C15 R22 R21 2 - C39 R23 6 5 + MC33078P GND 1 2 1 2 FILT FILT HDR16 HDR3X1 HDR17 HDR3X1 Figure 4. Channel B Selectable Instrumentation Amplifier 300 AOUTB+ R42 AOUTB- 300 2200PF C56 DS459DB1 GND R43 AOUTB+ AOUTB- CDB4392 11 12 AMUTEC AMUTEC AOUTA+ AOUTA- 1.33K R26 1 4.42K R24 GND 2 3 GND 22UF C53 R15 1.5K R18 R17 715 1 2.32K GND VEE 3 .1UF C49 GND .1UF C48 MC33078P 1 U11 GND 470PF COG R25 MMUN2111LT1 Q3 R37 10K VA+5 2 4 8 VEE V- + - V+ 1500PF COG C5 3 2 VCC C6 2K C51 22UF Figure 5. Channel A Audio Output and Mute Circuit Q4 MMUN2211LT1 6800PF COG C14 GND GND 2200PF COG 4.99K R20 560 3 Q1 2SC2878 1 2 GND HDR1X2 HDR8 1 2 C7 R28 GND R5 47K GND 2 1 3 4 NC J3 CON_RCA_RA AOUTA CDB4392 DS459DB1 DS459DB1 BMUTEC AOUTB+ AOUTB- BMUTEC 1.33K R33 1 4.42K R34 2 3 GND GND GND 22UF C52 + - GND VEE 3 2 7 R36 MMUN2111LT1 Q6 MC33078P U11 470PF COG R27 10K VA+5 1500PF COG C22 5 6 C18 2K C50 22UF R19 OUTPUT FILTERS Figure 6. Channel B Audio Output and Mute Circuit 1 715 R32 R31 1.5K 2.32K R29 Q2 MMUN2211LT1 6800PF COG C28 GND 2200PF COG C4 4.99K 560 3 Q5 2SC2878 1 2 GND HDR1X2 HDR7 1 2 R35 GND R4 47K GND 2 1 3 4 NC J4 CON_RCA_RA AOUTB CDB4392 13 14 C9 6 D5 LED_RECT 13 D2 12 LED_RECT GND 11 5 3 1 GND .1UF D4 10 LED_RECT GND VCC 9 7 14 8 D6 LED_RECT 4 D3 LED_RECT SN74HC04N U8 VD+5 C16 VD+5 RXP GND C1 10UF VD1 C31 C26 R11 RXP RXN 1UF .1UF X7R 10 VA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CS8414 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SDATA HDR1X3 HDR1 LRCK HDR1X3 HDR2 VERF C CD/F1 CE/F2 CC/F0 SDATA CB/E2 ERF CA/E1 M1 /C0/E0 M0 VD+ VA+ DGND AGND RXP FILT RXN MCK FSYNC M2 SCK M3 CS12/FCK SEL U CBL U2 GND SCLK HDR1X3 HDR3 Figure 7. CS8414 Digital Audio Receiver VA+5 HDR1X3 HDR4 8414 EXTERNAL CLK SOURCE HDR1X3 HDR5 1 2 3 2 GND 47UH L4 .01UF RXN 1 2 3 D1 LED_RECT .01UF C10 .01UF 1 2 3 RN3 560 4 3 2 1 R30 75 C11 1 2 3 8414_DEM VD+5 TORX173 OPT1 GND 2 1 1 2 3 5 6 OPTICAL INPUT 3 NC 4 CON_RCA_RA J5 DIGITAL INPUT VD1 1UF C32 C33 .1UF X7R ERROR & FREQ R7 47.5K SW_B3W_1100 S4 R9 470 C27 MCLK RN4 47K CSLR/FCK CS8414_M2 .068UF X7R GND VA CS8414_M1 CS8414_M0 VD1 SW1 SW_DIP_5 5 4 3 2 1 GND CDB4392 DS459DB1 OPEN DS459DB1 8414 EXTERNAL CLK SOURCE HDR1X3 HDR6 VD+5 GND HDR5X2 J9 2 1 4 3 6 5 8 7 10 9 DIGITAL I/O (DSD_CLK)M3 SDATA LRCK SCLK MCLK GND 1 2 3 3 4 5 6 1 13 3 4 5 6 1 13 VCC GND B1 B2 B3 B4 VCC GND B1 B2 B3 B4 14 7 11 10 9 8 14 7 11 10 9 8 VD+5 GND .1UF C35 GND .1UF C24 VD+5 SDATA LRCK SCLK MCLK Figure 8. I/O for Clocks and Data SN74HC243N A1 A2 A3 A4 G1 G2 U10 SN74HC243N A1 A2 A3 A4 G1 G2 RN5 47K M3 VD+5 0 GND R1 U4 M3 HDR1X3 HDR14 1 2 3 CDB4392 15 16 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 DB25M_RA P1 VDPC+5 GND RN1 1K R38 5 RN2 4 RN2 3 RN2 2 RN2 1 RN2 6 RN2 GND 9 5 2 11 U16 9 11 GND 13 10 GND 12 M1/SDA/CDIN D7 12 RST SN74HCT125D 8 U16 SN74HCT125D GND BAT85 EN_SCL/CCLK SN74HCT125D 8 U15 SN74HCT125D 6 U15 SN74HCT125D 3 U15 10 GND 4 GND 7 1 GND 13 GND 14 VDPC+5 VCC U15 SN74HCT125D 4.7K 12 4.7K 13 4.7K 14 4.7K 15 4.7K 16 4.7K 11 4.7K PC PORT .1UF C63 VDPC+5 GND .1UF C62 U1 VCC GND 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 5 2 GND 4 7 1 14 GND GND VCC VDPC+5 SN74HC574DW 1D 2D 3D 4D 5D 6D 7D 8D /OE CLK GND VDPC+5 .1UF C47 SN74HCT125D 6 U16 SN74HCT125D 3 U16 20 10 19 18 17 16 15 14 13 12 VDPC+5 EN_SCL/CCLK Figure 9. Control Port Interface RST GND VDPC+5 2 3 4 5 6 7 8 9 1 11 HDR10 HDR1X3 ENABLE 1 2 3 ENCTRL DISABLE GND .1UF C46 VD+5 1 2 4 5 13 12 10 9 GND O3 O2 O1 O0 VCC 74VHC125M /A0 B0 /A1 B1 /A2 B2 /A3 B3 U5 6 3 8 7 11 14 GND VL C45 GND R6 2K 1 2 3 M0/AD0/CS HDR1X3 HDR11 GND .1UF R8 2K M2/SCL/CCLK GND HDR4X2 HDR9 1 2 3 4 5 6 7 8 HDR21 1 2 HDR22 1 2 HDR23 1 2 GND HDR1X3 HDR12 1 2 3 DEM VL GND M1/SDA/CDIN R12 2K VL M2/SCL/CCLK M0/AD0/CS M1/SDA/CDIN CDB4392 DS459DB1 GND L2 VDPC+5 .1UF 10UF C19 C8 VA+5 VD+5 FB L3 FB .1UF C13 47UF C25 C12 47UF GND GND GND 100PF C23 RST GND GND C57 GND .1UF C29 47UF Z5 P6KE6V8P VL 1 U3 DS1233-10 J11 CON_BANANA VL/1.8 - 5V RST Vcc RST 2 GND 1 VCC C30 47UF Z3 VD+5 C37 J8 CON_BANANA VCC/+12 Figure 10. Power Supply and Reset Circuitry J7 J6 P6KE6V8P CON_BANANA CON_BANANA Z1 GND S1 SW_B3W_1100 DS459DB1 +5V .1UF P6KE13 GND Z4 C38 .1UF C36 47UF P6KE13 VEE J10 CON_BANANA VEE/-12 CDB4392 3 17 CDB4392 Figure 11. Silkscreen Top 18 DS459DB1 CDB4392 Figure 12. Top Side DS459DB1 19 CDB4392 Figure 13. Bottom Side 20 DS459DB1 • Notes •