A3974: DMOS Dual Full-Bridge PWM Motor Driver

A3974
DMOS Dual Full-Bridge PWM Motor Driver
Discontinued Product
These parts are no longer in production The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: May 3, 2010
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, refer to your Allegro sales representative.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A3974
DMOS Dual Full-Bridge PWM Motor Driver
Features and Benefits
Description
▪ ±1.5 A, 50 V continuous output rating
▪ Low rDS(on) DMOS output drivers
▪ Programmable slow, fast, and mixed current-decay modes
▪ Serial-interface controls chip functions
▪ Synchronous rectification for low power dissipation
▪ Internal UVLO and thermal shutdown circuitry
▪ Crossover-current protection
▪ Sleep and idle modes
Designed for pulse width modulated (PWM) current control
of two DC motors, the A3974 is capable of output currents to
±1.5 A and operating voltages to 50 V. Internal fixed off-time
PWM current-control timing circuitry can be programmed via
a serial interface to operate in slow, fast, and mixed currentdecay modes.
Independent ENABLE input terminals are provided for use
in controlling the speed and torque of each DC motor with
externally applied PWM control signals.
Synchronous rectification circuitry allows the load current
to flow through the low rDS(on) of the DMOS output driver
during the current decay. This feature will eliminate the need
for external clamp diodes in most applications, saving cost
and external component count, while minimizing power
dissipation.
Package: 44-pin PLCC with internally
fused pins (suffix ED)
Internal circuit protection includes thermal shutdown with
hysteresis, undervoltage monitoring of VDD and the charge
pump, and crossover-current protection. Special power-up
sequencing is not required.
Not to scale
The A3974 is supplied in a 44-pin plastic PLCC with 3 internally
fused pins on each side, for maximum heat dissipation. The fused
pins are at ground potential and need no electrical isolation.
ENABLE1
NC
OUT1B
42
41
40
GND
LOAD
43 SUPPLY1
GND
1
GND
2
44
NC
SENSE1
4
NC
5
3
OUT1A
6
Pin-out Diagram
VBB1
NC
7
STROBE
8
CP2
37
CP1
36
CP
GND 11
35
GND
GND 12
34
GND
GND 13
33
GND
CLOCK
9
DATA 10
PROGRAM
PWM TIMER
CHARGE PUMP
NC
38
SERIAL PORT
39
LOGIC
REF1 14
REF2 15
LOGIC
16
SUPPLY
NC
PROGRAM
PWM TIMER
LOGIC
VDD
17
32
OSC
31
SLEEP
30
VREG
29
NC
29319.35C
OUT2B 28
NC 27
25
ENABLE2 26
LOAD
SUPPLY2
23
GND 24
GND
GND 22
21
NC 20
SENSE2
NC 19
OUT2A 18
VBB2
Dwg. PP-073
A3974
DMOS Dual Full-Bridge PWM Motor Driver
Selection Guide
Part Number
A3974SED-T
A3974SEDTR-T
Packing
27 pieces per tube
450 pieces per reel
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
Units
Load Supply Voltage
VBB
50
V
Logic Supply Voltage
VDD
7.0
V
Logic Input Voltage Range
VIN
Continuous
–0.3 to VDD+ 0.3
V
Pulsed, tw < 30 ns
–1.0 to VDD+ 1.0
V
Reference Voltage
Sense Voltage (DC)
Output Current
VREF
VS
IOUT
3
V
Continuous
0.5
V
Pulsed, tw < 1 μs
2.5
V
Output current rating may be limited by duty
cycle, ambient temperature, and heat sinking.
Under any set of conditions, do not exceed the
specified current rating or a junction temperature
of 150°C.
±1.5
A
Operating Ambient Temperature
TA
–20 to 85
ºC
Maximum Junction Temperature
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Storage Temperature
Range S
Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic
Package Thermal Resistance
Test Conditions*
Symbol
RθJA
4-layer PCB based on JEDEC standard
RθJT
Value Units
22
ºC/W
6
ºC/W
*Additional thermal information available on the Allegro website.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A3974
DMOS Dual Full-Bridge PWM Motor Driver
FUNCTIONAL BLOCK DIAGRAM
VBB1
VDD
UNDERVOLTAGE &
FAULT DETECT
CP2
CP1
CHARGE PUMP
BANDGAP
VDD
CREG
TSD
CP
+
LOGIC
SUPPLY
LOAD
SUPPLY1
CHARGE
PUMP
BANDGAP
REGULATOR
ENABLE1
OUT1A
GATE DRIVE
PHASE
SYNC RECT MODE
SYNC RECT DISABLE
MODE
CONTROL LOGIC
VREG
OUT1B
SENSE1
CS1
ZERO CURRENT DETECT
FIXED OFF
PROGRAMMABLE BLANK
DECAY
RS1
PWM TIMER
CURRENT SENSE
FIXED OFF
ENABLE2
PHASE
ENABLE
SYNC RECT MODE
SYNC RECT DISABLE
PWM MODE INT
PWM MODE EXT
PROGRAMMABLE BLANK
DECAY
PWM TIMER
SLEEP
MODE
REFERENCE
BUFFER &
DIVIDER
SERIAL
PORT
REF1
VREF
LOAD
SUPPLY2
CHARGE
PUMP
+
VBB2
OUT2A
GATE DRIVE
OSC
CLOCK
DATA
STROBE
OUT2B
CONTROL LOGIC
SENSE2
TO PWM TIMER
CS2
ZERO CURRENT DETECT
RS2
CURRENT SENSE
REFERENCE
BUFFER &
DIVIDER
REF2
VREF2
Dwg. FP-048-1
Copyright © 2001 Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A3974
DMOS Dual Full-Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, fPWM < 50 kHz (unless
otherwise noted).
Characteristic
Symbol
Test Conditions
Min.
Limits
Typ. Max.
Units
Output Drivers
Load Supply Voltage Range
Output Leakage Current
Output ON Resistance
Body Diode Forward Voltage
Load Supply Current
VBB
IDSS
rDS(on)
VF
IBB
Operating
15
—
50
V
During sleep mode
0
—
50
V
VOUT = VBB
—
<1.0
20
μA
VOUT = 0 V
—
<-1.0
-20
μA
Source driver, IOUT = -1.5 A
—
0.5
0.55
Ω
Sink driver, IOUT = 1.5 A
—
0.315
0.35
Ω
Source diode, IF = 1.5 A
—
—
1.2
V
Sink diode, IF = 1.5 A
—
—
1.2
V
fPWM < 50 kHz
—
4.0
7.0
mA
Charge pump on, outputs disabled
—
2.0
5.0
mA
Sleep or idle mode
—
—
20
μA
Operating
4.5
5.0
5.5
V
Control Logic
Logic Supply Voltage Range
VDD
Logic Input Voltage
VIN(1)
2.0
—
—
V
VIN(0)
—
—
0.8
V
Logic Input Current
IIN(1)
VIN = 2.0 V
—
<1.0
±20
μA
(except ENABLE)
IIN(0)
VIN = 0.8 V
—
<1.0
±20
μA
ENABLE Input Current
IEN(1)
VEN = 2.0 V
—
40
100
μA
IEN(0)
VEN = 0.8 V
—
16
30
μA
OSC Input Frequency
fOSC
2.9
—
6.1
MHz
OSC Input Duty Cycle
—
40
—
60
%
OSC Input Hysterisis
ΔVIN
200
—
400
mV
Reference Input Voltage Range
VREF
0
—
2.6
V
Operating
continued next page ...
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A3974
DMOS Dual Full-Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, fPWM < 50 kHz (unless
otherwise noted), continued.
Characteristic
Control Logic (continued)
Symbol
Reference Input Current
IREF
Reference Input Offset Voltage
VIO
Reference Divider Ratio
Gain (Gm) Error (note 3)
Propagation Delay Time
Crossover Delay Time
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
Logic Supply Current
Test Conditions
Limits
Typ. Max.
Units
—
—
±1.0
μA
—
±10
—
mV
D16 = 1
—
10
—
—
D16 = 0
—
5.0
—
—
VREF = 2.6 V, D16 = 0
—
0
±4.0
%
VREF = 0.5 V, D16 = 0
—
0
±14
%
VREF = 2.6 V, D16 = 1
—
0
±4.0
%
VREF = 0.5 V, D16 = 1
—
0
±10
%
50% TO 90%:
PWM change to source on
PWM change to source off
PWM change to sink on
PWM change to sink off
600
50
600
50
750
150
750
150
1000
350
1000
350
ns
ns
ns
ns
SR enabled
300
600
1000
ns
TJ
—
165
—
°C
ΔTJ
—
15
—
°C
3.9
4.2
4.45
V
0.05
0.10
—
V
fPWM < 50 kHz
—
—
10
mA
Outputs off
—
—
8.0
mA
Idle mode (D18 = 1, D19 = 0)
—
—
1.5
mA
Sleep mode (inputs below 0.5 V)
—
—
100
μA
VREF/VS
EG
tpd
tCOD
VUVLO
VREF = 2.6 V
Min.
Increasing VDD
ΔVUVLO
IDD
NOTES: 1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
3. EG = [(VREF/Range) - VS]/(VREF/Range).
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A3974
DMOS Dual Full-Bridge PWM Motor Driver
FUNCTIONAL DESCRIPTION
Serial Interface. The A3974SED is controlled via a 3-wire
(clock, data,strobe) serial port. The programmable functions
allow maximum flexibility in configuring the PWM to the motor drive requirements. The serial data is written as two 20-bit
words: 1 bit to select the word and 19 bits of data. The data is
clocked in starting with D19.
D2 – D6 Fixed Off Time. This five-bit word sets the fixed
off-time for the internal PWM control circuitry. The off-time is
defined by
Word 0 Bit Assignments
For example, with an oscillator frequency of 4 MHz, the fixed
off-time will be adjustable from 1.75 μs to 63.75 μs in increments of 2 μs.
Select Word 0 (D18 = 0)
Bit
Function
D0
Bridge 1 blank time LSB
D1
Bridge 1 blank time MSB
D2
Bridge 1 off-time LSB
D3
Bridge 1 off-time bit 1
D4
Bridge 1 off-time bit 2
D5
Bridge 1 off-time bit 3
D6
Bridge 1 off-time MSB
D7
Bridge 1 fast-decay time bit LSB
D8
Bridge 1 fast-decay time bit 1
D9
Bridge 1 fast-decay time bit 2
D10
Bridge 1 fast-decay time MSB
D11
Bridge 1 sync. rect. control
D12
Bridge 1 sync. rect. control
D13
Bridge 1 external PWM mode
D14
Bridge 1 enable
D15
Bridge 1 phase
D16
Bridge 1 reference range select
D17
Bridge 1 internal PWM mode
D18
Word select = 0
D19
Test mode
D0 – D1 Blank Time. The current-sense comparator is blanked
when any output driver is switched on, according to the table
below. fosc is the oscillator input frequency.
D1
0
0
1
1
D0
0
1
0
1
Blank Time
4/fOSC
6/fOSC
12/fOSC
24/fOSC
toff =(8 [1 + N]/fOSC) - 1/fOSC
where N = 0 .... 31
D7 – D10 Fast Decay Time. This four-bit word sets the fastdecay portion of the fixed off-time for the internal PWM control
circuitry. This will only have impact if mixed-decay mode is
selected (via bit D17). For tfd > toff, the device will effectively
operate in fast-decay mode. The fast-decay portion is defined by
tfd = (8[1 + N]/fOSC] - 1/fOSC
where N = 0 .... 15
For example, with an oscillator frequency of 4 MHz, the fastdecay time will be adjustable from 1.75 μs to 31.75 μs in increments of 2 μs.
D11 – D12 Synchronous Rectification.
D12
0
0
1
1
D11
0
1
0
1
Synchronous Rectifier
Disabled
Low side only
Active
Passive
The different modes of operation are described in the synchronous rectification section of the functional description.
D13 External PWM Decay Mode. This bit determines the
current-decay mode when using ENABLE chopping for external
PWM current control.
D13
0
1
Mode
Fast
Slow
continued next page ...
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A3974
DMOS Dual Full-Bridge PWM Motor Driver
FUNCTIONAL DESCRIPTION (continued)
D14 Enable Logic. This bit, in conjuction with ENABLE,
determines if the output drivers are in the chopped or on state.
ENABLE1
0
1
0
1
D14
0
0
1
1
Mode
Chopped
On
On
Chopped
D15 Phase Logic. This bit determines if the device is operating in the forward or reverse state.
D15
State
OUTA
OUTB
0
1
Reverse
Forward
L
H
H
L
D16 Gm Range Select. This bit determines if VREF is divided
by 5 or 10.
D16
0
1
Divider
÷10
÷5
D17 Bridge 2 Mode. This bit determines slow or mixed decay
for internal current-control operation.
D17
0
1
Decay Mode
Mixed
Slow
D19 Test Mode. This bit is reserved for testing and should
never be changed by the user. Default (low) operates the device
in normal mode.
Word 1 Bit Assignments
Select Word 1 (D18 = 1)
Bit
Function
D0
Bridge 2 blank time LSB
D1
Bridge 2 blank time MSB
D2
Bridge 2 off-time LSB
D3
Bridge 2 off-time bit 1
D4
Bridge 2 off-time bit 2
D5
Bridge 2 off-time bit 3
D6
Bridge 2 off-time MSB
D7
Bridge 2 fast-decay time bit LSB
D8
Bridge 2 fast-decay time bit 1
D9
Bridge 2 fast-decay time bit 2
D10
Bridge 2 fast-decay time bit MSB
D11
Bridge 2 sync. rect. control
D12
Bridge 2 sync. rect. control
D13
Bridge 2 external PWM mode
D14
Bridge 2 enable
D15
Bridge 2 phase
D16
Bridge 2 reference range select
D17
Bridge 2 internal PWM mode
D18
Word select = 1
D19
Idle mode
D0 - D17. Identical definitions as Word 0, with Word 1 selected.
Data is written to Full Bridge 2.
D19 Idle Mode. The device can be placed in a low-power
“idle” mode by writing a “0” to D19. The outputs will be disabled, the charge pump will be turned off, and the device will
draw a lower load supply currrent. The undervoltage monitor
circuit will remain active. D19 should be programmed high for
1 ms before attempting to enable any output driver.
continued next page ...
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A3974
DMOS Dual Full-Bridge PWM Motor Driver
FUNCTIONAL DESCRIPTION (continued)
VREG. This internally generated supply voltage is used to operate the sink-side DMOS outputs. VREG is internally monitored
and in the case of a fault condition, the outputs of the device are
disabled. The VREG terminal should be decoupled with a 0.22 μF
capacitor to ground.
Charge Pump. The charge pump is used to generate a supply
voltage greater than VBB to drive the source-side DMOS gates.
A 0.22 μF ceramic capacitor should be connected between CP1
and CP2 for pumping purposes. A 0.22 μF ceramic capacitor
should be connected between VCP and VBB to act as a reservoir
to run the high-side DMOS devices. The CP voltage is internally
monitored and in the case of a fault condition, the outputs of the
device are disabled.
Shutdown. In the event of a fault due to excessive junction
temperature, or low voltage on CP or VREG, the outputs of the
device are disabled until the fault condition is removed. At
power up, or in the event of low VDD, the UVLO circuit disables
the drivers and resets the data in the serial port to all zeros.
Current Regulation. Load current is regulated by an internal fixed off-time PWM control circuit. When the outputs of
the DMOS H-bridge are turned on, the current increases in the
motor winding until it reaches a trip value determined by the
external sense resistor (RS), the applied analog reference voltage
(VREF), and serial data bit D16:
When D16 = 0 ....................... ITRIP = VREF/10RS
When D16 = 1 ....................... ITRIP = VREF/5RS
At the trip point, the sense comparator resets the source-enable
latch, turning off the source driver (except in the case of lowside only mode where the sink driver is turned off). The load
inductance then causes the current to recirculate for the serialport programmed fixed off-time period. The current path during
recirculation is determined by the configuration of slow/mixeddecay mode (D17) and the synchronous rectification control bits
(D11 and D12).
Sleep Mode. The input terminal SLEEP is dedicated to putting
the device into a minimum current draw mode. When asserted
low, the serial port will be reset to all zeros and all circuits will
be disabled.
PWM Timer Function. The PWM timer is programmable via
the serial port (bits D2 – D10) to provide fixed off-time PWM
signals to the control circuitry. In mixed current-decay mode,
the first portion of the off time operates in fast decay, until the
fast-decay time count is reached (serial bits D7 – D10), followed
by slow decay for the rest of the off-time period (bits D2 – D6).
If the fast-decay time is set longer than the off-time, the device
effectively operates in fast-decay mode. Bit D17 selects mixed
or slow decay.
Synchronous Rectification. When a PWM off cycle is triggered, either by an ENABLE chop command or internal fixed
off-time cycle, load current will recirculate according to the
decay mode selected by the control logic. After a short crossover
delay, the A3974 synchronous rectification feature will turn on
the appropriate MOSFET (or pair of MOSFETs for the mixed
decay portion of the off-time) during the current decay and effectively short out the body diodes with the low rDS(on) driver.
This will lower power dissipation significantly and can eliminate
the need for external Schottky diodes.
Synchronous rectification can be configured in active mode, passive mode, low side only, or disabled via the serial port (bits D11
and D12). The active mode prevents reversal of load current by
turning off synchronous rectification when a zero current level
is detected. Passive mode will allow reversal of current but will
turn off the synchronous rectifier circuit if the load current inversion ramps up to the current limit set by
VREF/10RS (when D16 = 0) or VREF/5RS(when D16 = 1).
Low side only mode will switch the low-side MOSFETs on during the off time to short out the current path through the MOSFET body diode. With this setting, the high-side MOSFETs will
not synchronously rectify so four external diodes from output
to supply are recommended. This mode is intended for use with
high-power applications where it is desired to save the expense
of two external diodes per bridge. In this mode, the sink-side
MOSFETs are chopped during the PWM off time. In all other
cases, the source-side MOSFETs are chopped in response to a
PWM OFF command.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A3974
DMOS Dual Full-Bridge PWM Motor Driver
APPLICATIONS INFORMATION
Current Sensing. To minimize inaccuracies in sensing the
ITRIP current level caused by ground-trace IR drops, the sense
resistor should have an independent ground return to a ground
terminal of the device. For low-value sense resistors, the IR
drops in the PCB sense traces of the resistor can be significant
and should be taken into account. The use of sockets should be
avoided as they can introduce variation in RS due to their contact
resistance.
The maximum value of RS is given as RS = 0.5/ITRIPMAX.
Braking. The braking function is implemented by driving the
device in slow-decay mode via serial port bit D13, enabling
synchronous rectification via bits D11 and D12, and applying
an enable chop command with the combination of D14 and the
ENABLE input terminal. Because it is possible to drive current
in both directions through the DMOS switches, this configuration effectively shorts out the motor-generated BEMF as long as
the ENABLE chop mode is asserted. It is important to note that
the internal PWM current-control circuit will not limit the current when braking, because the current does not flow through the
sense resistor. The maximum brake current can be approximated
by VBEMF/RL. Care should be taken to ensure that the maximum
ratings of the device are not exceeded in worst-case braking situations of high speed and high inertial loads.
Thermal protection. Circuitry turns off all drivers when the
junction temperature reaches 165°C typically. It is intended only
to protect the device from failures due to excessive junction
temperatures and should not imply that output short circuits are
permitted. Thermal shutdown has a hysteresis of approximately
15°C.
Layout. The printed wiring board should use a heavy ground
plane. For optimum electrical and thermal performance, the
driver should be soldered directly onto the board. The ground
side of RS should have an individual path to a ground terminal of
the device. This path should be as short as is possible physically
and should not have any other components connected to it. The
load supply terminal, VBB, should be decoupled with an electrolytic capacitor (>47 μF is recommended) placed as close to the
device as is possible.
Serial Port Write Timing Operation. Data is clocked into
shift register on the rising edge of CLOCK signal. Normally,
STROBE will be held high, and only will be brought low to
initiate a write cycle. Refer to diagram below and specification
table for timing requirements.
A. Minimum Data Setup Time .........................................15 ns
B. Minimum Data Hold Time ...........................................10 ns
C. Minimum Setup Strobe to Clock Rising Edge ............50 ns
D. Minimum Clock High Pulse Width .............................50 ns
E. Minimum Clock Low Pulse Width ..............................50 ns
F. Minimum Setup Clock Rising Edge to Strobe .............50 ns
G. Minimum Strobe Pulse Width .....................................50 ns
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
A3974
DMOS Dual Full-Bridge PWM Motor Driver
Terminal List
Terminal Name
GND
SENSE1
NC
OUT1A
NC
STROBE
CLOCK
DATA
GND
REF1
REF2
LOGIC SUPPLY
NC
OUT2A
NC
SENSE2
GND
LOAD SUPPLY2
ENABLE2
NC
OUT2B
NC
VREG
SLEEP
OSC
GND
CP
CP1 & CP2
NC
OUT1B
NC
ENABLE1
LOAD SUPPLY1
GND
Terminal Description
Power and logic ground terminals
Sense resistor terminal for bridge 1
No (internal) connection
DMOS H-bridge 1 – output A
No (internal) connection
Logic input for serial Interface
Logic input for serial Interface
Logic input for serial Interface
Power and logic ground terminals
Gm reference input voltage – bridge 1
Gm reference input voltage – bridge 2
VDD, the low voltage (typically 5 V) supply
No (internal) connection
DMOS H-bridge 2 – output A
No (internal) connection
Sense resistor pin for bridge 2
Power and logic ground terminals
VBB2, the high current, 20 V to 50 V,
supply for bridge 2
Logic input for bridge 2 – enable control
No (internal) connection
DMOS H-bridge 2 – output B
No (internal) connection
Regulator decoupling capacitor (typ. 0.22 μF)
Logic input for SLEEP mode
Logic-level oscillator (square wave) input
Power and logic ground terminals
Reservoir capacitor (typically 0.22 μF)
The charge pump capacitor (typically 0.22 μF)
No (internal) connection
DMOS H-bridge 1 – output B
No (internal) connection
Logic input for bridge 1 – enable control
VBB1, the high current, 20 V to 50 V,
supply for bridge 1
Power and logic ground terminals
Terminal Number
1, 2
3
4, 5
6
7
8
9
10
11, 12, 13
14
15
16
17
18
19, 20
21
22, 23, 24
25
26
27
28
29
30
31
32
33, 34, 35
36
37 & 38
39
40
41
42
43
44
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
A3974
DMOS Dual Full-Bridge PWM Motor Driver
Package EB, 44-pin PLCC
17.53 ±0.13
16.59 ±0.08
0.51
2 1 44
7.75 ±0.36
A
17.53 ±0.13 16.59 ±0.08
7.75 ±0.36
0.74 ±0.08
4.57 MAX
44X
SEATING
PLANE
0.10 C
0.43 ±0.10
C
1.27
7.75 ±0.36
7.75 ±0.36
For Reference Only
(reference JEDEC MS-018 AC)
Dimensions in millimeters
Internally fused pins 44, 1 and 2; 11-13; 22-24; and 33-35
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
Copyright ©2001-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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