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The following document contains information on Cypress products.
CM44-10105-6ET2
Errata
This errata sheet is for MB90590 Series Hardware Manual Rev.6 (CM44-10105-6E)
F2MC-16LX
16-BIT MICROCONTROLLER
MB90590 Series
HARDWARE MANUAL
2009.1.9
:Corrected part
Updated
2009/
1/9
Page
487
Item
APPENDIX
B
Description
■Table B.9-20 XCH Ri, ea Instruction (First Byte = 7EH) is changed.
・Error
Item "A"
Line of +A
"W2+d16,A"
・Correct
Item "A0"
Line of +A "@RW2+d16"
1/1
Corrections of Hardware Manual
MB90590 –
hm90590-cm44-10105-6e-corr-x1-00
© Fujitsu Microelectronics Europe GmbH
Addendum, MB90590 Hardware Manual (CM44-10105-6E)
This is the Addendum for the Hardware Manual CM44-10105-6E of the MB90590
microcontroller series. It describes all known discrepancies of the MB90590
microcontroller series Hardware Manual.
Version Chapter/Page
No.
Description/Correction
11.07.02
1.00
Chapter 19
HWM90590002
11.07.02
1.00
1.8
HWM90590003
30.08.02
1.01
1.8
CAN, ‘Hit and Away’ description
added
Information about Pin state
behaviour during Power-on, date
code added
Series Port Output in Standby
Mode
Ref. Number
Date
(Text Link)
dd.mm.yy
HWM90590001
hm90590-cm44-10105-6e-corr-x1-00.doc 1 / 8
HWM90590001
Chapter 19 CAN
‘Hit and Away’ Description:
Affected Parts:
MB90V590/A/G, MB9059x/A/G, MB90F59x/A/G
Caution for disabling Message Buffers by BVAL bits
1 Caution for
Reception
1.1 Behaviour
If there is a complete (no error until 6th bit of EOF) incoming message that
have passed the acceptance filter, then this message is stored into a message
buffer x (with x=0…15). If this store operation coincides with reset operation
of the corresponding BVAL bit (BVALx=0), the received message will be stored
into the message buffer 0 regardless of register settings. Note that this
coincidence has to happen within a specific CAN-clock cycle (see event 2 in
figures). Hence, the probability is very low.
If transmission request of buffer 0 is set (TREQ0=1), the above-mentioned
behaviour will lead to the following transmission of a message. This message
consists of the received ID, DLC and Data together with original IDE and RTR
bits set of the message buffer 0.
However, if there are two or more message buffers with passing acceptance
filers for the incoming message and only buffer x is disabled, the message
will be stored into the 2nd prioritised message buffer.
If there are two or more message buffers with passing acceptance filers for
the incoming message and all those buffers are disabled, the message will be
stored into buffer 0.
1.2 Operation to avoid
When disabling message buffers by the BVAL register, it must be avoided that
the write operation to the BVAL register coincides with the store operation of
the received message in the CAN Controller.
The following diagram illustrates the timing to be avoided for the BVAL write
operation.
hm90590-cm44-10105-6e-corr-x1-00.doc 2 / 8
DLC
Data
dlc
data
Id-Arbitration
CRC
ACK
ID
RTR
ID
SRR
IDE
SOF
idle
EOF
ITM
ID, DLC and DTR are copied to
buffer 0
no RX-flags are set
LEIR (buffer pointer) set to 0
determine one or more
buffers with Hit
16 cycles
64 cycles
3 4
Away
1 Hit
ACK
DEL
idle
EOF6 EOF5 EOF4 EOF3 EOF2 EOF1 EOF0
SYNC_SEG
TSEG1
TSEG2
sample point
RS=1? 0
2
disable all buffers x to y with hit exactly one
CAN-clock cycle after sample point (BVALx..y=0)
c
d
e
f
CAN-controller determines buffers, which can store the message, because
their acceptance filters had been passed.
Software disable all buffers with hit exactly one CAN-clock cycle after
the sample point of EOF1.
CAN-controller stores received ID, DLC and data in buffer 0 regardless
of the buffers determined in c.
CAN-Controller sets LEIR to point to buffer 0 but RX-flags (RCR, ROVR,
RRTRR) are not set.
f
2. Caution for
Transmission
2.1 Behaviour
When there is a pending transmission of buffer x and the CAN bus status is in
Intermission or in Bus Idle, the CAN-controller will load the message from
buffer x in order to send it. If this load operation coincides with disabling
the pending message buffer x by clearing the BVAL bit, this results in
transmission of a Standard message. This message consists of RTR=0, IDE=0,
DLC, 11 ID bits and Data stored in the message buffer 0.
Note that this coincidence has to happen with in a specific CAN-clock cycle.
Hence, the probability is very low. The position of that cycle depends also on
previous frame reception and occurrence of error frames.
2.2 Operation to avoid
When disabling message buffers by the BVAL register, it must be avoided that
the write operation to the BVAL register coincides with the preparation for
the next transmission in the CAN Controller.
The following diagram illustrates the timing to be avoided for the BVAL write
operation.
hm90590-cm44-10105-6e-corr-x1-00.doc 3 / 8
DLC
Data
dlc
data
CRC
ACK
ID
RTR
ID
SRR
IDE
SOF
idle
...
EOF
ITM
idle
5
Id-Arbitration
TREQx=1
TREQx=1
6
EOF-SOF
BVALx=0
BVALx=0
7
Hit
transmit standard data frame with
ID, DLC and data of buffer 0
g
h
i
j
8
Away
LEIR set to buffer 0
TCR remains unchanged
Software requests transmission of buffer x by setting TREQx.
Software disables the buffer x by clearing BVALx.
CAN-controller transmits a standard data frame with ID, length code and
data of buffer 0.
After completion of frame only LEIR is updated for buffer 0. However,
TCR is not set (neither for buffer 0 nor for buffer x).
3. Correct Operation
3.1 Operation for re-configuring receive message buffers
Depending on CAN applications, it may be necessary to re-configure message
buffers after receiving messages through the already active CAN communication.
While the CAN bus is active, it is necessary to follow one of the two
operations described below to re-configure message buffers by ID, AMS and
AMR0/1 register settings. "Active" means that read value of the HALT bit is 0
and the CAN Controller is ready to receive and transmit messages.
1.1.1 Use of HALT bit
Write 1 to the HALT bit and read it back for checking the result is 1. Then
change settings for the ID/AMS/AMR0/1 registers.
1.1.2 No use of Message Buffer 0
Do not use the message buffer 0. In other words, disable message buffer
(BVAL=0), prohibit receive interrupt (RIE=0) and do not request transmission
(TREQ=0).
3.2 Operation for processing received message.
When reading a received message from a message buffer, consideration must be
given for possible over-write operation by next incoming messages.
Disabling receive operation by the BVAL bit must not be used for this purpose.
Use the ROVR bit for checking, if over-writing has been performed. For
details, refer to description of ROVR in the hardware manual.
hm90590-cm44-10105-6e-corr-x1-00.doc 4 / 8
3.3 Cancellation of transmission request
Do not use the BVAL bit for suppressing/cancellation of transmission request.
The TCANR bit is prepared for this purpose.
3.4 Composing transmission message
When composing a transmission message by writing to ID, data and other
registers, the message buffer should be disabled by the BVAL bit.
In this case, the BVAL bit should reset (BVAL=0) after checking if the TREQ
bit is 0 or after completion of the previous message transmission (TC=1).
4. Example of avoiding Hit-And-Away
1. Do not use message buffer 0. Keep it always disabled (BVAL0 = 0).
By not using buffer 0 the processing of wrongly received messages in buffer
0 is avoided. Even if data are received in this buffer, they have no
influence.
2. Set an unused 11-Bit identifier in buffer 0.
"Unused" means that the identifier has no meaning to any node in the
network. If an invalid standard data frame is sent according to the
condition described in "0
2. Caution for Transmission", that frame must not cause misoperation of
other nodes.
3. Use overrun test while processing a received message.
After temporarily saving received message, test for overrun (ROVRR). If
overrun occurred, read the buffer again, because the read data before
overrun could be inconsistent.
4. Wait for completion of transmission.
A buffer must not be disabled by clearing the BVAL-flag, as long as there
is a pending transmission. Easiest way to wait for transmission completion
is to use transmission interrupt but polling of TREQ is also possible.
hm90590-cm44-10105-6e-corr-x1-00.doc 5 / 8
HWM90590002
Power-On Reset
Output “unknown value” , when the power supply Is turned on If F2MC16LX is used. (Note)
1.Device covered
MB90V590A, MB90F591A, MB90F594A/G,
MB90591, MB90594/G
2. Note:
During testing it has been found that some port pins may enter an
undefined state during power on. By asserting RSTx during the power on
reset (217 cycles of main clock) port pins can be forced to high
impedance.
The following Ports will output a High Impedance (Hi-z) at the terminal
when the power supply is turned on when PONR and RSTX = 1:
P20 – P45, P56, P60 – P67, P90 – P95
The following ports will output High Impedance (High-Z) on RSTX or with
the End of PONR and Start of internal clocks:
P00 – P05, P14 – P15, P46 – P55, P57, P70 – P87
The following Ports will output High Impedance (high-Z) with the End of
PONR and Start of the internal Clock. RSTX does not force the pins to
high-Z during power on.
P06 – P13, P16 – P17
Note:
This workaround will work for Mode pin setting 011 (Single chip,
Internal ROM external bus), 110 (Burn_In ROM), 111 (EPROM mode)
Fixed version:
MB90F594G
MB90594G
: fixed after date code 0132-K02
: fixed after date code 0135-K09
MB90F591G
MB90591G
: not affected
: not affected
hm90590-cm44-10105-6e-corr-x1-00.doc 6 / 8
The following diagram shows the timing chart in detail.
Oscillation stabilization time
Under “power-on reset”
Vcc (power supply terminal)
“power-on reset” signal
RSTX (external asynchronous reset)
signal
RST (Internal reset) signal
Program Execution
MCLK (main clock) signal
Internal operation clock signal
Hi-z
Output port 0, 1
output “unknown value”
How to output “Hi-z” under “power-on reset”
Input external reset over 217 x oscillation clock frequency
RSTX (external asynchronous reset)
signal
Output port 0, 1
Hi-z
Timing chart
Under “power-on reset” 217 x oscillation clock frequency
(8.192ms in case of oscillation clock frequency = 16MHz)
Waiting time to be stabilized oscillation 218 x oscillation clock frequency
(16.384ms in case of oscillation clock frequency = 16MHz).
hm90590-cm44-10105-6e-corr-x1-00.doc 7 / 8
HWM90590003
Port Output in Standby Mode
Problems
The following problem has been found for the MB90590 Series of products for
some pins serving as a resource output and general-purpose port when a
transition is made to a standby mode (stop mode or time-base timer mode) with
the resource output enabled, the pins are not placed in the Hi-Z state
although the pin state setting bit is Hi-Z (SPL bit = 1).
When a transition is made to a standby mode with the following states
established, the pins shown in the table below are not placed in the Hi-Z
state and they remain in the resource output state.
State setting: Resource output enabled
SPL bit = 1 (Port state is Hi-Z setting in standby mode)
Products
MB90V590A/G,
MB90F591A/G,
MB90591/G,
MB90F594A/G,
MB90594/G
Pins not placed in Hi-Z state in standby mode
P06/OUT0, P07/OUT1, P10/OUT2, P11/OUT3, P12/OUT4, P13/OUT5,
P15/TX1,
P16/SGO, P17/SGA, P34/SOT0, P35/SCK0
Solution
To place the above pins in the Hi-Z state in the standby mode, the pins must
be set by software to general-purpose input ports as follows before
transitioning to a standby mode.
(1) Set “input” using the port data direction register (DDR) for the shared
general-purpose port.
(2) Disable the resource output.
(3) Transition to the standby mode.
hm90590-cm44-10105-6e-corr-x1-00.doc 8 / 8
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