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The following document contains information on Cypress products.
CM44-10106-6ET2
Errata
This errata sheet is for MB90595 Series Hardware Manual Rev. 6 (CM44-10106-6E).
F2MC-16LX
16-BIT MICROCONTROLLER
MB90595 Series
HARDWARE MANUAL
2009.1.6
Date
2009/
1/6
Page
478
Item
APPENDIX
B
Description
■Table B.9-20 XCH Ri, ea Instruction (First Byte = 7EH) is changed.
・Error
Item "A"
Line of +A
"W2+d16,A"
・Correct
Item "A0"
Line of +A "@RW2+d16"
1/1
Corrections of Hardware Manual
MB90595 hm90595-cm44-10106-6e-corr-x1-00
© Fujitsu Microelectronics Europe GmbH
Addendum, MB90595 Hardware Manual (CM44-10106-6E)
This is the Addendum for the Hardware Manual CM44-10106-6E of the MB90595
microcontroller series. It describes all known discrepancies of the MB90595
microcontroller series Hardware Manual.
Ref. Number Date
Version Chapter/Page
No.
Description/Correction
(Text Link) dd.mm.yy
HWM90595001 06.01.03 1.00
15.5.1
HWM90595002 06.01.03
13.3.3
HWM90595003 06.01.03
20
HWM90595004 06.01.03
1.8
HWM90595005 06.01.03
19
HWM90595006 06.01.03
19.7
HWM90595007 06.01.03
1.8
HWM90595004 23.06.03 1.03
1.8
hm90595-cm44-10106-6e-corr-x1-00.doc
Wrong ICR register for A/DC
mentioned
PPG Count clock selection bit:
wrong time scales, wrong bit
identifier
Stepper Motor, information about
Zero Detect register added
Information about Pin state
behaviour during Power-on
CAN, ‘Hit and Away’ description
added
Transmission under CAN
Controller, wrong flowchart
Port State Output in Standby Mode
Information about Pin state
behaviour during Power-on
corrected
1 / 13
HWM90595001
Chapter 15.5.1 Example of EI2OS Activation in single Mode:
Wrong comment below the table:
A/D Converter is located to ICR3 instead of ICR2
HWM90595002
Chapter 13.3.3 PPG0,1 Output Pin Control Register (PPG01)
Incorrect time scales in table, see correction below:
PCS2
0
0
0
0
1
1
PCS1
0
0
1
1
0
0
PCS0
0
1
0
1
0
1
Operation mode
Periphal clock (62,5 ns machine clock, 16MHz)
Periphal clock/2 (125 ns machine clock, 16MHz)
Periphal clock/4 (250 ns machine clock, 16MHz)
Periphal clock/8 (500 ns machine clock, 16MHz)
Periphal clock/16 (1 μs machine clock, 16MHz)
Clock input from the time base timer (128 μs, 4MHz)
This bit is initialised to ‘000‘ upon a reset. This bit is readable and
writable.
Incorrect time scales and wrong bit definition in table, see correction below:
PCM2
0
0
0
0
1
1
PCM1
0
0
1
1
0
0
PCM0
0
1
0
1
0
1
Operation mode
Periphal clock (62,5 ns machine clock, 16MHz)
Periphal clock/2 (125 ns machine clock, 16MHz)
Periphal clock/4 (250 ns machine clock, 16MHz)
Periphal clock/8 (500 ns machine clock, 16MHz)
Periphal clock/16 (1 μs machine clock, 16MHz)
Clock input from the time base timer (128 μs, 4MHz)
This bit is initialised to ‘000‘ upon a reset. This bit is readable and
writable.
hm90595-cm44-10106-6e-corr-x1-00.doc
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HWM90595003
Chapter 20.1 Outline of Stepping Motor Controller
Old:
The Stepping Motor Controller consists of two PWM Pulse Generators, four motor
drivers and the Selector Logic.
The four motor drivers have high output drive capabilities and they can be
directly
connected to the four ends of two motor coils. The combination of the PWM
Pulse
Generators and Selector Logic is designed to control the rotation of the
motor. A
synchronization mechanism assures the synchronous operations of the two PWMs.
The following sections describe the Stepping Motor Controller 0 only. The
other
controllers have the same function. The register addresses are found in the
I/O map.
New:
This Chapter provides an overview of the Stepper Motor Control Module,
describe the register structure and functions, and described the operation of
the Stepper Motor Control Module.
The Stepping Motor Controller consists of two PWM Pulse Generators, four motor
drivers, Selector Logic and the Zero Rotor Position Detector. The four motor
drivers have high output drive capabilities and they can be directly connected
to the four ends of two motor coils. The combination of the PWM Pulse
Generators and Selector Logic is designed to control the rotation of the
motor. A Synchronization mechanism assures the synchronous operaitons of the
two PWMs. The Zero Rotor Position Detector helps CPU obtain feed back
information of the rotor movements. The following sections describe the
Stepping Motor Controller 0 only. The other controllers have the same
functions. The register addresses are found in the I/O map.
<Note> The Rotor Zero Position Detection capability is protected by a patent
from Mannesmann VDO and may only be used with VDO’s prior approval.
hm90595-cm44-10106-6e-corr-x1-00.doc
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•
Stepping Motor Control Block
Additionally Diagram:
Comparator
Debounce logic
8-bit counter
Zero Detect 0 register
+
-
PWM2M0
1/9 AVCC
reference
voltage
power down
Zero Rotor Position Detector
Chapter 20.2 Stepping Motor Control Registers:
Additionally Register ZPDC:
I/O MAP:
Chapter 20.2.4 Zero Detect Register
[bits 15 to 14] S1 to S0 : Debounce clock select bit
These bits specify the clock frequency used for the Debounce logic. The
Debounce logic samples the output of the comparator with the specified clock
frequency.
hm90595-cm44-10106-6e-corr-x1-00.doc
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S1
0
0
1
1
S0
0
1
0
1
Clock input
Machine clock
½ Machine clock
¼ Machine clock
1/8 Machine clock
[bits 13] TS : Time slice bit
This bit enables the operation of the Zero Rotor Position Detector. While this
bit is "1", the Zero Rotor Position Detector compares the input voltage at the
PWM2M0 pin with the reference voltage and sets the RS bit if the input voltage
exceed the reference voltage.
[bits 12 to 10] T2 to T0 : Number of samples
These bits specifies the number of samples for the Debounce logic. The
Debounce logic samples the output of the comparator the specified number of
times. The output of the Debounce logic becomes "1" when all the sampled
values are "1"
T2
T1
T0
Number of
samples
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
1
2
3
4
5
[bits 9] PD : Power down bit
When this bit is set to "1", the power supply to the analog components
(comparator and reference voltage source) is switched off.
age source) is switched off.
[bits 8] RS : Result bit
The RS bit indicates whether the input voltage at the PWM2M0 pin exceeded the
reference voltage.
The RS bit is set to "1" if the output of the Debounce logic becomes "1".
While TS bit is "0", the RS bit always indicates "0".
hm90595-cm44-10106-6e-corr-x1-00.doc
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HWM90595004
Power-On Reset
Output “unknown value” , when the power supply Is turned on If F2MC16LX is used. (Note)
1.Device covered
MB90V595G, MB90598, MB90F598, MB90F598G
2. Note:
During testing it has been found that some port pins may enter an
undefined state during power on. By asserting RSTx during the power on
reset (217 cycles of main clock) port pins can be forced to high
impedance.
1. The following Ports will output a High Impedance (Hi-z) at the
terminal when the power supply is turned on when PONR and RSTX = 1
(RSTx not asserted):
P20 – P45, P50 – P57, P90 – P95
2. The following ports can be forced to high impedance state (Hi-z)
during PONR if RSTX is asserted during power on (217 cycles of main
clock) or with the End of POMR and the Start of the internal clock
P00 – P03, P16 – P17, P46 – P47, P70 – P87
3. The following Ports will output an High-Z with the End of PONR and
the Start of internal clocks. RSTx does not force the pins to High-Z
during power on.
P04 – P15, P60 - P67
Note:
This workaround will work for Mode pin setting 011 (Single chip,
Internal ROM external bus), 110 (Burn_In ROM), 111 (EPROM mode)
Fixed version:
MB90F598G
: fixed after date code 0126-K00
MB90598G
: not affected
hm90595-cm44-10106-6e-corr-x1-00.doc
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The following diagram shows the timing chart in detail.
Oscillation stabilization time
Under “power-on reset”
Vcc (power supply terminal)
“power-on reset” signal
RSTX (external asynchronous reset)
signal
RST (Internal reset) signal
Program Execution
MCLK (main clock) signal
Internal operation clock signal
Hi-z
Output port 0, 1
output “unknown value”
How to output “Hi-z” under “power-on reset”
Input external reset over 217 x oscillation clock frequency
RSTX (external asynchronous reset)
signal
Output port 0, 1
Hi-z
Timing chart
Under “power-on reset” 217 x oscillation clock frequency
(8.192ms in case of oscillation clock frequency = 16MHz)
Waiting time to be stabilized oscillation 218 x oscillation clock frequency
(16.384ms in case of oscillation clock frequency = 16MHz)
hm90595-cm44-10106-6e-corr-x1-00.doc
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HWM90595005
Chapter 19 CAN
‘Hit and Away’ description:
Affected parts:
MB90V595/G, MB90598/G, MB90F598/G
Caution for disabling Message Buffers by BVAL bits
1 Caution for
Reception
1.1 Behaviour
If there is a complete (no error until 6th bit of EOF) incoming message that
have passed the acceptance filter, then this message is stored into a message
buffer x (with x=0…15). If this store operation coincides with reset operation
of the corresponding BVAL bit (BVALx=0), the received message will be stored
into the message buffer 0 regardless of register settings. Note that this
coincidence has to happen within a specific CAN-clock cycle (see event 2 in
figures). Hence, the probability is very low.
If transmission request of buffer 0 is set (TREQ0=1), the above-mentioned
behaviour will lead to the following transmission of a message. This message
consists of the received ID, DLC and Data together with original IDE and RTR
bits set of the message buffer 0.
However, if there are two or more message buffers with passing acceptance
filers for the incoming message and only buffer x is disabled, the message
will be stored into the 2nd prioritised message buffer.
If there are two or more message buffers with passing acceptance filers for
the incoming message and all those buffers are disabled, the message will be
stored into buffer 0.
1.2 Operation to avoid
When disabling message buffers by the BVAL register, it must be avoided that
the write operation to the BVAL register coincides with the store operation of
the received message in the CAN Controller.
The following diagram illustrates the timing to be avoided for the BVAL write
operation.
hm90595-cm44-10106-6e-corr-x1-00.doc
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DLC
Data
dlc
data
Id-Arbitration
CRC
ACK
ID
RTR
ID
SRR
IDE
SOF
idle
EOF
ITM
ID, DLC and DTR are copied to
buffer 0
no RX-flags are set
LEIR (buffer pointer) set to 0
determine one or more
buffers with Hit
16 cycles
64 cycles
3 4
Away
1 Hit
ACK
DEL
idle
EOF6 EOF5 EOF4 EOF3 EOF2 EOF1 EOF0
SYNC_SEG
TSEG1
TSEG2
sample point
RS=1? 0
2
disable all buffers x to y with hit exactly one
CAN-clock cycle after sample point (BVALx..y=0)
c
d
e
f
CAN-controller determines buffers, which can store the message, because
their acceptance filters had been passed.
Software disable all buffers with hit exactly one CAN-clock cycle after
the sample point of EOF1.
CAN-controller stores received ID, DLC and data in buffer 0 regardless
of the buffers determined in c.
CAN-Controller sets LEIR to point to buffer 0 but RX-flags (RCR, ROVR,
RRTRR) are not set.
f
2. Caution for
Transmission
2.1 Behaviour
When there is a pending transmission of buffer x and the CAN bus status is in
Intermission or in Bus Idle, the CAN-controller will load the message from
buffer x in order to send it. If this load operation coincides with disabling
the pending message buffer x by clearing the BVAL bit, this results in
transmission of a Standard message. This message consists of RTR=0, IDE=0,
DLC, 11 ID bits and Data stored in the message buffer 0.
Note that this coincidence has to happen with in a specific CAN-clock cycle.
Hence, the probability is very low. The position of that cycle depends also on
previous frame reception and occurrence of error frames.
2.2 Operation to avoid
When disabling message buffers by the BVAL register, it must be avoided that
the write operation to the BVAL register coincides with the preparation for
the next transmission in the CAN Controller.
The following diagram illustrates the timing to be avoided for the BVAL write
operation.
hm90595-cm44-10106-6e-corr-x1-00.doc
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DLC
Data
dlc
data
CRC
ACK
ID
RTR
ID
SRR
IDE
SOF
idle
...
EOF
ITM
idle
5
Id-Arbitration
TREQx=1
TREQx=1
6
EOF-SOF
BVALx=0
BVALx=0
7
Hit
8
Away
LEIR set to buffer 0
TCR remains unchanged
transmit standard data frame with
ID, DLC and data of buffer 0
g
h
i
j
Software requests transmission of buffer x by setting TREQx.
Software disables the buffer x by clearing BVALx.
CAN-controller transmits a standard data frame with ID, length code and
data of buffer 0.
After completion of frame only LEIR is updated for buffer 0. However,
TCR is not set (neither for buffer 0 nor for buffer x).
3. Correct Operation
3.1 Operation for re-configuring receive message buffers
Depending on CAN applications, it may be necessary to re-configure message
buffers after receiving messages through the already active CAN communication.
While the CAN bus is active, it is necessary to follow one of the two
operations described below to re-configure message buffers by ID, AMS and
AMR0/1 register settings. "Active" means that read value of the HALT bit is 0
and the CAN Controller is ready to receive and transmit messages.
1.1.1 Use of HALT bit
Write 1 to the HALT bit and read it back for checking the result is 1. Then
change settings for the ID/AMS/AMR0/1 registers.
1.1.2 No use of Message Buffer 0
Do not use the message buffer 0. In other words, disable message buffer
(BVAL=0), prohibit receive interrupt (RIE=0) and do not request transmission
(TREQ=0).
3.2 Operation for processing received message.
When reading a received message from a message buffer, consideration must be
given for possible over-write operation by next incoming messages.
Disabling receive operation by the BVAL bit must not be used for this purpose.
Use the ROVR bit for checking, if over-writing has been performed. For
details, refer to description of ROVR in the hardware manual.
hm90595-cm44-10106-6e-corr-x1-00.doc
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3.3 Cancellation of transmission request
Do not use the BVAL bit for suppressing/cancellation of transmission request.
The TCANR bit is prepared for this purpose.
3.4 Composing transmission message
When composing a transmission message by writing to ID, data and other
registers, the message buffer should be disabled by the BVAL bit.
In this case, the BVAL bit should reset (BVAL=0) after checking if the TREQ
bit is 0 or after completion of the previous message transmission (TC=1).
4. Example of avoiding Hit-And-Away
1.
Do not use message buffer 0. Keep it always disabled (BVAL0 = 0).
By not using buffer 0 the processing of wrongly received messages in buffer
0 is avoided. Even if data are received in this buffer, they have no
influence.
2.
Set an unused 11-Bit identifier in buffer 0.
"Unused" means that the identifier has no meaning to any node in the
network. If an invalid standard data frame is sent according to the
condition described in "0
2. Caution for Transmission", that frame must not cause misoperation of other
nodes.
3.
Use overrun test while processing a received message.
After temporarily saving received message, test for overrun (ROVRR). If
overrun occurred, read the buffer again, because the read data before
overrun could be inconsistent.
4.
Wait for completion of transmission.
A buffer must not be disabled by clearing the BVAL-flag, as long as there
is a pending transmission. Easiest way to wait for transmission completion
is to use transmission interrupt but polling of TREQ is also possible.
hm90595-cm44-10106-6e-corr-x1-00.doc
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HWM90595006
Chapter 19.7 Transmission under CAN Controller
Figure 19.7-1 CAN Controller Transmission Flowchart
Wrong Flowchart used, see correction below.
hm90595-cm44-10106-6e-corr-x1-00.doc
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HWM90595007
Port State Output in Standby Mode
The following problem has been found for the MB90595 Series of products for
some pins serving as a resource output and general-purpose port when a
transition is made to a standby mode (stop mode or time-base timer mode) with
the resource output enabled, the pins are not placed in the Hi-Z state
although the pin state setting bit is Hi-Z (SPL bit = 1).
When a transition is made to a standby mode with the following states
established, the pins shown in the table below are not placed in the Hi-Z
state; they remain in the resource output state.
State setting: Resource output enabled
SPL bit = 1 (Port state is Hi-Z setting in standby mode)
Products
MB90V595/G,
MB90F598/G,
MB90598/G
Pins not placed in Hi-Z state in standby mode
P04/OUT0, P05/OUT1, P06/OUT2, P07/OUT3, P10/PPG0,
P11/PPG1, P12/PPG2, P13/PPG3, P14/PPG4, P15/PPG5, P17/TOT1
Solution
To place the above pins in the Hi-Z state in the standby mode, the pins must
be set by software to general-purpose input ports as follows before
transitioning to a standby mode.
(1) Set “input” using the port data direction register (DDR) for the shared
general-purpose port.
(2) Disable the resource output.
(3) Transition to the standby mode.
hm90595-cm44-10106-6e-corr-x1-00.doc
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